2012-03-26 19:18:29 +00:00
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/* spu.h -- Assembler for spu
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2017-04-10 11:32:00 +00:00
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Copyright (C) 2006-2017 Free Software Foundation, Inc.
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2012-03-26 19:18:29 +00:00
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#ifndef TC_SPU
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#define TC_SPU 1
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#include "opcode/spu.h"
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#define TARGET_FORMAT "elf32-spu"
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#define TARGET_ARCH bfd_arch_spu
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#define TARGET_NAME "elf32-spu"
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#define TARGET_BYTES_BIG_ENDIAN 1
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struct tc_fix_info {
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unsigned short arg_format;
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unsigned short insn_tag;
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};
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/* fixS will have a member named tc_fix_data of this type. */
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#define TC_FIX_TYPE struct tc_fix_info
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#define TC_INIT_FIX_DATA(FIXP) \
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do \
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{ \
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(FIXP)->tc_fix_data.arg_format = 0; \
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(FIXP)->tc_fix_data.insn_tag = 0; \
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} \
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while (0)
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/* Don't reduce function symbols to section symbols, and don't adjust
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references to PPU symbols. */
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#define tc_fix_adjustable(FIXP) \
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(!(S_IS_FUNCTION ((FIXP)->fx_addsy) \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_ADD_PIC))
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/* Keep relocs on calls. Branches to function symbols are tail or
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sibling calls. */
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#define TC_FORCE_RELOCATION(FIXP) \
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((FIXP)->tc_fix_data.insn_tag == M_BRSL \
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|| (FIXP)->tc_fix_data.insn_tag == M_BRASL \
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|| (((FIXP)->tc_fix_data.insn_tag == M_BR \
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|| (FIXP)->tc_fix_data.insn_tag == M_BRA) \
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&& (FIXP)->fx_addsy != NULL \
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&& S_IS_FUNCTION ((FIXP)->fx_addsy)) \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64 \
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|| (FIXP)->fx_r_type == BFD_RELOC_SPU_ADD_PIC \
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|| generic_force_reloc (FIXP))
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/* Values passed to md_apply_fix don't include symbol values. */
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#define MD_APPLY_SYM_VALUE(FIX) 0
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/* The spu uses pseudo-ops with no leading period. */
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#define NO_PSEUDO_DOT 1
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/* Don't warn on word overflow; it happens on %hi relocs. */
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#undef WARN_SIGNED_OVERFLOW_WORD
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#define DIFF_EXPR_OK
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#define WORKING_DOT_WORD
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#define md_number_to_chars number_to_chars_bigendian
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#define md_convert_frag(b,s,f) {as_fatal (_("spu convert_frag\n"));}
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/* We don't need to do anything special for undefined symbols. */
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#define md_undefined_symbol(s) 0
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extern symbolS *section_symbol (asection *);
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#define md_operand(e) \
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do { \
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if (strncasecmp (input_line_pointer, "@ppu", 4) == 0) \
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{ \
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e->X_op = O_symbol; \
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if (abs_section_sym == NULL) \
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abs_section_sym = section_symbol (absolute_section); \
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e->X_add_symbol = abs_section_sym; \
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e->X_add_number = 0; \
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} \
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} while (0)
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/* Fill in rs_align_code fragments. */
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extern void spu_handle_align (fragS *);
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#define HANDLE_ALIGN(frag) spu_handle_align (frag)
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#define MAX_MEM_FOR_RS_ALIGN_CODE (7 + 8)
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#endif /* TC_SPU */
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