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Revert "switch from binutils only to binutils-gdb, tag gdb-10.1-release"
This reverts commit 6c5c652ee1.
This commit is contained in:
Wolfgang Thaller
@@ -1,5 +1,5 @@
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/* ppc.h -- Header file for PowerPC opcode table
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Copyright (C) 1994-2020 Free Software Foundation, Inc.
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Copyright (C) 1994-2018 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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@@ -30,6 +30,14 @@ extern "C" {
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typedef uint64_t ppc_cpu_t;
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#if BFD_HOST_64BIT_LONG
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# define PPC_INT_FMT "l"
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#elif defined (__MSVCRT__)
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# define PPC_INT_FMT "I64"
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#else
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# define PPC_INT_FMT "ll"
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#endif
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/* The opcode table is an array of struct powerpc_opcode. */
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struct powerpc_opcode
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@@ -68,8 +76,6 @@ struct powerpc_opcode
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instructions. */
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extern const struct powerpc_opcode powerpc_opcodes[];
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extern const unsigned int powerpc_num_opcodes;
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extern const struct powerpc_opcode prefix_opcodes[];
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extern const unsigned int prefix_num_opcodes;
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extern const struct powerpc_opcode vle_opcodes[];
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extern const unsigned int vle_num_opcodes;
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extern const struct powerpc_opcode spe2_opcodes[];
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@@ -198,7 +204,7 @@ extern const unsigned int spe2_num_opcodes;
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/* Opcode is only supported by Power8 architecture. */
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#define PPC_OPCODE_POWER8 0x1000000000ull
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/* Opcode is supported by ppc750cl/Gekko/Broadway. */
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/* Opcode is supported by ppc750cl. */
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#define PPC_OPCODE_750 0x2000000000ull
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/* Opcode is supported by ppc7450. */
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@@ -228,9 +234,6 @@ extern const unsigned int spe2_num_opcodes;
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/* Opcode is supported by EFS2. */
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#define PPC_OPCODE_EFS2 0x200000000000ull
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/* Opcode is only supported by power10 architecture. */
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#define PPC_OPCODE_POWER10 0x400000000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@@ -248,19 +251,6 @@ extern const unsigned int spe2_num_opcodes;
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/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
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#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
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/* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
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#define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
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/* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
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#define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
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/* A macro to determine whether insn I is an 8-byte prefix instruction. */
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#define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
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/* A macro used to hash 8-byte PREFIX instructions. */
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#define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
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/* The operands table is an array of struct powerpc_operand. */
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@@ -290,10 +280,11 @@ struct powerpc_operand
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the operand value is illegal, *ERRMSG
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will be set to a warning string (the operand will be inserted in
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any case). If the operand value is legal, *ERRMSG will be
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unchanged (most operands can accept any value). */
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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uint64_t (*insert)
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(uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
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@@ -311,18 +302,11 @@ struct powerpc_operand
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is the result).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand.
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*INVALID will be set to one by the extraction function if this
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operand type can not be extracted from this operand (i.e., the
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instruction does not match). If the operand is valid, *INVALID
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will not be changed. *INVALID will always be non-negative when
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used to extract a field from an instruction.
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The extraction function is also called by both the assembler and
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disassembler if an operand is optional, in which case the
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function should return the default value of the operand.
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*INVALID is negative in this case, and is the negative count of
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omitted optional operands up to and including this operand. */
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
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/* One bit syntax flags. */
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@@ -362,9 +346,6 @@ extern const unsigned int num_powerpc_operands;
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x10)
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/* This operand names a VSX accumulator. */
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#define PPC_OPERAND_ACC (0x20)
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/* This operand may use the symbolic names for the CR fields (even
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without -mregnames), which are
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lt 0 gt 1 eq 2 so 3 un 3
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@@ -372,60 +353,57 @@ extern const unsigned int num_powerpc_operands;
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cr4 4 cr5 5 cr6 6 cr7 7
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These may be combined arithmetically, as in cr2*4+gt. These are
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only supported on the PowerPC, not the POWER. */
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#define PPC_OPERAND_CR_BIT (0x40)
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#define PPC_OPERAND_CR_BIT (0x20)
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/* This is a CR FIELD that does not use symbolic names (unless
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-mregnames is in effect). If both PPC_OPERAND_CR_BIT and
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PPC_OPERAND_CR_REG are set then treat the field as per
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PPC_OPERAND_CR_BIT for assembly, but as if neither of these
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bits are set for disassembly. */
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#define PPC_OPERAND_CR_REG (0x80)
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-mregnames is in effect). */
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#define PPC_OPERAND_CR_REG (0x40)
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/* This operand names a special purpose register. */
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#define PPC_OPERAND_SPR (0x100)
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#define PPC_OPERAND_SPR (0x80)
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/* This operand names a paired-single graphics quantization register. */
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#define PPC_OPERAND_GQR (0x200)
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#define PPC_OPERAND_GQR (0x100)
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_RELATIVE (0x400)
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#define PPC_OPERAND_RELATIVE (0x200)
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_ABSOLUTE (0x800)
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#define PPC_OPERAND_ABSOLUTE (0x400)
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/* This operand takes signed values. */
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#define PPC_OPERAND_SIGNED (0x1000)
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#define PPC_OPERAND_SIGNED (0x800)
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/* This operand takes signed values, but also accepts a full positive
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range of values when running in 32 bit mode. That is, if bits is
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16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
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this flag is ignored. */
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#define PPC_OPERAND_SIGNOPT (0x2000)
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#define PPC_OPERAND_SIGNOPT (0x1000)
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/* The next operand should be wrapped in parentheses rather than
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separated from this one by a comma. This is used for the load and
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store instructions which want their operands to look like
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reg,displacement(reg)
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*/
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#define PPC_OPERAND_PARENS (0x4000)
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#define PPC_OPERAND_PARENS (0x2000)
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/* This operand is for the DS field in a DS form instruction. */
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#define PPC_OPERAND_DS (0x8000)
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#define PPC_OPERAND_DS (0x4000)
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (0x10000)
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#define PPC_OPERAND_DQ (0x8000)
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define PPC_OPERAND_NEGATIVE (0x20000)
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#define PPC_OPERAND_NEGATIVE (0x10000)
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/* Valid range of operand is 0..n rather than 0..n-1. */
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#define PPC_OPERAND_PLUS1 (0x40000)
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#define PPC_OPERAND_PLUS1 (0x20000)
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/* This operand is optional, and is zero if omitted. This is used for
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example, in the optional BF field in the comparison instructions. The
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@@ -443,6 +421,11 @@ extern const unsigned int num_powerpc_operands;
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out regardless of the PPC_OPERAND_OPTIONAL field. */
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#define PPC_OPERAND_NEXT (0x100000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then the value it should use for the operand is stored
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in the SHIFT field of the immediatly following operand field. */
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#define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
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only optional when generating 32-bit code. */
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#define PPC_OPERAND_OPTIONAL32 (0x400000)
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@@ -481,19 +464,14 @@ extern const int powerpc_num_macros;
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extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
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static inline int64_t
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ppc_optional_operand_value (const struct powerpc_operand *operand,
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uint64_t insn,
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ppc_cpu_t dialect,
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int num_optional)
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ppc_optional_operand_value (const struct powerpc_operand *operand)
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{
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if (operand->extract)
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return (*operand->extract) (insn, dialect, &num_optional);
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if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
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return (operand+1)->shift;
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return 0;
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}
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/* PowerPC VLE insns. */
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#define E_OPCODE_MASK 0xfc00f800
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/* Form I16L, uses 16A relocs. */
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#define E_OR2I_INSN 0x7000C000
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#define E_AND2I_DOT_INSN 0x7000C800
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@@ -510,9 +488,6 @@ ppc_optional_operand_value (const struct powerpc_operand *operand,
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#define E_CMPH16I_INSN 0x7000B000
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#define E_CMPHL16I_INSN 0x7000B800
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#define E_LI_INSN 0x70000000
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#define E_LI_MASK 0xfc008000
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#ifdef __cplusplus
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}
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#endif
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