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362 lines
12 KiB
C
362 lines
12 KiB
C
/* DWARF2 EH unwinding support for PA HP-UX.
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Copyright (C) 2005-2017 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Do code reading to identify a signal frame, and set the frame
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state data appropriately. See unwind-dw2.c for the structs. */
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/* Don't use this if inhibit_libc is set.
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The build for this target will fail trying to include missing headers. */
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#ifndef inhibit_libc
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#include <signal.h>
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#include <sys/ucontext.h>
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#include <unistd.h>
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/* FIXME: We currently ignore the high halves of general, space and
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control registers on PA 2.0 machines for applications using the
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32-bit runtime. We don't restore space registers or the floating
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point status registers. */
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#define MD_FALLBACK_FRAME_STATE_FOR pa_fallback_frame_state
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/* HP-UX 10.X doesn't define GetSSReg. */
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#ifndef GetSSReg
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#define GetSSReg(ssp, ss_reg) \
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((UseWideRegs (ssp)) \
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? (ssp)->ss_wide.ss_32.ss_reg ## _lo \
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: (ssp)->ss_narrow.ss_reg)
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#endif
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#if TARGET_64BIT
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#define GetSSRegAddr(ssp, ss_reg) ((long) &((ssp)->ss_wide.ss_64.ss_reg))
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#else
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#define GetSSRegAddr(ssp, ss_reg) \
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((UseWideRegs (ssp)) \
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? (long) &((ssp)->ss_wide.ss_32.ss_reg ## _lo) \
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: (long) &((ssp)->ss_narrow.ss_reg))
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#endif
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#define UPDATE_FS_FOR_SAR(FS, N) \
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(FS)->regs.reg[N].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[N].loc.offset = GetSSRegAddr (mc, ss_cr11) - new_cfa
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#define UPDATE_FS_FOR_GR(FS, GRN, N) \
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(FS)->regs.reg[N].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[N].loc.offset = GetSSRegAddr (mc, ss_gr##GRN) - new_cfa
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#define UPDATE_FS_FOR_FR(FS, FRN, N) \
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(FS)->regs.reg[N].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[N].loc.offset = (long) &(mc->ss_fr##FRN) - new_cfa;
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#define UPDATE_FS_FOR_PC(FS, N) \
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(FS)->regs.reg[N].how = REG_SAVED_OFFSET; \
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(FS)->regs.reg[N].loc.offset = GetSSRegAddr (mc, ss_pcoq_head) - new_cfa
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/* Extract bit field from word using HP's numbering (MSB = 0). */
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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static inline int
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sign_extend (int x, int len)
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{
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int signbit = (1 << (len - 1));
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int mask = (signbit << 1) - 1;
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return ((x & mask) ^ signbit) - signbit;
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}
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/* Extract a 17-bit signed constant from branch instructions. */
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static inline int
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extract_17 (unsigned word)
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{
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return sign_extend (GET_FIELD (word, 19, 28)
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| GET_FIELD (word, 29, 29) << 10
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| GET_FIELD (word, 11, 15) << 11
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| (word & 0x1) << 16, 17);
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}
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/* Extract a 22-bit signed constant from branch instructions. */
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static inline int
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extract_22 (unsigned word)
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{
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return sign_extend (GET_FIELD (word, 19, 28)
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| GET_FIELD (word, 29, 29) << 10
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| GET_FIELD (word, 11, 15) << 11
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| GET_FIELD (word, 6, 10) << 16
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| (word & 0x1) << 21, 22);
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}
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static _Unwind_Reason_Code
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pa_fallback_frame_state (struct _Unwind_Context *context,
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_Unwind_FrameState *fs)
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{
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static long cpu;
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unsigned int *pc = (unsigned int *) context->ra;
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if (pc == 0)
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return _URC_END_OF_STACK;
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/* Check for relocation of the return value. */
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if (!TARGET_64BIT
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&& *(pc + 0) == 0x2fd01224 /* fstd,ma fr4,8(sp) */
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&& *(pc + 1) == 0x0fd9109d /* ldw -4(sp),ret1 */
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&& *(pc + 2) == 0x0fd130bc) /* ldw,mb -8(sp),ret0 */
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pc += 3;
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else if (!TARGET_64BIT
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&& *(pc + 0) == 0x27d01224 /* fstw,ma fr4,8(sp) */
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&& *(pc + 1) == 0x0fd130bc) /* ldw,mb -8(sp),ret0 */
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pc += 2;
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else if (!TARGET_64BIT
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&& *(pc + 0) == 0x0fdc12b0 /* stw,ma ret0,8(sp) */
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&& *(pc + 1) == 0x0fdd1299 /* stw ret1,-4(sp) */
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&& *(pc + 2) == 0x2fd13024) /* fldd,mb -8(sp),fr4 */
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pc += 3;
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else if (!TARGET_64BIT
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&& *(pc + 0) == 0x0fdc12b0 /* stw,ma ret0,8(sp) */
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&& *(pc + 1) == 0x27d13024) /* fldw,mb -8(sp),fr4 */
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pc += 2;
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/* Check if the return address points to an export stub (PA 1.1 or 2.0). */
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if ((!TARGET_64BIT
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&& *(pc + 0) == 0x4bc23fd1 /* ldw -18(sp),rp */
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&& *(pc + 1) == 0x004010a1 /* ldsid (rp),r1 */
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&& *(pc + 2) == 0x00011820 /* mtsp r1,sr0 */
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&& *(pc + 3) == 0xe0400002) /* be,n 0(sr0,rp) */
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||
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(!TARGET_64BIT
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&& *(pc + 0) == 0x4bc23fd1 /* ldw -18(sp),rp */
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&& *(pc + 1) == 0xe840d002)) /* bve,n (rp) */
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{
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_reg = 30;
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fs->regs.cfa_offset = 0;
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fs->retaddr_column = 0;
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fs->regs.reg[0].how = REG_SAVED_OFFSET;
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fs->regs.reg[0].loc.offset = -24;
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/* Update context to describe the stub frame. */
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uw_update_context (context, fs);
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/* Set up fs to describe the FDE for the caller of this stub. */
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return uw_frame_state_for (context, fs);
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}
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/* Check if the return address points to a relocation stub. */
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else if (!TARGET_64BIT
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&& *(pc + 0) == 0x0fd11082 /* ldw -8(sp),rp */
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&& (*(pc + 1) == 0xe840c002 /* bv,n r0(rp) */
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|| *(pc + 1) == 0xe840d002)) /* bve,n (rp) */
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{
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_reg = 30;
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fs->regs.cfa_offset = 0;
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fs->retaddr_column = 0;
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fs->regs.reg[0].how = REG_SAVED_OFFSET;
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fs->regs.reg[0].loc.offset = -8;
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/* Update context to describe the stub frame. */
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uw_update_context (context, fs);
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/* Set up fs to describe the FDE for the caller of this stub. */
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return uw_frame_state_for (context, fs);
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}
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/* Check if the return address is an export stub as signal handlers
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may return via an export stub. */
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if (!TARGET_64BIT
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&& (*pc & 0xffe0e002) == 0xe8400000 /* bl x,r2 */
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&& *(pc + 1) == 0x08000240 /* nop */
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&& *(pc + 2) == 0x4bc23fd1 /* ldw -18(sp),rp */
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&& *(pc + 3) == 0x004010a1 /* ldsid (rp),r1 */
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&& *(pc + 4) == 0x00011820 /* mtsp r1,sr0 */
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&& *(pc + 5) == 0xe0400002) /* be,n 0(sr0,rp) */
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/* Extract target address from PA 1.x 17-bit branch. */
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pc += extract_17 (*pc) + 2;
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else if (!TARGET_64BIT
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&& (*pc & 0xfc00e002) == 0xe800a000 /* b,l x,r2 */
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&& *(pc + 1) == 0x08000240 /* nop */
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&& *(pc + 2) == 0x4bc23fd1 /* ldw -18(sp),rp */
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&& *(pc + 3) == 0xe840d002) /* bve,n (rp) */
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/* Extract target address from PA 2.0 22-bit branch. */
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pc += extract_22 (*pc) + 2;
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/* Now check if the return address is one of the signal handler
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returns, _sigreturn or _sigsetreturn. */
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if ((TARGET_64BIT
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&& *(pc + 0) == 0x53db3f51 /* ldd -58(sp),dp */
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&& *(pc + 8) == 0x34160116 /* ldi 8b,r22 */
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&& *(pc + 9) == 0x08360ac1 /* shladd,l r22,3,r1,r1 */
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&& *(pc + 10) == 0x0c2010c1 /* ldd 0(r1),r1 */
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&& *(pc + 11) == 0xe4202000) /* be,l 0(sr4,r1) */
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||
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(TARGET_64BIT
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&& *(pc + 0) == 0x36dc0000 /* ldo 0(r22),ret0 */
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&& *(pc + 6) == 0x341601c0 /* ldi e0,r22 */
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&& *(pc + 7) == 0x08360ac1 /* shladd,l r22,3,r1,r1 */
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&& *(pc + 8) == 0x0c2010c1 /* ldd 0(r1),r1 */
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&& *(pc + 9) == 0xe4202000) /* be,l 0(sr4,r1) */
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||
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(!TARGET_64BIT
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&& *(pc + 0) == 0x379a0000 /* ldo 0(ret0),r26 */
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&& *(pc + 1) == 0x6bd33fc9 /* stw r19,-1c(sp) */
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&& *(pc + 2) == 0x20200801 /* ldil L%-40000000,r1 */
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&& *(pc + 3) == 0xe420e008 /* be,l 4(sr7,r1) */
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&& *(pc + 4) == 0x34160116) /* ldi 8b,r22 */
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||
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(!TARGET_64BIT
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&& *(pc + 0) == 0x6bd33fc9 /* stw r19,-1c(sp) */
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&& *(pc + 1) == 0x20200801 /* ldil L%-40000000,r1 */
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&& *(pc + 2) == 0xe420e008 /* be,l 4(sr7,r1) */
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&& *(pc + 3) == 0x341601c0)) /* ldi e0,r22 */
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{
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/* The previous stack pointer is saved at (long *)SP - 1. The
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ucontext structure is offset from the start of the previous
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frame by the siglocal_misc structure. */
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struct siglocalx *sl = (struct siglocalx *)
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(*((long *) context->cfa - 1));
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mcontext_t *mc = &(sl->sl_uc.uc_mcontext);
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long new_cfa = GetSSReg (mc, ss_sp);
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fs->regs.cfa_how = CFA_REG_OFFSET;
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fs->regs.cfa_reg = 30;
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fs->regs.cfa_offset = new_cfa - (long) context->cfa;
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UPDATE_FS_FOR_GR (fs, 1, 1);
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UPDATE_FS_FOR_GR (fs, 2, 2);
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UPDATE_FS_FOR_GR (fs, 3, 3);
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UPDATE_FS_FOR_GR (fs, 4, 4);
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UPDATE_FS_FOR_GR (fs, 5, 5);
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UPDATE_FS_FOR_GR (fs, 6, 6);
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UPDATE_FS_FOR_GR (fs, 7, 7);
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UPDATE_FS_FOR_GR (fs, 8, 8);
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UPDATE_FS_FOR_GR (fs, 9, 9);
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UPDATE_FS_FOR_GR (fs, 10, 10);
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UPDATE_FS_FOR_GR (fs, 11, 11);
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UPDATE_FS_FOR_GR (fs, 12, 12);
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UPDATE_FS_FOR_GR (fs, 13, 13);
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UPDATE_FS_FOR_GR (fs, 14, 14);
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UPDATE_FS_FOR_GR (fs, 15, 15);
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UPDATE_FS_FOR_GR (fs, 16, 16);
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UPDATE_FS_FOR_GR (fs, 17, 17);
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UPDATE_FS_FOR_GR (fs, 18, 18);
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UPDATE_FS_FOR_GR (fs, 19, 19);
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UPDATE_FS_FOR_GR (fs, 20, 20);
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UPDATE_FS_FOR_GR (fs, 21, 21);
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UPDATE_FS_FOR_GR (fs, 22, 22);
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UPDATE_FS_FOR_GR (fs, 23, 23);
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UPDATE_FS_FOR_GR (fs, 24, 24);
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UPDATE_FS_FOR_GR (fs, 25, 25);
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UPDATE_FS_FOR_GR (fs, 26, 26);
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UPDATE_FS_FOR_GR (fs, 27, 27);
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UPDATE_FS_FOR_GR (fs, 28, 28);
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UPDATE_FS_FOR_GR (fs, 29, 29);
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UPDATE_FS_FOR_GR (fs, 30, 30);
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UPDATE_FS_FOR_GR (fs, 31, 31);
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if (TARGET_64BIT)
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{
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UPDATE_FS_FOR_FR (fs, 4, 32);
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UPDATE_FS_FOR_FR (fs, 5, 33);
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UPDATE_FS_FOR_FR (fs, 6, 34);
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UPDATE_FS_FOR_FR (fs, 7, 35);
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UPDATE_FS_FOR_FR (fs, 8, 36);
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UPDATE_FS_FOR_FR (fs, 9, 37);
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UPDATE_FS_FOR_FR (fs, 10, 38);
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UPDATE_FS_FOR_FR (fs, 11, 39);
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UPDATE_FS_FOR_FR (fs, 12, 40);
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UPDATE_FS_FOR_FR (fs, 13, 41);
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UPDATE_FS_FOR_FR (fs, 14, 42);
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UPDATE_FS_FOR_FR (fs, 15, 43);
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UPDATE_FS_FOR_FR (fs, 16, 44);
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UPDATE_FS_FOR_FR (fs, 17, 45);
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UPDATE_FS_FOR_FR (fs, 18, 46);
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UPDATE_FS_FOR_FR (fs, 19, 47);
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UPDATE_FS_FOR_FR (fs, 20, 48);
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UPDATE_FS_FOR_FR (fs, 21, 49);
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UPDATE_FS_FOR_FR (fs, 22, 50);
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UPDATE_FS_FOR_FR (fs, 23, 51);
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UPDATE_FS_FOR_FR (fs, 24, 52);
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UPDATE_FS_FOR_FR (fs, 25, 53);
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UPDATE_FS_FOR_FR (fs, 26, 54);
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UPDATE_FS_FOR_FR (fs, 27, 55);
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UPDATE_FS_FOR_FR (fs, 28, 56);
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UPDATE_FS_FOR_FR (fs, 29, 57);
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UPDATE_FS_FOR_FR (fs, 30, 58);
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UPDATE_FS_FOR_FR (fs, 31, 59);
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UPDATE_FS_FOR_SAR (fs, 60);
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}
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else
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{
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UPDATE_FS_FOR_FR (fs, 4, 32);
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UPDATE_FS_FOR_FR (fs, 5, 34);
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UPDATE_FS_FOR_FR (fs, 6, 36);
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UPDATE_FS_FOR_FR (fs, 7, 38);
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UPDATE_FS_FOR_FR (fs, 8, 40);
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UPDATE_FS_FOR_FR (fs, 9, 44);
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UPDATE_FS_FOR_FR (fs, 10, 44);
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UPDATE_FS_FOR_FR (fs, 11, 46);
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UPDATE_FS_FOR_FR (fs, 12, 48);
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UPDATE_FS_FOR_FR (fs, 13, 50);
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UPDATE_FS_FOR_FR (fs, 14, 52);
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UPDATE_FS_FOR_FR (fs, 15, 54);
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if (!cpu)
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cpu = sysconf (_SC_CPU_VERSION);
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/* PA-RISC 1.0 only has 16 floating point registers. */
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if (cpu != CPU_PA_RISC1_0)
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{
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UPDATE_FS_FOR_FR (fs, 16, 56);
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UPDATE_FS_FOR_FR (fs, 17, 58);
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UPDATE_FS_FOR_FR (fs, 18, 60);
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UPDATE_FS_FOR_FR (fs, 19, 62);
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UPDATE_FS_FOR_FR (fs, 20, 64);
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UPDATE_FS_FOR_FR (fs, 21, 66);
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UPDATE_FS_FOR_FR (fs, 22, 68);
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UPDATE_FS_FOR_FR (fs, 23, 70);
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UPDATE_FS_FOR_FR (fs, 24, 72);
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UPDATE_FS_FOR_FR (fs, 25, 74);
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UPDATE_FS_FOR_FR (fs, 26, 76);
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UPDATE_FS_FOR_FR (fs, 27, 78);
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UPDATE_FS_FOR_FR (fs, 28, 80);
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UPDATE_FS_FOR_FR (fs, 29, 82);
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UPDATE_FS_FOR_FR (fs, 30, 84);
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UPDATE_FS_FOR_FR (fs, 31, 86);
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}
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UPDATE_FS_FOR_SAR (fs, 88);
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}
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fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
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UPDATE_FS_FOR_PC (fs, __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__);
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fs->signal_frame = 1;
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return _URC_NO_REASON;
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}
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return _URC_END_OF_STACK;
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}
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#endif /* inhibit_libc */
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