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https://github.com/autc04/Retro68.git
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284 lines
13 KiB
C
284 lines
13 KiB
C
/* Table of opcodes for the DLX microprocess.
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Copyright (C) 2002-2017 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA.
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Initially created by Kuang Hwa Lin, 2002. */
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/* Following are the function codes for the Special OP (ALU). */
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#define ALUOP 0x00000000
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#define SPECIALOP 0x00000000
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#define NOPF 0x00000000
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#define SLLF 0x00000004
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#define SRLF 0x00000006
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#define SRAF 0x00000007
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#define SEQUF 0x00000010
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#define SNEUF 0x00000011
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#define SLTUF 0x00000012
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#define SGTUF 0x00000013
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#define SLEUF 0x00000014
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#define SGEUF 0x00000015
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#define ADDF 0x00000020
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#define ADDUF 0x00000021
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#define SUBF 0x00000022
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#define SUBUF 0x00000023
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#define ANDF 0x00000024
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#define ORF 0x00000025
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#define XORF 0x00000026
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#define SEQF 0x00000028
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#define SNEF 0x00000029
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#define SLTF 0x0000002A
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#define SGTF 0x0000002B
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#define SLEF 0x0000002C
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#define SGEF 0x0000002D
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/* Following special functions was not mentioned in the
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Hennessy's book but was implemented in the RTL. */
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#define MVTSF 0x00000030
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#define MVFSF 0x00000031
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#define BSWAPF 0x00000032
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#define LUTF 0x00000033
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/* Following special functions was mentioned in the
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Hennessy's book but was not implemented in the RTL. */
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#define MULTF 0x00000005
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#define MULTUF 0x00000006
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#define DIVF 0x00000007
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#define DIVUF 0x00000008
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/* Following are the rest of the OPcodes:
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JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26)
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ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26)
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ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26)
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RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26)
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BREAKOP= (0x014 << 26)
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SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26)
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SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26)
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LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26)
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LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26)
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LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26),
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SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26)
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SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26)
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SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */
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#define JOP 0x08000000
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#define JALOP 0x0c000000
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#define BEQOP 0x10000000
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#define BNEOP 0x14000000
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#define ADDIOP 0x20000000
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#define ADDUIOP 0x24000000
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#define SUBIOP 0x28000000
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#define SUBUIOP 0x2c000000
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#define ANDIOP 0x30000000
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#define ORIOP 0x34000000
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#define XORIOP 0x38000000
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#define LHIOP 0x3c000000
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#define RFEOP 0x40000000
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#define TRAPOP 0x44000000
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#define JROP 0x48000000
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#define JALROP 0x4c000000
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#define BREAKOP 0x50000000
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#define SEQIOP 0x60000000
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#define SNEIOP 0x64000000
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#define SLTIOP 0x68000000
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#define SGTIOP 0x6c000000
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#define SLEIOP 0x70000000
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#define SGEIOP 0x74000000
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#define LBOP 0x80000000
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#define LHOP 0x84000000
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#define LWOP 0x8c000000
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#define LBUOP 0x90000000
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#define LHUOP 0x94000000
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#define LDSTBU
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#define LDSTHU
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#define SBOP 0xa0000000
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#define SHOP 0xa4000000
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#define SWOP 0xac000000
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#define LDST
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#define SEQUIOP 0xc0000000
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#define SNEUIOP 0xc4000000
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#define SLTUIOP 0xc8000000
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#define SGTUIOP 0xcc000000
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#define SLEUIOP 0xd0000000
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#define SGEUIOP 0xd4000000
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#define SLLIOP 0xd8000000
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#define SRLIOP 0xdc000000
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#define SRAIOP 0xe0000000
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/* Following 3 ops was added to provide the MP atonmic operation. */
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#define LSBUOP 0x98000000
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#define LSHUOP 0x9c000000
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#define LSWOP 0xb0000000
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/* Following opcode was defined in the Hennessy's book as
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"normal" opcode but was implemented in the RTL as special
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functions. */
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#if 0
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#define MVTSOP 0x50000000
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#define MVFSOP 0x54000000
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#endif
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struct dlx_opcode
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{
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/* Name of the instruction. */
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const char *name;
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/* Opcode word. */
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unsigned long opcode;
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/* A string of characters which describe the operands.
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Valid characters are:
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, Itself. The character appears in the assembly code.
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a rs1 The register number is in bits 21-25 of the instruction.
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b rs2/rd The register number is in bits 16-20 of the instruction.
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c rd. The register number is in bits 11-15 of the instruction.
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f FUNC bits 0-10 of the instruction.
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i An immediate operand is in bits 0-16 of the instruction. 0 extended
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I An immediate operand is in bits 0-16 of the instruction. sign extended
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d An 16 bit PC relative displacement.
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D An immediate operand is in bits 0-25 of the instruction.
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N No opperands needed, for nops.
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P it can be a register or a 16 bit operand. */
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const char *args;
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};
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static const struct dlx_opcode dlx_opcodes[] =
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{
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/* Arithmetic and Logic R-TYPE instructions. */
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{ "nop", (ALUOP|NOPF), "N" }, /* NOP */
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{ "add", (ALUOP|ADDF), "c,a,b" }, /* Add */
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{ "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */
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{ "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */
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{ "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */
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{ "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */
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{ "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */
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{ "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */
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{ "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */
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{ "and", (ALUOP|ANDF), "c,a,b" }, /* AND */
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{ "or", (ALUOP|ORF), "c,a,b" }, /* OR */
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{ "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */
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{ "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */
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{ "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */
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{ "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */
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{ "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */
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{ "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */
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{ "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */
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{ "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */
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{ "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */
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{ "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */
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{ "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */
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{ "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */
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{ "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */
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{ "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */
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{ "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/
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{ "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */
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{ "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */
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{ "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */
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{ "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */
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{ "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */
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/* Arithmetic and Logical Immediate I-TYPE instructions. */
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{ "addi", ADDIOP, "b,a,I" }, /* Add Immediate */
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{ "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */
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{ "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */
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{ "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */
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{ "andi", ANDIOP, "b,a,i" }, /* AND Immediate */
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{ "ori", ORIOP, "b,a,i" }, /* OR Immediate */
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{ "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */
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{ "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */
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{ "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */
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{ "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/
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{ "seqi", SEQIOP, "b,a,i" }, /* Set if equal */
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{ "snei", SNEIOP, "b,a,i" }, /* Set if not equal */
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{ "slti", SLTIOP, "b,a,i" }, /* Set if less */
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{ "sgti", SGTIOP, "b,a,i" }, /* Set if greater */
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{ "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */
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{ "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */
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{ "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */
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{ "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */
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{ "sltui", SLTUIOP, "b,a,i" }, /* Set if less */
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{ "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */
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{ "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */
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{ "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */
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/* Macros for I type instructions. */
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{ "mov", ADDIOP, "b,P" }, /* a move macro */
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{ "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */
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#if 0
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/* Move special. */
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{ "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */
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{ "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */
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#endif
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/* Load high Immediate I-TYPE instruction. */
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{ "lhi", LHIOP, "b,i" }, /* Load High Immediate */
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{ "lui", LHIOP, "b,i" }, /* Load High Immediate */
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{ "sethi", LHIOP, "b,i" }, /* Load High Immediate */
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/* LOAD/STORE BYTE 8 bits I-TYPE. */
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{ "lb", LBOP, "b,a,I" }, /* Load Byte */
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{ "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */
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{ "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */
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{ "sb", SBOP, "b,a,I" }, /* Store Byte */
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/* LOAD/STORE HALFWORD 16 bits. */
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{ "lh", LHOP, "b,a,I" }, /* Load Halfword */
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{ "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */
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{ "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */
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{ "sh", SHOP, "b,a,I" }, /* Store Halfword */
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/* LOAD/STORE WORD 32 bits. */
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{ "lw", LWOP, "b,a,I" }, /* Load Word */
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{ "sw", SWOP, "b,a,I" }, /* Store Word */
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{ "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */
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/* Branch PC-relative, 16 bits offset. */
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{ "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */
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{ "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */
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{ "beq", BEQOP, "a,d" }, /* Branch if a == 0 */
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{ "bne", BNEOP, "a,d" }, /* Branch if a != 0 */
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/* Jumps Trap and RFE J-TYPE. */
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{ "j", JOP, "D" }, /* Jump, PC-relative 26 bits */
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{ "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */
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{ "break", BREAKOP, "D" }, /* break to OS */
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{ "trap" , TRAPOP, "D" }, /* TRAP to OS */
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{ "rfe", RFEOP, "N" }, /* Return From Exception */
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/* Macros. */
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{ "call", JOP, "D" }, /* Jump, PC-relative 26 bits */
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/* Jumps Trap and RFE I-TYPE. */
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{ "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */
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{ "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */
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/* Macros. */
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{ "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */
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{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES.
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This lets code examine entry i + 1 without
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checking if we've run off the end of the table. */
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};
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const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1);
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