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455 lines
11 KiB
C
455 lines
11 KiB
C
/* Table of opcodes for the Motorola M88k family.
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Copyright (C) 1989-2017 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/*
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* Disassembler Instruction Table
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*
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* The first field of the table is the opcode field. If an opcode
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* is specified which has any non-opcode bits on, a system error
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* will occur when the system attempts the install it into the
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* instruction table. The second parameter is a pointer to the
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* instruction mnemonic. Each operand is specified by offset, width,
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* and type. The offset is the bit number of the least significant
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* bit of the operand with bit 0 being the least significant bit of
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* the instruction. The width is the number of bits used to specify
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* the operand. The type specifies the output format to be used for
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* the operand. The valid formats are: register, register indirect,
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* hex constant, and bit field specification. The last field is a
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* pointer to the next instruction in the linked list. These pointers
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* are initialized by init_disasm().
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*
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* Revision History
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*
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* Revision 1.0 11/08/85 Creation date
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* 1.1 02/05/86 Updated instruction mnemonic table MD
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* 1.2 06/16/86 Updated SIM_FLAGS for floating point
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* 1.3 09/20/86 Updated for new encoding
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* 05/11/89 R. Trawick adapted from Motorola disassembler
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*/
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#include <stdio.h>
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/* Define the number of bits in the primary opcode field of the instruction,
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the destination field, the source 1 and source 2 fields. */
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/* Size of opcode field. */
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#define OP 8
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/* Size of destination. */
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#define DEST 6
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/* Size of source1. */
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#define SOURCE1 6
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/* Size of source2. */
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#define SOURCE2 6
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/* Number of registers. */
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#define REGs 32
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/* Type definitions. */
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typedef unsigned int UINT;
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#define WORD long
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#define FLAG unsigned
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#define STATE short
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/* The next four equates define the priorities that the various classes
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* of instructions have regarding writing results back into registers and
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* signalling exceptions. */
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/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
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#undef PMEM
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/* Integer priority. */
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#define PINT 0
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/* Floating point priority. */
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#define PFLT 1
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/* Memory priority. */
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#define PMEM 2
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/* Not applicable, instruction doesn't write to regs. */
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#define NA 3
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/* Highest of these priorities. */
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#define HIPRI 3
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/* The instruction registers are an artificial mechanism to speed up
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* simulator execution. In the real processor, an instruction register
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* is 32 bits wide. In the simulator, the 32 bit instruction is kept in
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* a structure field called rawop, and the instruction is partially decoded,
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* and split into various fields and flags which make up the other fields
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* of the structure.
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* The partial decode is done when the instructions are initially loaded
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* into simulator memory. The simulator code memory is not an array of
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* 32 bit words, but is an array of instruction register structures.
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* Yes this wastes memory, but it executes much quicker.
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*/
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struct IR_FIELDS
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{
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unsigned op:OP,
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dest: DEST,
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src1: SOURCE1,
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src2: SOURCE2;
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int ltncy,
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extime,
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/* Writeback priority. */
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wb_pri;
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/* Immediate size. */
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unsigned imm_flags:2,
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/* Register source 1 used. */
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rs1_used:1,
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/* Register source 2 used. */
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rs2_used:1,
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/* Register source/dest. used. */
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rsd_used:1,
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/* Complement. */
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c_flag:1,
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/* Upper half word. */
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u_flag:1,
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/* Execute next. */
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n_flag:1,
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/* Uses writeback slot. */
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wb_flag:1,
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/* Dest size. */
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dest_64:1,
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/* Source 1 size. */
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s1_64:1,
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/* Source 2 size. */
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s2_64:1,
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scale_flag:1,
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/* Scaled register. */
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brk_flg:1;
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};
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struct mem_segs
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{
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/* Pointer (returned by calloc) to segment. */
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struct mem_wrd *seg;
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/* Base load address from file headers. */
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unsigned long baseaddr;
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/* Ending address of segment. */
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unsigned long endaddr;
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/* Segment control flags (none defined). */
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int flags;
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};
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#define MAXSEGS (10) /* max number of segment allowed */
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#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
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#if 0
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#define BRK_RD (0x01) /* break on memory read */
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#define BRK_WR (0x02) /* break on memory write */
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#define BRK_EXEC (0x04) /* break on execution */
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#define BRK_CNT (0x08) /* break on terminal count */
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#endif
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struct mem_wrd
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{
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/* Simulator instruction break down. */
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struct IR_FIELDS opcode;
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union {
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/* Memory element break down. */
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unsigned long l;
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unsigned short s[2];
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unsigned char c[4];
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} mem;
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};
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/* Size of each 32 bit memory model. */
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#define MEMWRDSIZE (sizeof (struct mem_wrd))
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extern struct mem_segs memory[];
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extern struct PROCESSOR m78000;
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struct PROCESSOR
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{
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unsigned WORD
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/* Execute instruction pointer. */
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ip,
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/* Vector base register. */
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vbr,
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/* Processor status register. */
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psr;
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/* Source 1. */
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WORD S1bus,
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/* Source 2. */
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S2bus,
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/* Destination. */
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Dbus,
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/* Data address bus. */
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DAbus,
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ALU,
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/* Data registers. */
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Regs[REGs],
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/* Max clocks before reg is available. */
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time_left[REGs],
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/* Writeback priority of reg. */
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wb_pri[REGs],
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/* Integer unit control regs. */
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SFU0_regs[REGs],
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/* Floating point control regs. */
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SFU1_regs[REGs],
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Scoreboard[REGs],
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Vbr;
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unsigned WORD scoreboard,
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Psw,
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Tpsw;
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/* Waiting for a jump instruction. */
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FLAG jump_pending:1;
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};
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/* Size of immediate field. */
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#define i26bit 1
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#define i16bit 2
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#define i10bit 3
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/* Definitions for fields in psr. */
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#define psr_mode 31
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#define psr_rbo 30
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#define psr_ser 29
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#define psr_carry 28
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#define psr_sf7m 11
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#define psr_sf6m 10
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#define psr_sf5m 9
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#define psr_sf4m 8
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#define psr_sf3m 7
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#define psr_sf2m 6
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#define psr_sf1m 5
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#define psr_mam 4
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#define psr_inm 3
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#define psr_exm 2
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#define psr_trm 1
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#define psr_ovfm 0
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/* The 1 clock operations. */
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#define ADDU 1
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#define ADDC 2
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#define ADDUC 3
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#define ADD 4
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#define SUBU ADD+1
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#define SUBB ADD+2
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#define SUBUB ADD+3
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#define SUB ADD+4
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#define AND_ ADD+5
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#define OR ADD+6
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#define XOR ADD+7
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#define CMP ADD+8
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/* Loads. */
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#define LDAB CMP+1
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#define LDAH CMP+2
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#define LDA CMP+3
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#define LDAD CMP+4
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#define LDB LDAD+1
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#define LDH LDAD+2
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#define LD LDAD+3
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#define LDD LDAD+4
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#define LDBU LDAD+5
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#define LDHU LDAD+6
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/* Stores. */
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#define STB LDHU+1
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#define STH LDHU+2
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#define ST LDHU+3
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#define STD LDHU+4
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/* Exchange. */
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#define XMEMBU LDHU+5
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#define XMEM LDHU+6
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/* Branches. */
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#define JSR STD+1
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#define BSR STD+2
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#define BR STD+3
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#define JMP STD+4
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#define BB1 STD+5
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#define BB0 STD+6
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#define RTN STD+7
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#define BCND STD+8
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/* Traps. */
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#define TB1 BCND+1
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#define TB0 BCND+2
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#define TCND BCND+3
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#define RTE BCND+4
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#define TBND BCND+5
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/* Misc. */
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#define MUL TBND + 1
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#define DIV MUL +2
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#define DIVU MUL +3
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#define MASK MUL +4
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#define FF0 MUL +5
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#define FF1 MUL +6
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#define CLR MUL +7
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#define SET MUL +8
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#define EXT MUL +9
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#define EXTU MUL +10
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#define MAK MUL +11
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#define ROT MUL +12
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/* Control register manipulations. */
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#define LDCR ROT +1
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#define STCR ROT +2
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#define XCR ROT +3
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#define FLDCR ROT +4
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#define FSTCR ROT +5
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#define FXCR ROT +6
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#define NOP XCR +1
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/* Floating point instructions. */
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#define FADD NOP +1
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#define FSUB NOP +2
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#define FMUL NOP +3
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#define FDIV NOP +4
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#define FSQRT NOP +5
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#define FCMP NOP +6
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#define FIP NOP +7
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#define FLT NOP +8
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#define INT NOP +9
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#define NINT NOP +10
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#define TRNC NOP +11
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#define FLDC NOP +12
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#define FSTC NOP +13
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#define FXC NOP +14
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#define UEXT(src,off,wid) \
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((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
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#define SEXT(src,off,wid) \
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(((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
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#define MAKE(src,off,wid) \
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((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
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#define opword(n) (unsigned long) (memaddr->mem.l)
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/* Constants and masks. */
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#define SFU0 0x80000000
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#define SFU1 0x84000000
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#define SFU7 0x9c000000
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#define RRI10 0xf0000000
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#define RRR 0xf4000000
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#define SFUMASK 0xfc00ffe0
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#define RRRMASK 0xfc00ffe0
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#define RRI10MASK 0xfc00fc00
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#define DEFMASK 0xfc000000
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#define CTRL 0x0000f000
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#define CTRLMASK 0xfc00f800
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/* Operands types. */
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enum operand_type
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{
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HEX = 1,
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REG = 2,
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CONT = 3,
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IND = 3,
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BF = 4,
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/* Scaled register. */
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REGSC = 5,
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/* Control register. */
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CRREG = 6,
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/* Floating point control register. */
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FCRREG = 7,
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PCREL = 8,
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CONDMASK = 9,
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/* Extended register. */
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XREG = 10,
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/* Decimal. */
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DEC = 11
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};
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/* Hashing specification. */
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#define HASHVAL 79
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/* Structure templates. */
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typedef struct
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{
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unsigned int offset;
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unsigned int width;
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enum operand_type type;
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} OPSPEC;
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struct SIM_FLAGS
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{
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int ltncy, /* latency (max number of clocks needed to execute). */
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extime, /* execution time (min number of clocks needed to execute). */
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wb_pri; /* writeback slot priority. */
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unsigned op:OP, /* simulator version of opcode. */
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imm_flags:2, /* 10,16 or 26 bit immediate flags. */
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rs1_used:1, /* register source 1 used. */
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rs2_used:1, /* register source 2 used. */
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rsd_used:1, /* register source/dest used. */
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c_flag:1, /* complement. */
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u_flag:1, /* upper half word. */
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n_flag:1, /* execute next. */
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wb_flag:1, /* uses writeback slot. */
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dest_64:1, /* double precision dest. */
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s1_64:1, /* double precision source 1. */
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s2_64:1, /* double precision source 2. */
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scale_flag:1; /* register is scaled. */
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};
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typedef struct INSTRUCTAB {
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unsigned int opcode;
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char *mnemonic;
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OPSPEC op1,op2,op3;
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struct SIM_FLAGS flgs;
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} INSTAB;
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#define NO_OPERAND {0,0,0}
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extern const INSTAB instructions[];
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/*
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* Local Variables:
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* fill-column: 131
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* End:
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*/
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