mirror of
https://github.com/autc04/Retro68.git
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2497 lines
94 KiB
Groff
2497 lines
94 KiB
Groff
.\" Automatically generated by Pod::Man 4.09 (Pod::Simple 3.35)
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.\"
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.\" Standard preamble:
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.\" ========================================================================
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.ft R
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..
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.\" Set up some character translations and predefined strings. \*(-- will
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.tr \(*W-
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.\"
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.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
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\{\
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.\}
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.rm #[ #] #H #V #F C
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.\" ========================================================================
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.\"
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.IX Title "AS 1"
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.TH AS 1 "2018-06-24" "binutils-2.30.90" "GNU Development Tools"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.if n .ad l
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.nh
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.SH "NAME"
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AS \- the portable GNU assembler.
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
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[\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR]
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[\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
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[\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
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[\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-gdwarf\-sections\fR]
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[\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
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[\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
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[\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR]
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[\fB\-\-no\-pad\-sections\fR]
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[\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR]
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[\fB\-\-hash\-size\fR=\fI\s-1NUM\s0\fR] [\fB\-\-reduce\-memory\-overheads\fR]
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[\fB\-\-statistics\fR]
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[\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR]
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[\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR]
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[\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
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[\fB\-\-sectname\-subst\fR] [\fB\-\-size\-check=[error|warning]\fR]
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[\fB\-\-elf\-stt\-common=[no|yes]\fR]
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[\fB\-\-generate\-missing\-build\-notes=[no|yes]\fR]
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[\fB\-\-target\-help\fR] [\fItarget-options\fR]
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[\fB\-\-\fR|\fIfiles\fR ...]
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.SH "TARGET"
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.IX Header "TARGET"
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\&\fITarget AArch64 options:\fR
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[\fB\-EB\fR|\fB\-EL\fR]
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[\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
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.PP
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\&\fITarget Alpha options:\fR
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[\fB\-m\fR\fIcpu\fR]
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[\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
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[\fB\-replace\fR | \fB\-noreplace\fR]
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[\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
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[\fB\-F\fR] [\fB\-32addr\fR]
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.PP
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\&\fITarget \s-1ARC\s0 options:\fR
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[\fB\-mcpu=\fR\fIcpu\fR]
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[\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
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[\fB\-mcode\-density\fR]
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[\fB\-mrelax\fR]
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[\fB\-EB\fR|\fB\-EL\fR]
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.PP
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\&\fITarget \s-1ARM\s0 options:\fR
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[\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
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[\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
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[\fB\-mfpu\fR=\fIfloating-point-format\fR]
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[\fB\-mfloat\-abi\fR=\fIabi\fR]
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[\fB\-meabi\fR=\fIver\fR]
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[\fB\-mthumb\fR]
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[\fB\-EB\fR|\fB\-EL\fR]
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[\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
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\fB\-mapcs\-reentrant\fR]
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[\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
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.PP
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\&\fITarget Blackfin options:\fR
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[\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]]
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[\fB\-mfdpic\fR]
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[\fB\-mno\-fdpic\fR]
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[\fB\-mnopic\fR]
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.PP
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\&\fITarget \s-1CRIS\s0 options:\fR
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[\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
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[\fB\-\-pic\fR] [\fB\-N\fR]
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[\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
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[\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
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.PP
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\&\fITarget D10V options:\fR
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[\fB\-O\fR]
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.PP
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\&\fITarget D30V options:\fR
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[\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
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.PP
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\&\fITarget \s-1EPIPHANY\s0 options:\fR
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[\fB\-mepiphany\fR|\fB\-mepiphany16\fR]
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.PP
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\&\fITarget H8/300 options:\fR
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[\-h\-tick\-hex]
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.PP
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\&\fITarget i386 options:\fR
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[\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR]
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[\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
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.PP
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\&\fITarget \s-1IA\-64\s0 options:\fR
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[\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
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[\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
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[\fB\-mle\fR|\fBmbe\fR]
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[\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
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[\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
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[\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
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[\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
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.PP
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\&\fITarget \s-1IP2K\s0 options:\fR
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[\fB\-mip2022\fR|\fB\-mip2022ext\fR]
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.PP
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\&\fITarget M32C options:\fR
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[\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex]
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.PP
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\&\fITarget M32R options:\fR
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[\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
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\fB\-\-W[n]p\fR]
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.PP
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\&\fITarget M680X0 options:\fR
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[\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
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.PP
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\&\fITarget M68HC11 options:\fR
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[\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
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[\fB\-mshort\fR|\fB\-mlong\fR]
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[\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
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[\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]
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[\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
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[\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
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.PP
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\&\fITarget \s-1MCORE\s0 options:\fR
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[\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
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[\fB\-mcpu=[210|340]\fR]
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.PP
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|
\&\fITarget Meta options:\fR
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[\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR]
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\&\fITarget \s-1MICROBLAZE\s0 options:\fR
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.PP
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|
\&\fITarget \s-1MIPS\s0 options:\fR
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[\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
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[\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
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[\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]
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|
[\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
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[\fB\-mfp64\fR] [\fB\-mgp64\fR] [\fB\-mfpxx\fR]
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|
[\fB\-modd\-spreg\fR] [\fB\-mno\-odd\-spreg\fR]
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[\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
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[\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
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[\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR]
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|
[\fB\-mips64r3\fR] [\fB\-mips64r5\fR] [\fB\-mips64r6\fR]
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[\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
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[\fB\-mignore\-branch\-isa\fR] [\fB\-mno\-ignore\-branch\-isa\fR]
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[\fB\-mnan=\fR\fIencoding\fR]
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[\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
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|
[\fB\-mips16\fR] [\fB\-no\-mips16\fR]
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|
[\fB\-mmips16e2\fR] [\fB\-mno\-mips16e2\fR]
|
|
[\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR]
|
|
[\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]
|
|
[\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
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|
[\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
|
|
[\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
|
|
[\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]
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|
[\fB\-mdspr3\fR] [\fB\-mno\-dspr3\fR]
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|
[\fB\-mmsa\fR] [\fB\-mno\-msa\fR]
|
|
[\fB\-mxpa\fR] [\fB\-mno\-xpa\fR]
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|
[\fB\-mmt\fR] [\fB\-mno\-mt\fR]
|
|
[\fB\-mmcu\fR] [\fB\-mno\-mcu\fR]
|
|
[\fB\-mcrc\fR] [\fB\-mno\-crc\fR]
|
|
[\fB\-mginv\fR] [\fB\-mno\-ginv\fR]
|
|
[\fB\-minsn32\fR] [\fB\-mno\-insn32\fR]
|
|
[\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
|
|
[\fB\-mfix\-rm7000\fR] [\fB\-mno\-fix\-rm7000\fR]
|
|
[\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR]
|
|
[\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR]
|
|
[\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
|
|
[\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
|
|
.PP
|
|
\&\fITarget \s-1MMIX\s0 options:\fR
|
|
[\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
|
|
[\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
|
|
[\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
|
|
[\fB\-\-linker\-allocated\-gregs\fR]
|
|
.PP
|
|
\&\fITarget Nios \s-1II\s0 options:\fR
|
|
[\fB\-relax\-all\fR] [\fB\-relax\-section\fR] [\fB\-no\-relax\fR]
|
|
[\fB\-EB\fR] [\fB\-EL\fR]
|
|
.PP
|
|
\&\fITarget \s-1NDS32\s0 options:\fR
|
|
[\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR] [\fB\-mcpu=\fR\fIcpu\fR]
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|
[\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR]
|
|
[\fB\-m[no\-]16\-bit\fR] [\fB\-m[no\-]perf\-ext\fR] [\fB\-m[no\-]perf2\-ext\fR]
|
|
[\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR] [\fB\-m[no\-]div\fR]
|
|
[\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR] [\fB\-m[no\-]fpu\-dp\-ext\fR]
|
|
[\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fI\s-1FREG\s0\fR] [\fB\-mreduced\-regs\fR]
|
|
[\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR] [\fB\-mno\-relax\fR]
|
|
[\fB\-mb2bb\fR]
|
|
.PP
|
|
\&\fITarget \s-1PDP11\s0 options:\fR
|
|
[\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
|
|
[\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
|
|
[\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
|
|
.PP
|
|
\&\fITarget picoJava options:\fR
|
|
[\fB\-mb\fR|\fB\-me\fR]
|
|
.PP
|
|
\&\fITarget PowerPC options:\fR
|
|
[\fB\-a32\fR|\fB\-a64\fR]
|
|
[\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
|
|
\fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mppc64\fR|
|
|
\fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|\fB\-me6500\fR|\fB\-mppc64bridge\fR|
|
|
\fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|\fB\-mpower6\fR|\fB\-mpwr6\fR|
|
|
\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
|
|
\fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
|
|
[\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR|\fB\-mhtm\fR|\fB\-mvle\fR]
|
|
[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
|
|
[\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR]
|
|
[\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
|
|
[\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
|
|
[\fB\-nops=\fR\fIcount\fR]
|
|
.PP
|
|
\&\fITarget \s-1PRU\s0 options:\fR
|
|
[\fB\-link\-relax\fR]
|
|
[\fB\-mnolink\-relax\fR]
|
|
[\fB\-mno\-warn\-regname\-label\fR]
|
|
.PP
|
|
\&\fITarget RISC-V options:\fR
|
|
[\fB\-fpic\fR|\fB\-fPIC\fR|\fB\-fno\-pic\fR]
|
|
[\fB\-march\fR=\fI\s-1ISA\s0\fR]
|
|
[\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
|
|
.PP
|
|
\&\fITarget \s-1RL78\s0 options:\fR
|
|
[\fB\-mg10\fR]
|
|
[\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
|
|
.PP
|
|
\&\fITarget \s-1RX\s0 options:\fR
|
|
[\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR]
|
|
[\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
|
|
[\fB\-muse\-conventional\-section\-names\fR]
|
|
[\fB\-msmall\-data\-limit\fR]
|
|
[\fB\-mpid\fR]
|
|
[\fB\-mrelax\fR]
|
|
[\fB\-mint\-register=\fR\fInumber\fR]
|
|
[\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR]
|
|
.PP
|
|
\&\fITarget s390 options:\fR
|
|
[\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR]
|
|
[\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
|
|
[\fB\-mwarn\-areg\-zero\fR]
|
|
.PP
|
|
\&\fITarget \s-1SCORE\s0 options:\fR
|
|
[\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR]
|
|
[\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
|
|
[\fB\-march=score7\fR][\fB\-march=score3\fR]
|
|
[\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR]
|
|
.PP
|
|
\&\fITarget \s-1SPARC\s0 options:\fR
|
|
[\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
|
|
\fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
|
|
\fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
|
|
\fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
|
|
\fB\-Asparcvis2\fR|\fB\-Asparcfmaf\fR|\fB\-Asparcima\fR|\fB\-Asparcvis3\fR
|
|
\fB\-Asparcvisr\fR|\fB\-Asparc5\fR]
|
|
[\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
|
|
\fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
|
|
\fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
|
|
\fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
|
|
\fB\-xarch=sparcvis2\fR|\fB\-xarch=sparcfmaf\fR|\fB\-xarch=sparcima\fR
|
|
\fB\-xarch=sparcvis3\fR|\fB\-xarch=sparcvisr\fR|\fB\-xarch=sparc5\fR
|
|
\fB\-bump\fR]
|
|
[\fB\-32\fR|\fB\-64\fR]
|
|
[\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR]
|
|
.PP
|
|
\&\fITarget \s-1TIC54X\s0 options:\fR
|
|
[\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]
|
|
[\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
|
|
.PP
|
|
\&\fITarget \s-1TIC6X\s0 options:\fR
|
|
[\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR]
|
|
[\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR]
|
|
[\fB\-mpic\fR|\fB\-mno\-pic\fR]
|
|
.PP
|
|
\&\fITarget TILE-Gx options:\fR
|
|
[\fB\-m32\fR|\fB\-m64\fR][\fB\-EB\fR][\fB\-EL\fR]
|
|
.PP
|
|
\&\fITarget Visium options:\fR
|
|
[\fB\-mtune=\fR\fIarch\fR]
|
|
.PP
|
|
\&\fITarget Xtensa options:\fR
|
|
[\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]auto\-litpools\fR]
|
|
[\fB\-\-[no\-]absolute\-literals\fR]
|
|
[\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
|
|
[\fB\-\-[no\-]transform\fR]
|
|
[\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
|
|
[\fB\-\-[no\-]trampolines\fR]
|
|
.PP
|
|
\&\fITarget Z80 options:\fR
|
|
[\fB\-z80\fR] [\fB\-r800\fR]
|
|
[ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
|
|
[ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
|
|
[ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
|
|
[ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
|
|
[ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
|
|
[ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
|
|
.SH "DESCRIPTION"
|
|
.IX Header "DESCRIPTION"
|
|
\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
|
|
If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
|
|
should find a fairly similar environment when you use it on another
|
|
architecture. Each version has much in common with the others,
|
|
including object file formats, most assembler directives (often called
|
|
\&\fIpseudo-ops\fR) and assembler syntax.
|
|
.PP
|
|
\&\fBas\fR is primarily intended to assemble the output of the
|
|
\&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
|
|
\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR
|
|
assemble correctly everything that other assemblers for the same
|
|
machine would assemble.
|
|
Any exceptions are documented explicitly.
|
|
This doesn't mean \fBas\fR always uses the same syntax as another
|
|
assembler for the same architecture; for example, we know of several
|
|
incompatible versions of 680x0 assembly language syntax.
|
|
.PP
|
|
Each time you run \fBas\fR it assembles exactly one source
|
|
program. The source program is made up of one or more files.
|
|
(The standard input is also a file.)
|
|
.PP
|
|
You give \fBas\fR a command line that has zero or more input file
|
|
names. The input files are read (from left file name to right). A
|
|
command line argument (in any position) that has no special meaning
|
|
is taken to be an input file name.
|
|
.PP
|
|
If you give \fBas\fR no file names it attempts to read one input file
|
|
from the \fBas\fR standard input, which is normally your terminal. You
|
|
may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
|
|
to assemble.
|
|
.PP
|
|
Use \fB\-\-\fR if you need to explicitly name the standard input file
|
|
in your command line.
|
|
.PP
|
|
If the source is empty, \fBas\fR produces a small, empty object
|
|
file.
|
|
.PP
|
|
\&\fBas\fR may write warnings and error messages to the standard error
|
|
file (usually your terminal). This should not happen when a compiler
|
|
runs \fBas\fR automatically. Warnings report an assumption made so
|
|
that \fBas\fR could keep assembling a flawed program; errors report a
|
|
grave problem that stops the assembly.
|
|
.PP
|
|
If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler,
|
|
you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
|
|
The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
|
|
by commas. For example:
|
|
.PP
|
|
.Vb 1
|
|
\& gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
|
|
.Ve
|
|
.PP
|
|
This passes two options to the assembler: \fB\-alh\fR (emit a listing to
|
|
standard output with high-level and assembly source) and \fB\-L\fR (retain
|
|
local symbols in the symbol table).
|
|
.PP
|
|
Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
|
|
command-line options are automatically passed to the assembler by the compiler.
|
|
(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
|
|
precisely what options it passes to each compilation pass, including the
|
|
assembler.)
|
|
.SH "OPTIONS"
|
|
.IX Header "OPTIONS"
|
|
.IP "\fB@\fR\fIfile\fR" 4
|
|
.IX Item "@file"
|
|
Read command-line options from \fIfile\fR. The options read are
|
|
inserted in place of the original @\fIfile\fR option. If \fIfile\fR
|
|
does not exist, or cannot be read, then the option will be treated
|
|
literally, and not removed.
|
|
.Sp
|
|
Options in \fIfile\fR are separated by whitespace. A whitespace
|
|
character may be included in an option by surrounding the entire
|
|
option in either single or double quotes. Any character (including a
|
|
backslash) may be included by prefixing the character to be included
|
|
with a backslash. The \fIfile\fR may itself contain additional
|
|
@\fIfile\fR options; any such options will be processed recursively.
|
|
.IP "\fB\-a[cdghlmns]\fR" 4
|
|
.IX Item "-a[cdghlmns]"
|
|
Turn on listings, in any of a variety of ways:
|
|
.RS 4
|
|
.IP "\fB\-ac\fR" 4
|
|
.IX Item "-ac"
|
|
omit false conditionals
|
|
.IP "\fB\-ad\fR" 4
|
|
.IX Item "-ad"
|
|
omit debugging directives
|
|
.IP "\fB\-ag\fR" 4
|
|
.IX Item "-ag"
|
|
include general information, like as version and options passed
|
|
.IP "\fB\-ah\fR" 4
|
|
.IX Item "-ah"
|
|
include high-level source
|
|
.IP "\fB\-al\fR" 4
|
|
.IX Item "-al"
|
|
include assembly
|
|
.IP "\fB\-am\fR" 4
|
|
.IX Item "-am"
|
|
include macro expansions
|
|
.IP "\fB\-an\fR" 4
|
|
.IX Item "-an"
|
|
omit forms processing
|
|
.IP "\fB\-as\fR" 4
|
|
.IX Item "-as"
|
|
include symbols
|
|
.IP "\fB=file\fR" 4
|
|
.IX Item "=file"
|
|
set the name of the listing file
|
|
.RE
|
|
.RS 4
|
|
.Sp
|
|
You may combine these options; for example, use \fB\-aln\fR for assembly
|
|
listing without forms processing. The \fB=file\fR option, if used, must be
|
|
the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
|
|
.RE
|
|
.IP "\fB\-\-alternate\fR" 4
|
|
.IX Item "--alternate"
|
|
Begin in alternate macro mode.
|
|
.IP "\fB\-\-compress\-debug\-sections\fR" 4
|
|
.IX Item "--compress-debug-sections"
|
|
Compress \s-1DWARF\s0 debug sections using zlib with \s-1SHF_COMPRESSED\s0 from the
|
|
\&\s-1ELF ABI.\s0 The resulting object file may not be compatible with older
|
|
linkers and object file utilities. Note if compression would make a
|
|
given section \fIlarger\fR then it is not compressed.
|
|
.IP "\fB\-\-compress\-debug\-sections=none\fR" 4
|
|
.IX Item "--compress-debug-sections=none"
|
|
.PD 0
|
|
.IP "\fB\-\-compress\-debug\-sections=zlib\fR" 4
|
|
.IX Item "--compress-debug-sections=zlib"
|
|
.IP "\fB\-\-compress\-debug\-sections=zlib\-gnu\fR" 4
|
|
.IX Item "--compress-debug-sections=zlib-gnu"
|
|
.IP "\fB\-\-compress\-debug\-sections=zlib\-gabi\fR" 4
|
|
.IX Item "--compress-debug-sections=zlib-gabi"
|
|
.PD
|
|
These options control how \s-1DWARF\s0 debug sections are compressed.
|
|
\&\fB\-\-compress\-debug\-sections=none\fR is equivalent to
|
|
\&\fB\-\-nocompress\-debug\-sections\fR.
|
|
\&\fB\-\-compress\-debug\-sections=zlib\fR and
|
|
\&\fB\-\-compress\-debug\-sections=zlib\-gabi\fR are equivalent to
|
|
\&\fB\-\-compress\-debug\-sections\fR.
|
|
\&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses \s-1DWARF\s0 debug
|
|
sections using zlib. The debug sections are renamed to begin with
|
|
\&\fB.zdebug\fR. Note if compression would make a given section
|
|
\&\fIlarger\fR then it is not compressed nor renamed.
|
|
.IP "\fB\-\-nocompress\-debug\-sections\fR" 4
|
|
.IX Item "--nocompress-debug-sections"
|
|
Do not compress \s-1DWARF\s0 debug sections. This is usually the default for all
|
|
targets except the x86/x86_64, but a configure time option can be used to
|
|
override this.
|
|
.IP "\fB\-D\fR" 4
|
|
.IX Item "-D"
|
|
Ignored. This option is accepted for script compatibility with calls to
|
|
other assemblers.
|
|
.IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4
|
|
.IX Item "--debug-prefix-map old=new"
|
|
When assembling files in directory \fI\fIold\fI\fR, record debugging
|
|
information describing them as in \fI\fInew\fI\fR instead.
|
|
.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
|
|
.IX Item "--defsym sym=value"
|
|
Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
|
|
\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
|
|
indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
|
|
value. The value of the symbol can be overridden inside a source file via the
|
|
use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
|
|
.IP "\fB\-f\fR" 4
|
|
.IX Item "-f"
|
|
\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
|
|
compiler output).
|
|
.IP "\fB\-g\fR" 4
|
|
.IX Item "-g"
|
|
.PD 0
|
|
.IP "\fB\-\-gen\-debug\fR" 4
|
|
.IX Item "--gen-debug"
|
|
.PD
|
|
Generate debugging information for each assembler source line using whichever
|
|
debug format is preferred by the target. This currently means either \s-1STABS,
|
|
ECOFF\s0 or \s-1DWARF2.\s0
|
|
.IP "\fB\-\-gstabs\fR" 4
|
|
.IX Item "--gstabs"
|
|
Generate stabs debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it.
|
|
.IP "\fB\-\-gstabs+\fR" 4
|
|
.IX Item "--gstabs+"
|
|
Generate stabs debugging information for each assembler line, with \s-1GNU\s0
|
|
extensions that probably only gdb can handle, and that could make other
|
|
debuggers crash or refuse to read your program. This
|
|
may help debugging assembler code. Currently the only \s-1GNU\s0 extension is
|
|
the location of the current working directory at assembling time.
|
|
.IP "\fB\-\-gdwarf\-2\fR" 4
|
|
.IX Item "--gdwarf-2"
|
|
Generate \s-1DWARF2\s0 debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it. Note\-\-\-this
|
|
option is only supported by some targets, not all of them.
|
|
.IP "\fB\-\-gdwarf\-sections\fR" 4
|
|
.IX Item "--gdwarf-sections"
|
|
Instead of creating a .debug_line section, create a series of
|
|
\&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the
|
|
corresponding code section. For example a code section called \fI.text.func\fR
|
|
will have its dwarf line number information placed into a section called
|
|
\&\fI.debug_line.text.func\fR. If the code section is just called \fI.text\fR
|
|
then debug line section will still be called just \fI.debug_line\fR without any
|
|
suffix.
|
|
.IP "\fB\-\-size\-check=error\fR" 4
|
|
.IX Item "--size-check=error"
|
|
.PD 0
|
|
.IP "\fB\-\-size\-check=warning\fR" 4
|
|
.IX Item "--size-check=warning"
|
|
.PD
|
|
Issue an error or warning for invalid \s-1ELF\s0 .size directive.
|
|
.IP "\fB\-\-elf\-stt\-common=no\fR" 4
|
|
.IX Item "--elf-stt-common=no"
|
|
.PD 0
|
|
.IP "\fB\-\-elf\-stt\-common=yes\fR" 4
|
|
.IX Item "--elf-stt-common=yes"
|
|
.PD
|
|
These options control whether the \s-1ELF\s0 assembler should generate common
|
|
symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be controlled
|
|
by a configure option \fB\-\-enable\-elf\-stt\-common\fR.
|
|
.IP "\fB\-\-generate\-missing\-build\-notes=yes\fR" 4
|
|
.IX Item "--generate-missing-build-notes=yes"
|
|
.PD 0
|
|
.IP "\fB\-\-generate\-missing\-build\-notes=no\fR" 4
|
|
.IX Item "--generate-missing-build-notes=no"
|
|
.PD
|
|
These options control whether the \s-1ELF\s0 assembler should generate \s-1GNU\s0 Build
|
|
attribute notes if none are present in the input sources.
|
|
The default can be controlled by the \fB\-\-enable\-generate\-build\-notes\fR
|
|
configure option.
|
|
.IP "\fB\-\-help\fR" 4
|
|
.IX Item "--help"
|
|
Print a summary of the command line options and exit.
|
|
.IP "\fB\-\-target\-help\fR" 4
|
|
.IX Item "--target-help"
|
|
Print a summary of all target specific options and exit.
|
|
.IP "\fB\-I\fR \fIdir\fR" 4
|
|
.IX Item "-I dir"
|
|
Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
|
|
.IP "\fB\-J\fR" 4
|
|
.IX Item "-J"
|
|
Don't warn about signed overflow.
|
|
.IP "\fB\-K\fR" 4
|
|
.IX Item "-K"
|
|
Issue warnings when difference tables altered for long displacements.
|
|
.IP "\fB\-L\fR" 4
|
|
.IX Item "-L"
|
|
.PD 0
|
|
.IP "\fB\-\-keep\-locals\fR" 4
|
|
.IX Item "--keep-locals"
|
|
.PD
|
|
Keep (in the symbol table) local symbols. These symbols start with
|
|
system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems
|
|
or \fBL\fR for traditional a.out systems.
|
|
.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-lhs-width=number"
|
|
Set the maximum width, in words, of the output data column for an assembler
|
|
listing to \fInumber\fR.
|
|
.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-lhs-width2=number"
|
|
Set the maximum width, in words, of the output data column for continuation
|
|
lines in an assembler listing to \fInumber\fR.
|
|
.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-rhs-width=number"
|
|
Set the maximum width of an input source line, as displayed in a listing, to
|
|
\&\fInumber\fR bytes.
|
|
.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
|
|
.IX Item "--listing-cont-lines=number"
|
|
Set the maximum number of lines printed in a listing for a single line of input
|
|
to \fInumber\fR + 1.
|
|
.IP "\fB\-\-no\-pad\-sections\fR" 4
|
|
.IX Item "--no-pad-sections"
|
|
Stop the assembler for padding the ends of output sections to the alignment
|
|
of that section. The default is to pad the sections, but this can waste space
|
|
which might be needed on targets which have tight memory constraints.
|
|
.IP "\fB\-o\fR \fIobjfile\fR" 4
|
|
.IX Item "-o objfile"
|
|
Name the object-file output from \fBas\fR \fIobjfile\fR.
|
|
.IP "\fB\-R\fR" 4
|
|
.IX Item "-R"
|
|
Fold the data section into the text section.
|
|
.IP "\fB\-\-hash\-size=\fR\fInumber\fR" 4
|
|
.IX Item "--hash-size=number"
|
|
Set the default size of \s-1GAS\s0's hash tables to a prime number close to
|
|
\&\fInumber\fR. Increasing this value can reduce the length of time it takes the
|
|
assembler to perform its tasks, at the expense of increasing the assembler's
|
|
memory requirements. Similarly reducing this value can reduce the memory
|
|
requirements at the expense of speed.
|
|
.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
|
|
.IX Item "--reduce-memory-overheads"
|
|
This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
|
|
assembly processes slower. Currently this switch is a synonym for
|
|
\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
|
|
.IP "\fB\-\-sectname\-subst\fR" 4
|
|
.IX Item "--sectname-subst"
|
|
Honor substitution sequences in section names.
|
|
.IP "\fB\-\-statistics\fR" 4
|
|
.IX Item "--statistics"
|
|
Print the maximum space (in bytes) and total time (in seconds) used by
|
|
assembly.
|
|
.IP "\fB\-\-strip\-local\-absolute\fR" 4
|
|
.IX Item "--strip-local-absolute"
|
|
Remove local absolute symbols from the outgoing symbol table.
|
|
.IP "\fB\-v\fR" 4
|
|
.IX Item "-v"
|
|
.PD 0
|
|
.IP "\fB\-version\fR" 4
|
|
.IX Item "-version"
|
|
.PD
|
|
Print the \fBas\fR version.
|
|
.IP "\fB\-\-version\fR" 4
|
|
.IX Item "--version"
|
|
Print the \fBas\fR version and exit.
|
|
.IP "\fB\-W\fR" 4
|
|
.IX Item "-W"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-warn\fR" 4
|
|
.IX Item "--no-warn"
|
|
.PD
|
|
Suppress warning messages.
|
|
.IP "\fB\-\-fatal\-warnings\fR" 4
|
|
.IX Item "--fatal-warnings"
|
|
Treat warnings as errors.
|
|
.IP "\fB\-\-warn\fR" 4
|
|
.IX Item "--warn"
|
|
Don't suppress warning messages or treat them as errors.
|
|
.IP "\fB\-w\fR" 4
|
|
.IX Item "-w"
|
|
Ignored.
|
|
.IP "\fB\-x\fR" 4
|
|
.IX Item "-x"
|
|
Ignored.
|
|
.IP "\fB\-Z\fR" 4
|
|
.IX Item "-Z"
|
|
Generate an object file even after errors.
|
|
.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
|
|
.IX Item "-- | files ..."
|
|
Standard input, or source files to assemble.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
64\-bit mode of the \s-1ARM\s0 Architecture (AArch64).
|
|
.IP "\fB\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a big-endian processor.
|
|
.IP "\fB\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a little-endian processor.
|
|
.IP "\fB\-mabi=\fR\fIabi\fR" 4
|
|
.IX Item "-mabi=abi"
|
|
Specify which \s-1ABI\s0 the source code uses. The recognized arguments
|
|
are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object
|
|
file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR.
|
|
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-mcpu=processor[+extension...]"
|
|
This option specifies the target processor. The assembler will issue an error
|
|
message if an attempt is made to assemble an instruction which will not execute
|
|
on the target processor. The following processor names are recognized:
|
|
\&\f(CW\*(C`cortex\-a35\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a53\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a55\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a57\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a72\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a73\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a75\*(C'\fR,
|
|
\&\f(CW\*(C`cortex\-a76\*(C'\fR,
|
|
\&\f(CW\*(C`exynos\-m1\*(C'\fR,
|
|
\&\f(CW\*(C`falkor\*(C'\fR,
|
|
\&\f(CW\*(C`qdf24xx\*(C'\fR,
|
|
\&\f(CW\*(C`saphira\*(C'\fR,
|
|
\&\f(CW\*(C`thunderx\*(C'\fR,
|
|
\&\f(CW\*(C`vulcan\*(C'\fR,
|
|
\&\f(CW\*(C`xgene1\*(C'\fR
|
|
and
|
|
\&\f(CW\*(C`xgene2\*(C'\fR.
|
|
The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
|
|
instructions valid for any supported processor, including all optional
|
|
extensions.
|
|
.Sp
|
|
In addition to the basic instruction set, the assembler can be told to
|
|
accept, or restrict, various extension mnemonics that extend the
|
|
processor.
|
|
.Sp
|
|
If some implementations of a particular processor can have an
|
|
extension, then then those extensions are automatically enabled.
|
|
Consequently, you will not normally have to specify any additional
|
|
extensions.
|
|
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-march=architecture[+extension...]"
|
|
This option specifies the target architecture. The assembler will
|
|
issue an error message if an attempt is made to assemble an
|
|
instruction which will not execute on the target architecture. The
|
|
following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR,
|
|
\&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR and \f(CW\*(C`armv8.4\-a\*(C'\fR.
|
|
.Sp
|
|
If both \fB\-mcpu\fR and \fB\-march\fR are specified, the
|
|
assembler will use the setting for \fB\-mcpu\fR. If neither are
|
|
specified, the assembler will default to \fB\-mcpu=all\fR.
|
|
.Sp
|
|
The architecture option can be extended with the same instruction set
|
|
extension options as the \fB\-mcpu\fR option. Unlike
|
|
\&\fB\-mcpu\fR, extensions are not always enabled by default,
|
|
.IP "\fB\-mverbose\-error\fR" 4
|
|
.IX Item "-mverbose-error"
|
|
This option enables verbose error messages for AArch64 gas. This option
|
|
is enabled by default.
|
|
.IP "\fB\-mno\-verbose\-error\fR" 4
|
|
.IX Item "-mno-verbose-error"
|
|
This option disables verbose error messages in AArch64 gas.
|
|
.PP
|
|
The following options are available when as is configured for an Alpha
|
|
processor.
|
|
.IP "\fB\-m\fR\fIcpu\fR" 4
|
|
.IX Item "-mcpu"
|
|
This option specifies the target processor. If an attempt is made to
|
|
assemble an instruction which will not execute on the target processor,
|
|
the assembler may either expand the instruction as a macro or issue an
|
|
error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive.
|
|
.Sp
|
|
The following processor names are recognized:
|
|
\&\f(CW21064\fR,
|
|
\&\f(CW\*(C`21064a\*(C'\fR,
|
|
\&\f(CW21066\fR,
|
|
\&\f(CW21068\fR,
|
|
\&\f(CW21164\fR,
|
|
\&\f(CW\*(C`21164a\*(C'\fR,
|
|
\&\f(CW\*(C`21164pc\*(C'\fR,
|
|
\&\f(CW21264\fR,
|
|
\&\f(CW\*(C`21264a\*(C'\fR,
|
|
\&\f(CW\*(C`21264b\*(C'\fR,
|
|
\&\f(CW\*(C`ev4\*(C'\fR,
|
|
\&\f(CW\*(C`ev5\*(C'\fR,
|
|
\&\f(CW\*(C`lca45\*(C'\fR,
|
|
\&\f(CW\*(C`ev5\*(C'\fR,
|
|
\&\f(CW\*(C`ev56\*(C'\fR,
|
|
\&\f(CW\*(C`pca56\*(C'\fR,
|
|
\&\f(CW\*(C`ev6\*(C'\fR,
|
|
\&\f(CW\*(C`ev67\*(C'\fR,
|
|
\&\f(CW\*(C`ev68\*(C'\fR.
|
|
The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
|
|
instructions valid for any Alpha processor.
|
|
.Sp
|
|
In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR,
|
|
and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the
|
|
numbered processor names (e.g. 21064) enable the processor-specific PALcode
|
|
instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not.
|
|
.IP "\fB\-mdebug\fR" 4
|
|
.IX Item "-mdebug"
|
|
.PD 0
|
|
.IP "\fB\-no\-mdebug\fR" 4
|
|
.IX Item "-no-mdebug"
|
|
.PD
|
|
Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for
|
|
stabs directives and procedure descriptors. The default is to automatically
|
|
enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
|
|
.IP "\fB\-relax\fR" 4
|
|
.IX Item "-relax"
|
|
This option forces all relocations to be put into the object file, instead
|
|
of saving space and resolving some relocations at assembly time. Note that
|
|
this option does not propagate all symbol arithmetic into the object file,
|
|
because not all symbol arithmetic can be represented. However, the option
|
|
can still be useful in specific applications.
|
|
.IP "\fB\-replace\fR" 4
|
|
.IX Item "-replace"
|
|
.PD 0
|
|
.IP "\fB\-noreplace\fR" 4
|
|
.IX Item "-noreplace"
|
|
.PD
|
|
Enables or disables the optimization of procedure calls, both at assemblage
|
|
and at link time. These options are only available for \s-1VMS\s0 targets and
|
|
\&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker
|
|
Utility Manual.
|
|
.IP "\fB\-g\fR" 4
|
|
.IX Item "-g"
|
|
This option is used when the compiler generates debug information. When
|
|
\&\fBgcc\fR is using \fBmips-tfile\fR to generate debug
|
|
information for \s-1ECOFF,\s0 local labels must be passed through to the object
|
|
file. Otherwise this option has no effect.
|
|
.IP "\fB\-G\fR\fIsize\fR" 4
|
|
.IX Item "-Gsize"
|
|
A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR,
|
|
while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.
|
|
.IP "\fB\-F\fR" 4
|
|
.IX Item "-F"
|
|
.PD 0
|
|
.IP "\fB\-32addr\fR" 4
|
|
.IX Item "-32addr"
|
|
.PD
|
|
These options are ignored for backward compatibility.
|
|
.PP
|
|
The following options are available when as is configured for an \s-1ARC\s0
|
|
processor.
|
|
.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
|
|
.IX Item "-mcpu=cpu"
|
|
This option selects the core processor variant.
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
|
.IX Item "-EB | -EL"
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
|
.IP "\fB\-mcode\-density\fR" 4
|
|
.IX Item "-mcode-density"
|
|
Enable Code Density extenssion instructions.
|
|
.PP
|
|
The following options are available when as is configured for the \s-1ARM\s0
|
|
processor family.
|
|
.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-mcpu=processor[+extension...]"
|
|
Specify which \s-1ARM\s0 processor variant is the target.
|
|
.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
|
|
.IX Item "-march=architecture[+extension...]"
|
|
Specify which \s-1ARM\s0 architecture variant is used by the target.
|
|
.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
|
|
.IX Item "-mfpu=floating-point-format"
|
|
Select which Floating Point architecture is the target.
|
|
.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
|
|
.IX Item "-mfloat-abi=abi"
|
|
Select which floating point \s-1ABI\s0 is in use.
|
|
.IP "\fB\-mthumb\fR" 4
|
|
.IX Item "-mthumb"
|
|
Enable Thumb only instruction decoding.
|
|
.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
|
|
.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
|
|
Select which procedure calling convention is in use.
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
|
.IX Item "-EB | -EL"
|
|
Select either big-endian (\-EB) or little-endian (\-EL) output.
|
|
.IP "\fB\-mthumb\-interwork\fR" 4
|
|
.IX Item "-mthumb-interwork"
|
|
Specify that the code has been generated with interworking between Thumb and
|
|
\&\s-1ARM\s0 code in mind.
|
|
.IP "\fB\-mccs\fR" 4
|
|
.IX Item "-mccs"
|
|
Turns on CodeComposer Studio assembly syntax compatibility mode.
|
|
.IP "\fB\-k\fR" 4
|
|
.IX Item "-k"
|
|
Specify that \s-1PIC\s0 code has been generated.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
the Blackfin processor family.
|
|
.IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4
|
|
.IX Item "-mcpu=processor[-sirevision]"
|
|
This option specifies the target processor. The optional \fIsirevision\fR
|
|
is not used in assembler. It's here such that \s-1GCC\s0 can easily pass down its
|
|
\&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an
|
|
error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target processor. The following processor names are
|
|
recognized:
|
|
\&\f(CW\*(C`bf504\*(C'\fR,
|
|
\&\f(CW\*(C`bf506\*(C'\fR,
|
|
\&\f(CW\*(C`bf512\*(C'\fR,
|
|
\&\f(CW\*(C`bf514\*(C'\fR,
|
|
\&\f(CW\*(C`bf516\*(C'\fR,
|
|
\&\f(CW\*(C`bf518\*(C'\fR,
|
|
\&\f(CW\*(C`bf522\*(C'\fR,
|
|
\&\f(CW\*(C`bf523\*(C'\fR,
|
|
\&\f(CW\*(C`bf524\*(C'\fR,
|
|
\&\f(CW\*(C`bf525\*(C'\fR,
|
|
\&\f(CW\*(C`bf526\*(C'\fR,
|
|
\&\f(CW\*(C`bf527\*(C'\fR,
|
|
\&\f(CW\*(C`bf531\*(C'\fR,
|
|
\&\f(CW\*(C`bf532\*(C'\fR,
|
|
\&\f(CW\*(C`bf533\*(C'\fR,
|
|
\&\f(CW\*(C`bf534\*(C'\fR,
|
|
\&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),
|
|
\&\f(CW\*(C`bf536\*(C'\fR,
|
|
\&\f(CW\*(C`bf537\*(C'\fR,
|
|
\&\f(CW\*(C`bf538\*(C'\fR,
|
|
\&\f(CW\*(C`bf539\*(C'\fR,
|
|
\&\f(CW\*(C`bf542\*(C'\fR,
|
|
\&\f(CW\*(C`bf542m\*(C'\fR,
|
|
\&\f(CW\*(C`bf544\*(C'\fR,
|
|
\&\f(CW\*(C`bf544m\*(C'\fR,
|
|
\&\f(CW\*(C`bf547\*(C'\fR,
|
|
\&\f(CW\*(C`bf547m\*(C'\fR,
|
|
\&\f(CW\*(C`bf548\*(C'\fR,
|
|
\&\f(CW\*(C`bf548m\*(C'\fR,
|
|
\&\f(CW\*(C`bf549\*(C'\fR,
|
|
\&\f(CW\*(C`bf549m\*(C'\fR,
|
|
\&\f(CW\*(C`bf561\*(C'\fR,
|
|
and
|
|
\&\f(CW\*(C`bf592\*(C'\fR.
|
|
.IP "\fB\-mfdpic\fR" 4
|
|
.IX Item "-mfdpic"
|
|
Assemble for the \s-1FDPIC ABI.\s0
|
|
.IP "\fB\-mno\-fdpic\fR" 4
|
|
.IX Item "-mno-fdpic"
|
|
.PD 0
|
|
.IP "\fB\-mnopic\fR" 4
|
|
.IX Item "-mnopic"
|
|
.PD
|
|
Disable \-mfdpic.
|
|
.PP
|
|
See the info pages for documentation of the CRIS-specific options.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a D10V processor.
|
|
.IP "\fB\-O\fR" 4
|
|
.IX Item "-O"
|
|
Optimize output by parallelizing instructions.
|
|
.PP
|
|
The following options are available when as is configured for a D30V
|
|
processor.
|
|
.IP "\fB\-O\fR" 4
|
|
.IX Item "-O"
|
|
Optimize output by parallelizing instructions.
|
|
.IP "\fB\-n\fR" 4
|
|
.IX Item "-n"
|
|
Warn when nops are generated.
|
|
.IP "\fB\-N\fR" 4
|
|
.IX Item "-N"
|
|
Warn when a nop after a 32\-bit multiply instruction is generated.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
an Epiphany processor.
|
|
.IP "\fB\-mepiphany\fR" 4
|
|
.IX Item "-mepiphany"
|
|
Specifies that the both 32 and 16 bit instructions are allowed. This is the
|
|
default behavior.
|
|
.IP "\fB\-mepiphany16\fR" 4
|
|
.IX Item "-mepiphany16"
|
|
Restricts the permitted instructions to just the 16 bit set.
|
|
.PP
|
|
The following options are available when as is configured for an H8/300
|
|
processor.
|
|
\&\f(CW@chapter\fR H8/300 Dependent Features
|
|
.SS "Options"
|
|
.IX Subsection "Options"
|
|
The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one
|
|
machine-dependent option:
|
|
.IP "\fB\-h\-tick\-hex\fR" 4
|
|
.IX Item "-h-tick-hex"
|
|
Support H'00 style hex constants in addition to 0x00 style.
|
|
.IP "\fB\-mach=\fR\fIname\fR" 4
|
|
.IX Item "-mach=name"
|
|
Sets the H8300 machine variant. The following machine names
|
|
are recognised:
|
|
\&\f(CW\*(C`h8300h\*(C'\fR,
|
|
\&\f(CW\*(C`h8300hn\*(C'\fR,
|
|
\&\f(CW\*(C`h8300s\*(C'\fR,
|
|
\&\f(CW\*(C`h8300sn\*(C'\fR,
|
|
\&\f(CW\*(C`h8300sx\*(C'\fR and
|
|
\&\f(CW\*(C`h8300sxn\*(C'\fR.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
an i386 processor.
|
|
.IP "\fB\-\-32 | \-\-x32 | \-\-64\fR" 4
|
|
.IX Item "--32 | --x32 | --64"
|
|
Select the word size, either 32 bits or 64 bits. \fB\-\-32\fR
|
|
implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR
|
|
imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size
|
|
respectively.
|
|
.Sp
|
|
These options are only available with the \s-1ELF\s0 object file format, and
|
|
require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit
|
|
platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit
|
|
usage and use x86\-64 as target platform).
|
|
.IP "\fB\-n\fR" 4
|
|
.IX Item "-n"
|
|
By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for
|
|
alignment within code sections with multi-byte nop instructions such
|
|
as leal 0(%esi,1),%esi. This switch disables the optimization if a single
|
|
byte nop (0x90) is explicitly specified as the fill byte for alignment.
|
|
.IP "\fB\-\-divide\fR" 4
|
|
.IX Item "--divide"
|
|
On SVR4\-derived platforms, the character \fB/\fR is treated as a comment
|
|
character, which means that it cannot be used in expressions. The
|
|
\&\fB\-\-divide\fR option turns \fB/\fR into a normal character. This does
|
|
not disable \fB/\fR at the beginning of a line starting a comment, or
|
|
affect using \fB#\fR for starting a comment.
|
|
.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4
|
|
.IX Item "-march=CPU[+EXTENSION...]"
|
|
This option specifies the target processor. The assembler will
|
|
issue an error message if an attempt is made to assemble an instruction
|
|
which will not execute on the target processor. The following
|
|
processor names are recognized:
|
|
\&\f(CW\*(C`i8086\*(C'\fR,
|
|
\&\f(CW\*(C`i186\*(C'\fR,
|
|
\&\f(CW\*(C`i286\*(C'\fR,
|
|
\&\f(CW\*(C`i386\*(C'\fR,
|
|
\&\f(CW\*(C`i486\*(C'\fR,
|
|
\&\f(CW\*(C`i586\*(C'\fR,
|
|
\&\f(CW\*(C`i686\*(C'\fR,
|
|
\&\f(CW\*(C`pentium\*(C'\fR,
|
|
\&\f(CW\*(C`pentiumpro\*(C'\fR,
|
|
\&\f(CW\*(C`pentiumii\*(C'\fR,
|
|
\&\f(CW\*(C`pentiumiii\*(C'\fR,
|
|
\&\f(CW\*(C`pentium4\*(C'\fR,
|
|
\&\f(CW\*(C`prescott\*(C'\fR,
|
|
\&\f(CW\*(C`nocona\*(C'\fR,
|
|
\&\f(CW\*(C`core\*(C'\fR,
|
|
\&\f(CW\*(C`core2\*(C'\fR,
|
|
\&\f(CW\*(C`corei7\*(C'\fR,
|
|
\&\f(CW\*(C`l1om\*(C'\fR,
|
|
\&\f(CW\*(C`k1om\*(C'\fR,
|
|
\&\f(CW\*(C`iamcu\*(C'\fR,
|
|
\&\f(CW\*(C`k6\*(C'\fR,
|
|
\&\f(CW\*(C`k6_2\*(C'\fR,
|
|
\&\f(CW\*(C`athlon\*(C'\fR,
|
|
\&\f(CW\*(C`opteron\*(C'\fR,
|
|
\&\f(CW\*(C`k8\*(C'\fR,
|
|
\&\f(CW\*(C`amdfam10\*(C'\fR,
|
|
\&\f(CW\*(C`bdver1\*(C'\fR,
|
|
\&\f(CW\*(C`bdver2\*(C'\fR,
|
|
\&\f(CW\*(C`bdver3\*(C'\fR,
|
|
\&\f(CW\*(C`bdver4\*(C'\fR,
|
|
\&\f(CW\*(C`znver1\*(C'\fR,
|
|
\&\f(CW\*(C`znver2\*(C'\fR,
|
|
\&\f(CW\*(C`btver1\*(C'\fR,
|
|
\&\f(CW\*(C`btver2\*(C'\fR,
|
|
\&\f(CW\*(C`generic32\*(C'\fR and
|
|
\&\f(CW\*(C`generic64\*(C'\fR.
|
|
.Sp
|
|
In addition to the basic instruction set, the assembler can be told to
|
|
accept various extension mnemonics. For example,
|
|
\&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and
|
|
\&\fIvmx\fR. The following extensions are currently supported:
|
|
\&\f(CW8087\fR,
|
|
\&\f(CW287\fR,
|
|
\&\f(CW387\fR,
|
|
\&\f(CW687\fR,
|
|
\&\f(CW\*(C`no87\*(C'\fR,
|
|
\&\f(CW\*(C`no287\*(C'\fR,
|
|
\&\f(CW\*(C`no387\*(C'\fR,
|
|
\&\f(CW\*(C`no687\*(C'\fR,
|
|
\&\f(CW\*(C`mmx\*(C'\fR,
|
|
\&\f(CW\*(C`nommx\*(C'\fR,
|
|
\&\f(CW\*(C`sse\*(C'\fR,
|
|
\&\f(CW\*(C`sse2\*(C'\fR,
|
|
\&\f(CW\*(C`sse3\*(C'\fR,
|
|
\&\f(CW\*(C`ssse3\*(C'\fR,
|
|
\&\f(CW\*(C`sse4.1\*(C'\fR,
|
|
\&\f(CW\*(C`sse4.2\*(C'\fR,
|
|
\&\f(CW\*(C`sse4\*(C'\fR,
|
|
\&\f(CW\*(C`nosse\*(C'\fR,
|
|
\&\f(CW\*(C`nosse2\*(C'\fR,
|
|
\&\f(CW\*(C`nosse3\*(C'\fR,
|
|
\&\f(CW\*(C`nossse3\*(C'\fR,
|
|
\&\f(CW\*(C`nosse4.1\*(C'\fR,
|
|
\&\f(CW\*(C`nosse4.2\*(C'\fR,
|
|
\&\f(CW\*(C`nosse4\*(C'\fR,
|
|
\&\f(CW\*(C`avx\*(C'\fR,
|
|
\&\f(CW\*(C`avx2\*(C'\fR,
|
|
\&\f(CW\*(C`noavx\*(C'\fR,
|
|
\&\f(CW\*(C`noavx2\*(C'\fR,
|
|
\&\f(CW\*(C`adx\*(C'\fR,
|
|
\&\f(CW\*(C`rdseed\*(C'\fR,
|
|
\&\f(CW\*(C`prfchw\*(C'\fR,
|
|
\&\f(CW\*(C`smap\*(C'\fR,
|
|
\&\f(CW\*(C`mpx\*(C'\fR,
|
|
\&\f(CW\*(C`sha\*(C'\fR,
|
|
\&\f(CW\*(C`rdpid\*(C'\fR,
|
|
\&\f(CW\*(C`ptwrite\*(C'\fR,
|
|
\&\f(CW\*(C`cet\*(C'\fR,
|
|
\&\f(CW\*(C`gfni\*(C'\fR,
|
|
\&\f(CW\*(C`vaes\*(C'\fR,
|
|
\&\f(CW\*(C`vpclmulqdq\*(C'\fR,
|
|
\&\f(CW\*(C`prefetchwt1\*(C'\fR,
|
|
\&\f(CW\*(C`clflushopt\*(C'\fR,
|
|
\&\f(CW\*(C`se1\*(C'\fR,
|
|
\&\f(CW\*(C`clwb\*(C'\fR,
|
|
\&\f(CW\*(C`movdiri\*(C'\fR,
|
|
\&\f(CW\*(C`movdir64b\*(C'\fR,
|
|
\&\f(CW\*(C`avx512f\*(C'\fR,
|
|
\&\f(CW\*(C`avx512cd\*(C'\fR,
|
|
\&\f(CW\*(C`avx512er\*(C'\fR,
|
|
\&\f(CW\*(C`avx512pf\*(C'\fR,
|
|
\&\f(CW\*(C`avx512vl\*(C'\fR,
|
|
\&\f(CW\*(C`avx512bw\*(C'\fR,
|
|
\&\f(CW\*(C`avx512dq\*(C'\fR,
|
|
\&\f(CW\*(C`avx512ifma\*(C'\fR,
|
|
\&\f(CW\*(C`avx512vbmi\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_4fmaps\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_4vnniw\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_vpopcntdq\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_vbmi2\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_vnni\*(C'\fR,
|
|
\&\f(CW\*(C`avx512_bitalg\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512f\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512cd\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512er\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512pf\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512vl\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512bw\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512dq\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512ifma\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512vbmi\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_4fmaps\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_4vnniw\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_vpopcntdq\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_vbmi2\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_vnni\*(C'\fR,
|
|
\&\f(CW\*(C`noavx512_bitalg\*(C'\fR,
|
|
\&\f(CW\*(C`vmx\*(C'\fR,
|
|
\&\f(CW\*(C`vmfunc\*(C'\fR,
|
|
\&\f(CW\*(C`smx\*(C'\fR,
|
|
\&\f(CW\*(C`xsave\*(C'\fR,
|
|
\&\f(CW\*(C`xsaveopt\*(C'\fR,
|
|
\&\f(CW\*(C`xsavec\*(C'\fR,
|
|
\&\f(CW\*(C`xsaves\*(C'\fR,
|
|
\&\f(CW\*(C`aes\*(C'\fR,
|
|
\&\f(CW\*(C`pclmul\*(C'\fR,
|
|
\&\f(CW\*(C`fsgsbase\*(C'\fR,
|
|
\&\f(CW\*(C`rdrnd\*(C'\fR,
|
|
\&\f(CW\*(C`f16c\*(C'\fR,
|
|
\&\f(CW\*(C`bmi2\*(C'\fR,
|
|
\&\f(CW\*(C`fma\*(C'\fR,
|
|
\&\f(CW\*(C`movbe\*(C'\fR,
|
|
\&\f(CW\*(C`ept\*(C'\fR,
|
|
\&\f(CW\*(C`lzcnt\*(C'\fR,
|
|
\&\f(CW\*(C`hle\*(C'\fR,
|
|
\&\f(CW\*(C`rtm\*(C'\fR,
|
|
\&\f(CW\*(C`invpcid\*(C'\fR,
|
|
\&\f(CW\*(C`clflush\*(C'\fR,
|
|
\&\f(CW\*(C`mwaitx\*(C'\fR,
|
|
\&\f(CW\*(C`clzero\*(C'\fR,
|
|
\&\f(CW\*(C`wbnoinvd\*(C'\fR,
|
|
\&\f(CW\*(C`pconfig\*(C'\fR,
|
|
\&\f(CW\*(C`waitpkg\*(C'\fR,
|
|
\&\f(CW\*(C`cldemote\*(C'\fR,
|
|
\&\f(CW\*(C`lwp\*(C'\fR,
|
|
\&\f(CW\*(C`fma4\*(C'\fR,
|
|
\&\f(CW\*(C`xop\*(C'\fR,
|
|
\&\f(CW\*(C`cx16\*(C'\fR,
|
|
\&\f(CW\*(C`syscall\*(C'\fR,
|
|
\&\f(CW\*(C`rdtscp\*(C'\fR,
|
|
\&\f(CW\*(C`3dnow\*(C'\fR,
|
|
\&\f(CW\*(C`3dnowa\*(C'\fR,
|
|
\&\f(CW\*(C`sse4a\*(C'\fR,
|
|
\&\f(CW\*(C`sse5\*(C'\fR,
|
|
\&\f(CW\*(C`svme\*(C'\fR,
|
|
\&\f(CW\*(C`abm\*(C'\fR and
|
|
\&\f(CW\*(C`padlock\*(C'\fR.
|
|
Note that rather than extending a basic instruction set, the extension
|
|
mnemonics starting with \f(CW\*(C`no\*(C'\fR revoke the respective functionality.
|
|
.Sp
|
|
When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
|
|
\&\f(CW\*(C`.arch\*(C'\fR directive will take precedent.
|
|
.IP "\fB\-mtune=\fR\fI\s-1CPU\s0\fR" 4
|
|
.IX Item "-mtune=CPU"
|
|
This option specifies a processor to optimize for. When used in
|
|
conjunction with the \fB\-march\fR option, only instructions
|
|
of the processor specified by the \fB\-march\fR option will be
|
|
generated.
|
|
.Sp
|
|
Valid \fI\s-1CPU\s0\fR values are identical to the processor list of
|
|
\&\fB\-march=\fR\fI\s-1CPU\s0\fR.
|
|
.IP "\fB\-msse2avx\fR" 4
|
|
.IX Item "-msse2avx"
|
|
This option specifies that the assembler should encode \s-1SSE\s0 instructions
|
|
with \s-1VEX\s0 prefix.
|
|
.IP "\fB\-msse\-check=\fR\fInone\fR" 4
|
|
.IX Item "-msse-check=none"
|
|
.PD 0
|
|
.IP "\fB\-msse\-check=\fR\fIwarning\fR" 4
|
|
.IX Item "-msse-check=warning"
|
|
.IP "\fB\-msse\-check=\fR\fIerror\fR" 4
|
|
.IX Item "-msse-check=error"
|
|
.PD
|
|
These options control if the assembler should check \s-1SSE\s0 instructions.
|
|
\&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0
|
|
instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR
|
|
will make the assembler issue a warning for any \s-1SSE\s0 instruction.
|
|
\&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error
|
|
for any \s-1SSE\s0 instruction.
|
|
.IP "\fB\-mavxscalar=\fR\fI128\fR" 4
|
|
.IX Item "-mavxscalar=128"
|
|
.PD 0
|
|
.IP "\fB\-mavxscalar=\fR\fI256\fR" 4
|
|
.IX Item "-mavxscalar=256"
|
|
.PD
|
|
These options control how the assembler should encode scalar \s-1AVX\s0
|
|
instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar
|
|
\&\s-1AVX\s0 instructions with 128bit vector length, which is the default.
|
|
\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions
|
|
with 256bit vector length.
|
|
.IP "\fB\-mevexlig=\fR\fI128\fR" 4
|
|
.IX Item "-mevexlig=128"
|
|
.PD 0
|
|
.IP "\fB\-mevexlig=\fR\fI256\fR" 4
|
|
.IX Item "-mevexlig=256"
|
|
.IP "\fB\-mevexlig=\fR\fI512\fR" 4
|
|
.IX Item "-mevexlig=512"
|
|
.PD
|
|
These options control how the assembler should encode length-ignored
|
|
(\s-1LIG\s0) \s-1EVEX\s0 instructions. \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG
|
|
EVEX\s0 instructions with 128bit vector length, which is the default.
|
|
\&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will
|
|
encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length,
|
|
respectively.
|
|
.IP "\fB\-mevexwig=\fR\fI0\fR" 4
|
|
.IX Item "-mevexwig=0"
|
|
.PD 0
|
|
.IP "\fB\-mevexwig=\fR\fI1\fR" 4
|
|
.IX Item "-mevexwig=1"
|
|
.PD
|
|
These options control how the assembler should encode w\-ignored (\s-1WIG\s0)
|
|
\&\s-1EVEX\s0 instructions. \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG
|
|
EVEX\s0 instructions with evex.w = 0, which is the default.
|
|
\&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with
|
|
evex.w = 1.
|
|
.IP "\fB\-mmnemonic=\fR\fIatt\fR" 4
|
|
.IX Item "-mmnemonic=att"
|
|
.PD 0
|
|
.IP "\fB\-mmnemonic=\fR\fIintel\fR" 4
|
|
.IX Item "-mmnemonic=intel"
|
|
.PD
|
|
This option specifies instruction mnemonic for matching instructions.
|
|
The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will
|
|
take precedent.
|
|
.IP "\fB\-msyntax=\fR\fIatt\fR" 4
|
|
.IX Item "-msyntax=att"
|
|
.PD 0
|
|
.IP "\fB\-msyntax=\fR\fIintel\fR" 4
|
|
.IX Item "-msyntax=intel"
|
|
.PD
|
|
This option specifies instruction syntax when processing instructions.
|
|
The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will
|
|
take precedent.
|
|
.IP "\fB\-mnaked\-reg\fR" 4
|
|
.IX Item "-mnaked-reg"
|
|
This option specifies that registers don't require a \fB%\fR prefix.
|
|
The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent.
|
|
.IP "\fB\-madd\-bnd\-prefix\fR" 4
|
|
.IX Item "-madd-bnd-prefix"
|
|
This option forces the assembler to add \s-1BND\s0 prefix to all branches, even
|
|
if such prefix was not explicitly specified in the source code.
|
|
.IP "\fB\-mno\-shared\fR" 4
|
|
.IX Item "-mno-shared"
|
|
On \s-1ELF\s0 target, the assembler normally optimizes out non-PLT relocations
|
|
against defined non-weak global branch targets with default visibility.
|
|
The \fB\-mshared\fR option tells the assembler to generate code which
|
|
may go into a shared library where all non-weak global branch targets
|
|
with default visibility can be preempted. The resulting code is
|
|
slightly bigger. This option only affects the handling of branch
|
|
instructions.
|
|
.IP "\fB\-mbig\-obj\fR" 4
|
|
.IX Item "-mbig-obj"
|
|
On x86\-64 \s-1PE/COFF\s0 target this option forces the use of big object file
|
|
format, which allows more than 32768 sections.
|
|
.IP "\fB\-momit\-lock\-prefix=\fR\fIno\fR" 4
|
|
.IX Item "-momit-lock-prefix=no"
|
|
.PD 0
|
|
.IP "\fB\-momit\-lock\-prefix=\fR\fIyes\fR" 4
|
|
.IX Item "-momit-lock-prefix=yes"
|
|
.PD
|
|
These options control how the assembler should encode lock prefix.
|
|
This option is intended as a workaround for processors, that fail on
|
|
lock prefix. This option can only be safely used with single-core,
|
|
single-thread computers
|
|
\&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes.
|
|
\&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual,
|
|
which is the default.
|
|
.IP "\fB\-mfence\-as\-lock\-add=\fR\fIno\fR" 4
|
|
.IX Item "-mfence-as-lock-add=no"
|
|
.PD 0
|
|
.IP "\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR" 4
|
|
.IX Item "-mfence-as-lock-add=yes"
|
|
.PD
|
|
These options control how the assembler should encode lfence, mfence and
|
|
sfence.
|
|
\&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and
|
|
sfence as \fBlock addl \f(CB$0x0\fB, (%rsp)\fR in 64\-bit mode and
|
|
\&\fBlock addl \f(CB$0x0\fB, (%esp)\fR in 32\-bit mode.
|
|
\&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and
|
|
sfence as usual, which is the default.
|
|
.IP "\fB\-mrelax\-relocations=\fR\fIno\fR" 4
|
|
.IX Item "-mrelax-relocations=no"
|
|
.PD 0
|
|
.IP "\fB\-mrelax\-relocations=\fR\fIyes\fR" 4
|
|
.IX Item "-mrelax-relocations=yes"
|
|
.PD
|
|
These options control whether the assembler should generate relax
|
|
relocations, R_386_GOT32X, in 32\-bit mode, or R_X86_64_GOTPCRELX and
|
|
R_X86_64_REX_GOTPCRELX, in 64\-bit mode.
|
|
\&\fB\-mrelax\-relocations=\fR\fIyes\fR will generate relax relocations.
|
|
\&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax
|
|
relocations. The default can be controlled by a configure option
|
|
\&\fB\-\-enable\-x86\-relax\-relocations\fR.
|
|
.IP "\fB\-mevexrcig=\fR\fIrne\fR" 4
|
|
.IX Item "-mevexrcig=rne"
|
|
.PD 0
|
|
.IP "\fB\-mevexrcig=\fR\fIrd\fR" 4
|
|
.IX Item "-mevexrcig=rd"
|
|
.IP "\fB\-mevexrcig=\fR\fIru\fR" 4
|
|
.IX Item "-mevexrcig=ru"
|
|
.IP "\fB\-mevexrcig=\fR\fIrz\fR" 4
|
|
.IX Item "-mevexrcig=rz"
|
|
.PD
|
|
These options control how the assembler should encode SAE-only
|
|
\&\s-1EVEX\s0 instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode \s-1RC\s0 bits
|
|
of \s-1EVEX\s0 instruction with 00, which is the default.
|
|
\&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR
|
|
and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only \s-1EVEX\s0 instructions
|
|
with 01, 10 and 11 \s-1RC\s0 bits, respectively.
|
|
.IP "\fB\-mamd64\fR" 4
|
|
.IX Item "-mamd64"
|
|
.PD 0
|
|
.IP "\fB\-mintel64\fR" 4
|
|
.IX Item "-mintel64"
|
|
.PD
|
|
This option specifies that the assembler should accept only \s-1AMD64\s0 or
|
|
Intel64 \s-1ISA\s0 in 64\-bit mode. The default is to accept both.
|
|
.IP "\fB\-O0 | \-O | \-O1 | \-O2 | \-Os\fR" 4
|
|
.IX Item "-O0 | -O | -O1 | -O2 | -Os"
|
|
Optimize instruction encoding with smaller instruction size. \fB\-O\fR
|
|
and \fB\-O1\fR encode 64\-bit register load instructions with 64\-bit
|
|
immediate as 32\-bit register load instructions with 31\-bit or 32\-bits
|
|
immediates and encode 64\-bit register clearing instructions with 32\-bit
|
|
register clearing instructions. \fB\-O2\fR includes \fB\-O1\fR
|
|
optimization plus encodes 256\-bit and 512\-bit vector register clearing
|
|
instructions with 128\-bit vector register clearing instructions.
|
|
\&\fB\-Os\fR includes \fB\-O2\fR optimization plus encodes 16\-bit, 32\-bit
|
|
and 64\-bit register tests with immediate as 8\-bit register test with
|
|
immediate. \fB\-O0\fR turns off this optimization.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Ubicom \s-1IP2K\s0 series.
|
|
.IP "\fB\-mip2022ext\fR" 4
|
|
.IX Item "-mip2022ext"
|
|
Specifies that the extended \s-1IP2022\s0 instructions are allowed.
|
|
.IP "\fB\-mip2022\fR" 4
|
|
.IX Item "-mip2022"
|
|
Restores the default behaviour, which restricts the permitted instructions to
|
|
just the basic \s-1IP2022\s0 ones.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Renesas M32C and M16C processors.
|
|
.IP "\fB\-m32c\fR" 4
|
|
.IX Item "-m32c"
|
|
Assemble M32C instructions.
|
|
.IP "\fB\-m16c\fR" 4
|
|
.IX Item "-m16c"
|
|
Assemble M16C instructions (the default).
|
|
.IP "\fB\-relax\fR" 4
|
|
.IX Item "-relax"
|
|
Enable support for link-time relaxations.
|
|
.IP "\fB\-h\-tick\-hex\fR" 4
|
|
.IX Item "-h-tick-hex"
|
|
Support H'00 style hex constants in addition to 0x00 style.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Renesas M32R (formerly Mitsubishi M32R) series.
|
|
.IP "\fB\-\-m32rx\fR" 4
|
|
.IX Item "--m32rx"
|
|
Specify which processor in the M32R family is the target. The default
|
|
is normally the M32R, but this option changes it to the M32RX.
|
|
.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
|
|
.IX Item "--warn-explicit-parallel-conflicts or --Wp"
|
|
Produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
|
|
.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
|
|
Do not produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
.PP
|
|
The following options are available when as is configured for the
|
|
Motorola 68000 series.
|
|
.IP "\fB\-l\fR" 4
|
|
.IX Item "-l"
|
|
Shorten references to undefined symbols, to one word instead of two.
|
|
.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
|
|
.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
|
|
.PD 0
|
|
.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
|
|
.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
|
|
.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
|
|
.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
|
|
.PD
|
|
Specify what processor in the 68000 family is the target. The default
|
|
is normally the 68020, but this can be changed at configuration time.
|
|
.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
|
|
.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
|
|
The target machine does (or does not) have a floating-point coprocessor.
|
|
The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
|
|
the basic 68000 is not compatible with the 68881, a combination of the
|
|
two can be specified, since it's possible to do emulation of the
|
|
coprocessor instructions with the main processor.
|
|
.IP "\fB\-m68851 | \-mno\-68851\fR" 4
|
|
.IX Item "-m68851 | -mno-68851"
|
|
The target machine does (or does not) have a memory-management
|
|
unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
|
|
.PP
|
|
The following options are available when as is configured for an
|
|
Altera Nios \s-1II\s0 processor.
|
|
.IP "\fB\-relax\-section\fR" 4
|
|
.IX Item "-relax-section"
|
|
Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR
|
|
sequences when possible. The generated code sequences are suitable
|
|
for use in position-independent code, but there is a practical limit
|
|
on the extended branch range because of the length of the sequences.
|
|
This option is the default.
|
|
.IP "\fB\-relax\-all\fR" 4
|
|
.IX Item "-relax-all"
|
|
Replace branch instructions not determinable to be in range
|
|
and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences
|
|
(respectively). This option generates absolute relocations against the
|
|
target symbols and is not appropriate for position-independent code.
|
|
.IP "\fB\-no\-relax\fR" 4
|
|
.IX Item "-no-relax"
|
|
Do not replace any branches or calls.
|
|
.IP "\fB\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
Generate big-endian output.
|
|
.IP "\fB\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
Generate little-endian output. This is the default.
|
|
.IP "\fB\-march=\fR\fIarchitecture\fR" 4
|
|
.IX Item "-march=architecture"
|
|
This option specifies the target architecture. The assembler issues
|
|
an error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target architecture. The following architecture
|
|
names are recognized:
|
|
\&\f(CW\*(C`r1\*(C'\fR,
|
|
\&\f(CW\*(C`r2\*(C'\fR.
|
|
The default is \f(CW\*(C`r1\*(C'\fR.
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
\&\s-1PRU\s0 processor.
|
|
.IP "\fB\-mlink\-relax\fR" 4
|
|
.IX Item "-mlink-relax"
|
|
Assume that \s-1LD\s0 would optimize \s-1LDI32\s0 instructions by checking the upper
|
|
16 bits of the \fIexpression\fR. If they are all zeros, then \s-1LD\s0 would
|
|
shorten the \s-1LDI32\s0 instruction to a single \s-1LDI.\s0 In such case \f(CW\*(C`as\*(C'\fR
|
|
will output \s-1DIFF\s0 relocations for diff expressions.
|
|
.IP "\fB\-mno\-link\-relax\fR" 4
|
|
.IX Item "-mno-link-relax"
|
|
Assume that \s-1LD\s0 would not optimize \s-1LDI32\s0 instructions. As a consequence,
|
|
\&\s-1DIFF\s0 relocations will not be emitted.
|
|
.IP "\fB\-mno\-warn\-regname\-label\fR" 4
|
|
.IX Item "-mno-warn-regname-label"
|
|
Do not warn if a label name matches a register name. Usually assembler
|
|
programmers will want this warning to be emitted. C compilers may want
|
|
to turn this off.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a \s-1MIPS\s0 processor.
|
|
.IP "\fB\-G\fR \fInum\fR" 4
|
|
.IX Item "-G num"
|
|
This option sets the largest size of an object that can be referenced
|
|
implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
|
|
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
|
|
.IP "\fB\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
Generate \*(L"big endian\*(R" format output.
|
|
.IP "\fB\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
Generate \*(L"little endian\*(R" format output.
|
|
.IP "\fB\-mips1\fR" 4
|
|
.IX Item "-mips1"
|
|
.PD 0
|
|
.IP "\fB\-mips2\fR" 4
|
|
.IX Item "-mips2"
|
|
.IP "\fB\-mips3\fR" 4
|
|
.IX Item "-mips3"
|
|
.IP "\fB\-mips4\fR" 4
|
|
.IX Item "-mips4"
|
|
.IP "\fB\-mips5\fR" 4
|
|
.IX Item "-mips5"
|
|
.IP "\fB\-mips32\fR" 4
|
|
.IX Item "-mips32"
|
|
.IP "\fB\-mips32r2\fR" 4
|
|
.IX Item "-mips32r2"
|
|
.IP "\fB\-mips32r3\fR" 4
|
|
.IX Item "-mips32r3"
|
|
.IP "\fB\-mips32r5\fR" 4
|
|
.IX Item "-mips32r5"
|
|
.IP "\fB\-mips32r6\fR" 4
|
|
.IX Item "-mips32r6"
|
|
.IP "\fB\-mips64\fR" 4
|
|
.IX Item "-mips64"
|
|
.IP "\fB\-mips64r2\fR" 4
|
|
.IX Item "-mips64r2"
|
|
.IP "\fB\-mips64r3\fR" 4
|
|
.IX Item "-mips64r3"
|
|
.IP "\fB\-mips64r5\fR" 4
|
|
.IX Item "-mips64r5"
|
|
.IP "\fB\-mips64r6\fR" 4
|
|
.IX Item "-mips64r6"
|
|
.PD
|
|
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
|
|
\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
|
|
alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
|
|
\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
|
|
\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips32r3\fR,
|
|
\&\fB\-mips32r5\fR, \fB\-mips32r6\fR, \fB\-mips64\fR, \fB\-mips64r2\fR,
|
|
\&\fB\-mips64r3\fR, \fB\-mips64r5\fR, and \fB\-mips64r6\fR correspond to generic
|
|
\&\s-1MIPS V, MIPS32, MIPS32\s0 Release 2, \s-1MIPS32\s0 Release 3, \s-1MIPS32\s0 Release 5, \s-1MIPS32\s0
|
|
Release 6, \s-1MIPS64, MIPS64\s0 Release 2, \s-1MIPS64\s0 Release 3, \s-1MIPS64\s0 Release 5, and
|
|
\&\s-1MIPS64\s0 Release 6 \s-1ISA\s0 processors, respectively.
|
|
.IP "\fB\-march=\fR\fIcpu\fR" 4
|
|
.IX Item "-march=cpu"
|
|
Generate code for a particular \s-1MIPS CPU.\s0
|
|
.IP "\fB\-mtune=\fR\fIcpu\fR" 4
|
|
.IX Item "-mtune=cpu"
|
|
Schedule and tune for a particular \s-1MIPS CPU.\s0
|
|
.IP "\fB\-mfix7000\fR" 4
|
|
.IX Item "-mfix7000"
|
|
.PD 0
|
|
.IP "\fB\-mno\-fix7000\fR" 4
|
|
.IX Item "-mno-fix7000"
|
|
.PD
|
|
Cause nops to be inserted if the read of the destination register
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
.IP "\fB\-mfix\-rm7000\fR" 4
|
|
.IX Item "-mfix-rm7000"
|
|
.PD 0
|
|
.IP "\fB\-mno\-fix\-rm7000\fR" 4
|
|
.IX Item "-mno-fix-rm7000"
|
|
.PD
|
|
Cause nops to be inserted if a dmult or dmultu instruction is
|
|
followed by a load instruction.
|
|
.IP "\fB\-mdebug\fR" 4
|
|
.IX Item "-mdebug"
|
|
.PD 0
|
|
.IP "\fB\-no\-mdebug\fR" 4
|
|
.IX Item "-no-mdebug"
|
|
.PD
|
|
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
|
|
section instead of the standard \s-1ELF\s0 .stabs sections.
|
|
.IP "\fB\-mpdr\fR" 4
|
|
.IX Item "-mpdr"
|
|
.PD 0
|
|
.IP "\fB\-mno\-pdr\fR" 4
|
|
.IX Item "-mno-pdr"
|
|
.PD
|
|
Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
|
|
.IP "\fB\-mgp32\fR" 4
|
|
.IX Item "-mgp32"
|
|
.PD 0
|
|
.IP "\fB\-mfp32\fR" 4
|
|
.IX Item "-mfp32"
|
|
.PD
|
|
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these
|
|
flags force a certain group of registers to be treated as 32 bits wide at
|
|
all times. \fB\-mgp32\fR controls the size of general-purpose registers
|
|
and \fB\-mfp32\fR controls the size of floating-point registers.
|
|
.IP "\fB\-mgp64\fR" 4
|
|
.IX Item "-mgp64"
|
|
.PD 0
|
|
.IP "\fB\-mfp64\fR" 4
|
|
.IX Item "-mfp64"
|
|
.PD
|
|
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these
|
|
flags force a certain group of registers to be treated as 64 bits wide at
|
|
all times. \fB\-mgp64\fR controls the size of general-purpose registers
|
|
and \fB\-mfp64\fR controls the size of floating-point registers.
|
|
.IP "\fB\-mfpxx\fR" 4
|
|
.IX Item "-mfpxx"
|
|
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but using
|
|
this flag in combination with \fB\-mabi=32\fR enables an \s-1ABI\s0 variant
|
|
which will operate correctly with floating-point registers which are
|
|
32 or 64 bits wide.
|
|
.IP "\fB\-modd\-spreg\fR" 4
|
|
.IX Item "-modd-spreg"
|
|
.PD 0
|
|
.IP "\fB\-mno\-odd\-spreg\fR" 4
|
|
.IX Item "-mno-odd-spreg"
|
|
.PD
|
|
Enable use of floating-point operations on odd-numbered single-precision
|
|
registers when supported by the \s-1ISA.\s0 \fB\-mfpxx\fR implies
|
|
\&\fB\-mno\-odd\-spreg\fR, otherwise the default is \fB\-modd\-spreg\fR.
|
|
.IP "\fB\-mips16\fR" 4
|
|
.IX Item "-mips16"
|
|
.PD 0
|
|
.IP "\fB\-no\-mips16\fR" 4
|
|
.IX Item "-no-mips16"
|
|
.PD
|
|
Generate code for the \s-1MIPS 16\s0 processor. This is equivalent to putting
|
|
\&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR
|
|
turns off this option.
|
|
.IP "\fB\-mmips16e2\fR" 4
|
|
.IX Item "-mmips16e2"
|
|
.PD 0
|
|
.IP "\fB\-mno\-mips16e2\fR" 4
|
|
.IX Item "-mno-mips16e2"
|
|
.PD
|
|
Enable the use of MIPS16e2 instructions in \s-1MIPS16\s0 mode. This is equivalent
|
|
to putting \f(CW\*(C`.module mips16e2\*(C'\fR at the start of the assembly file.
|
|
\&\fB\-mno\-mips16e2\fR turns off this option.
|
|
.IP "\fB\-mmicromips\fR" 4
|
|
.IX Item "-mmicromips"
|
|
.PD 0
|
|
.IP "\fB\-mno\-micromips\fR" 4
|
|
.IX Item "-mno-micromips"
|
|
.PD
|
|
Generate code for the microMIPS processor. This is equivalent to putting
|
|
\&\f(CW\*(C`.module micromips\*(C'\fR at the start of the assembly file.
|
|
\&\fB\-mno\-micromips\fR turns off this option. This is equivalent to putting
|
|
\&\f(CW\*(C`.module nomicromips\*(C'\fR at the start of the assembly file.
|
|
.IP "\fB\-msmartmips\fR" 4
|
|
.IX Item "-msmartmips"
|
|
.PD 0
|
|
.IP "\fB\-mno\-smartmips\fR" 4
|
|
.IX Item "-mno-smartmips"
|
|
.PD
|
|
Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is
|
|
equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the assembly
|
|
file. \fB\-mno\-smartmips\fR turns off this option.
|
|
.IP "\fB\-mips3d\fR" 4
|
|
.IX Item "-mips3d"
|
|
.PD 0
|
|
.IP "\fB\-no\-mips3d\fR" 4
|
|
.IX Item "-no-mips3d"
|
|
.PD
|
|
Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
|
|
\&\fB\-no\-mips3d\fR turns off this option.
|
|
.IP "\fB\-mdmx\fR" 4
|
|
.IX Item "-mdmx"
|
|
.PD 0
|
|
.IP "\fB\-no\-mdmx\fR" 4
|
|
.IX Item "-no-mdmx"
|
|
.PD
|
|
Generate code for the \s-1MDMX\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MDMX\s0 instructions.
|
|
\&\fB\-no\-mdmx\fR turns off this option.
|
|
.IP "\fB\-mdsp\fR" 4
|
|
.IX Item "-mdsp"
|
|
.PD 0
|
|
.IP "\fB\-mno\-dsp\fR" 4
|
|
.IX Item "-mno-dsp"
|
|
.PD
|
|
Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension.
|
|
This tells the assembler to accept \s-1DSP\s0 Release 1 instructions.
|
|
\&\fB\-mno\-dsp\fR turns off this option.
|
|
.IP "\fB\-mdspr2\fR" 4
|
|
.IX Item "-mdspr2"
|
|
.PD 0
|
|
.IP "\fB\-mno\-dspr2\fR" 4
|
|
.IX Item "-mno-dspr2"
|
|
.PD
|
|
Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension.
|
|
This option implies \fB\-mdsp\fR.
|
|
This tells the assembler to accept \s-1DSP\s0 Release 2 instructions.
|
|
\&\fB\-mno\-dspr2\fR turns off this option.
|
|
.IP "\fB\-mdspr3\fR" 4
|
|
.IX Item "-mdspr3"
|
|
.PD 0
|
|
.IP "\fB\-mno\-dspr3\fR" 4
|
|
.IX Item "-mno-dspr3"
|
|
.PD
|
|
Generate code for the \s-1DSP\s0 Release 3 Application Specific Extension.
|
|
This option implies \fB\-mdsp\fR and \fB\-mdspr2\fR.
|
|
This tells the assembler to accept \s-1DSP\s0 Release 3 instructions.
|
|
\&\fB\-mno\-dspr3\fR turns off this option.
|
|
.IP "\fB\-mmsa\fR" 4
|
|
.IX Item "-mmsa"
|
|
.PD 0
|
|
.IP "\fB\-mno\-msa\fR" 4
|
|
.IX Item "-mno-msa"
|
|
.PD
|
|
Generate code for the \s-1MIPS SIMD\s0 Architecture Extension.
|
|
This tells the assembler to accept \s-1MSA\s0 instructions.
|
|
\&\fB\-mno\-msa\fR turns off this option.
|
|
.IP "\fB\-mxpa\fR" 4
|
|
.IX Item "-mxpa"
|
|
.PD 0
|
|
.IP "\fB\-mno\-xpa\fR" 4
|
|
.IX Item "-mno-xpa"
|
|
.PD
|
|
Generate code for the \s-1MIPS\s0 eXtended Physical Address (\s-1XPA\s0) Extension.
|
|
This tells the assembler to accept \s-1XPA\s0 instructions.
|
|
\&\fB\-mno\-xpa\fR turns off this option.
|
|
.IP "\fB\-mmt\fR" 4
|
|
.IX Item "-mmt"
|
|
.PD 0
|
|
.IP "\fB\-mno\-mt\fR" 4
|
|
.IX Item "-mno-mt"
|
|
.PD
|
|
Generate code for the \s-1MT\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MT\s0 instructions.
|
|
\&\fB\-mno\-mt\fR turns off this option.
|
|
.IP "\fB\-mmcu\fR" 4
|
|
.IX Item "-mmcu"
|
|
.PD 0
|
|
.IP "\fB\-mno\-mcu\fR" 4
|
|
.IX Item "-mno-mcu"
|
|
.PD
|
|
Generate code for the \s-1MCU\s0 Application Specific Extension.
|
|
This tells the assembler to accept \s-1MCU\s0 instructions.
|
|
\&\fB\-mno\-mcu\fR turns off this option.
|
|
.IP "\fB\-mcrc\fR" 4
|
|
.IX Item "-mcrc"
|
|
.PD 0
|
|
.IP "\fB\-mno\-crc\fR" 4
|
|
.IX Item "-mno-crc"
|
|
.PD
|
|
Generate code for the \s-1MIPS\s0 cyclic redundancy check (\s-1CRC\s0) Application
|
|
Specific Extension. This tells the assembler to accept \s-1CRC\s0 instructions.
|
|
\&\fB\-mno\-crc\fR turns off this option.
|
|
.IP "\fB\-mginv\fR" 4
|
|
.IX Item "-mginv"
|
|
.PD 0
|
|
.IP "\fB\-mno\-ginv\fR" 4
|
|
.IX Item "-mno-ginv"
|
|
.PD
|
|
Generate code for the Global INValidate (\s-1GINV\s0) Application Specific
|
|
Extension. This tells the assembler to accept \s-1GINV\s0 instructions.
|
|
\&\fB\-mno\-ginv\fR turns off this option.
|
|
.IP "\fB\-minsn32\fR" 4
|
|
.IX Item "-minsn32"
|
|
.PD 0
|
|
.IP "\fB\-mno\-insn32\fR" 4
|
|
.IX Item "-mno-insn32"
|
|
.PD
|
|
Only use 32\-bit instruction encodings when generating code for the
|
|
microMIPS processor. This option inhibits the use of any 16\-bit
|
|
instructions. This is equivalent to putting \f(CW\*(C`.set insn32\*(C'\fR at
|
|
the start of the assembly file. \fB\-mno\-insn32\fR turns off this
|
|
option. This is equivalent to putting \f(CW\*(C`.set noinsn32\*(C'\fR at the
|
|
start of the assembly file. By default \fB\-mno\-insn32\fR is
|
|
selected, allowing all instructions to be used.
|
|
.IP "\fB\-\-construct\-floats\fR" 4
|
|
.IX Item "--construct-floats"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-construct\-floats\fR" 4
|
|
.IX Item "--no-construct-floats"
|
|
.PD
|
|
The \fB\-\-no\-construct\-floats\fR option disables the construction of
|
|
double width floating point constants by loading the two halves of the
|
|
value into the two single width floating point registers that make up
|
|
the double width register. By default \fB\-\-construct\-floats\fR is
|
|
selected, allowing construction of these floating point constants.
|
|
.IP "\fB\-\-relax\-branch\fR" 4
|
|
.IX Item "--relax-branch"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-relax\-branch\fR" 4
|
|
.IX Item "--no-relax-branch"
|
|
.PD
|
|
The \fB\-\-relax\-branch\fR option enables the relaxation of out-of-range
|
|
branches. By default \fB\-\-no\-relax\-branch\fR is selected, causing any
|
|
out-of-range branches to produce an error.
|
|
.IP "\fB\-mignore\-branch\-isa\fR" 4
|
|
.IX Item "-mignore-branch-isa"
|
|
.PD 0
|
|
.IP "\fB\-mno\-ignore\-branch\-isa\fR" 4
|
|
.IX Item "-mno-ignore-branch-isa"
|
|
.PD
|
|
Ignore branch checks for invalid transitions between \s-1ISA\s0 modes. The
|
|
semantics of branches does not provide for an \s-1ISA\s0 mode switch, so in
|
|
most cases the \s-1ISA\s0 mode a branch has been encoded for has to be the
|
|
same as the \s-1ISA\s0 mode of the branch's target label. Therefore \s-1GAS\s0 has
|
|
checks implemented that verify in branch assembly that the two \s-1ISA\s0
|
|
modes match. \fB\-mignore\-branch\-isa\fR disables these checks. By
|
|
default \fB\-mno\-ignore\-branch\-isa\fR is selected, causing any invalid
|
|
branch requiring a transition between \s-1ISA\s0 modes to produce an error.
|
|
.IP "\fB\-mnan=\fR\fIencoding\fR" 4
|
|
.IX Item "-mnan=encoding"
|
|
Select between the \s-1IEEE 754\-2008\s0 (\fB\-mnan=2008\fR) or the legacy
|
|
(\fB\-mnan=legacy\fR) NaN encoding format. The latter is the default.
|
|
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
|
|
.IX Item "--emulation=name"
|
|
This option was formerly used to switch between \s-1ELF\s0 and \s-1ECOFF\s0 output
|
|
on targets like \s-1IRIX 5\s0 that supported both. \s-1MIPS ECOFF\s0 support was
|
|
removed in \s-1GAS 2.24,\s0 so the option now serves little purpose.
|
|
It is retained for backwards compatibility.
|
|
.Sp
|
|
The available configuration names are: \fBmipself\fR, \fBmipslelf\fR and
|
|
\&\fBmipsbelf\fR. Choosing \fBmipself\fR now has no effect, since the output
|
|
is always \s-1ELF.\s0 \fBmipslelf\fR and \fBmipsbelf\fR select little\- and
|
|
big-endian output respectively, but \fB\-EL\fR and \fB\-EB\fR are now the
|
|
preferred options instead.
|
|
.IP "\fB\-nocpp\fR" 4
|
|
.IX Item "-nocpp"
|
|
\&\fBas\fR ignores this option. It is accepted for compatibility with
|
|
the native tools.
|
|
.IP "\fB\-\-trap\fR" 4
|
|
.IX Item "--trap"
|
|
.PD 0
|
|
.IP "\fB\-\-no\-trap\fR" 4
|
|
.IX Item "--no-trap"
|
|
.IP "\fB\-\-break\fR" 4
|
|
.IX Item "--break"
|
|
.IP "\fB\-\-no\-break\fR" 4
|
|
.IX Item "--no-break"
|
|
.PD
|
|
Control how to deal with multiplication overflow and division by zero.
|
|
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
|
|
(and only work for Instruction Set Architecture level 2 and higher);
|
|
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
|
|
break exception.
|
|
.IP "\fB\-n\fR" 4
|
|
.IX Item "-n"
|
|
When this option is used, \fBas\fR will issue a warning every
|
|
time it generates a nop instruction from a macro.
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
Meta processor.
|
|
.ie n .IP """\-mcpu=metac11""" 4
|
|
.el .IP "\f(CW\-mcpu=metac11\fR" 4
|
|
.IX Item "-mcpu=metac11"
|
|
Generate code for Meta 1.1.
|
|
.ie n .IP """\-mcpu=metac12""" 4
|
|
.el .IP "\f(CW\-mcpu=metac12\fR" 4
|
|
.IX Item "-mcpu=metac12"
|
|
Generate code for Meta 1.2.
|
|
.ie n .IP """\-mcpu=metac21""" 4
|
|
.el .IP "\f(CW\-mcpu=metac21\fR" 4
|
|
.IX Item "-mcpu=metac21"
|
|
Generate code for Meta 2.1.
|
|
.ie n .IP """\-mfpu=metac21""" 4
|
|
.el .IP "\f(CW\-mfpu=metac21\fR" 4
|
|
.IX Item "-mfpu=metac21"
|
|
Allow code to use \s-1FPU\s0 hardware of Meta 2.1.
|
|
.PP
|
|
See the info pages for documentation of the MMIX-specific options.
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
\&\s-1NDS32\s0 processor.
|
|
.ie n .IP """\-O1""" 4
|
|
.el .IP "\f(CW\-O1\fR" 4
|
|
.IX Item "-O1"
|
|
Optimize for performance.
|
|
.ie n .IP """\-Os""" 4
|
|
.el .IP "\f(CW\-Os\fR" 4
|
|
.IX Item "-Os"
|
|
Optimize for space.
|
|
.ie n .IP """\-EL""" 4
|
|
.el .IP "\f(CW\-EL\fR" 4
|
|
.IX Item "-EL"
|
|
Produce little endian data output.
|
|
.ie n .IP """\-EB""" 4
|
|
.el .IP "\f(CW\-EB\fR" 4
|
|
.IX Item "-EB"
|
|
Produce little endian data output.
|
|
.ie n .IP """\-mpic""" 4
|
|
.el .IP "\f(CW\-mpic\fR" 4
|
|
.IX Item "-mpic"
|
|
Generate \s-1PIC.\s0
|
|
.ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4
|
|
.el .IP "\f(CW\-mno\-fp\-as\-gp\-relax\fR" 4
|
|
.IX Item "-mno-fp-as-gp-relax"
|
|
Suppress fp-as-gp relaxation for this file.
|
|
.ie n .IP """\-mb2bb\-relax""" 4
|
|
.el .IP "\f(CW\-mb2bb\-relax\fR" 4
|
|
.IX Item "-mb2bb-relax"
|
|
Back-to-back branch optimization.
|
|
.ie n .IP """\-mno\-all\-relax""" 4
|
|
.el .IP "\f(CW\-mno\-all\-relax\fR" 4
|
|
.IX Item "-mno-all-relax"
|
|
Suppress all relaxation for this file.
|
|
.ie n .IP """\-march=<arch name>""" 4
|
|
.el .IP "\f(CW\-march=<arch name>\fR" 4
|
|
.IX Item "-march=<arch name>"
|
|
Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
|
|
v3s, v2, v2j, v2f, v2s.
|
|
.ie n .IP """\-mbaseline=<baseline>""" 4
|
|
.el .IP "\f(CW\-mbaseline=<baseline>\fR" 4
|
|
.IX Item "-mbaseline=<baseline>"
|
|
Assemble for baseline <baseline> which could be v2, v3, v3m.
|
|
.ie n .IP """\-mfpu\-freg=\fIFREG\fP""" 4
|
|
.el .IP "\f(CW\-mfpu\-freg=\f(CIFREG\f(CW\fR" 4
|
|
.IX Item "-mfpu-freg=FREG"
|
|
Specify a \s-1FPU\s0 configuration.
|
|
.RS 4
|
|
.ie n .IP """0 8 SP / 4 DP registers""" 4
|
|
.el .IP "\f(CW0 8 SP / 4 DP registers\fR" 4
|
|
.IX Item "0 8 SP / 4 DP registers"
|
|
.PD 0
|
|
.ie n .IP """1 16 SP / 8 DP registers""" 4
|
|
.el .IP "\f(CW1 16 SP / 8 DP registers\fR" 4
|
|
.IX Item "1 16 SP / 8 DP registers"
|
|
.ie n .IP """2 32 SP / 16 DP registers""" 4
|
|
.el .IP "\f(CW2 32 SP / 16 DP registers\fR" 4
|
|
.IX Item "2 32 SP / 16 DP registers"
|
|
.ie n .IP """3 32 SP / 32 DP registers""" 4
|
|
.el .IP "\f(CW3 32 SP / 32 DP registers\fR" 4
|
|
.IX Item "3 32 SP / 32 DP registers"
|
|
.RE
|
|
.RS 4
|
|
.RE
|
|
.ie n .IP """\-mabi=\fIabi\fP""" 4
|
|
.el .IP "\f(CW\-mabi=\f(CIabi\f(CW\fR" 4
|
|
.IX Item "-mabi=abi"
|
|
.PD
|
|
Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
|
|
.ie n .IP """\-m[no\-]mac""" 4
|
|
.el .IP "\f(CW\-m[no\-]mac\fR" 4
|
|
.IX Item "-m[no-]mac"
|
|
Enable/Disable Multiply instructions support.
|
|
.ie n .IP """\-m[no\-]div""" 4
|
|
.el .IP "\f(CW\-m[no\-]div\fR" 4
|
|
.IX Item "-m[no-]div"
|
|
Enable/Disable Divide instructions support.
|
|
.ie n .IP """\-m[no\-]16bit\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]16bit\-ext\fR" 4
|
|
.IX Item "-m[no-]16bit-ext"
|
|
Enable/Disable 16\-bit extension
|
|
.ie n .IP """\-m[no\-]dx\-regs""" 4
|
|
.el .IP "\f(CW\-m[no\-]dx\-regs\fR" 4
|
|
.IX Item "-m[no-]dx-regs"
|
|
Enable/Disable d0/d1 registers
|
|
.ie n .IP """\-m[no\-]perf\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]perf\-ext\fR" 4
|
|
.IX Item "-m[no-]perf-ext"
|
|
Enable/Disable Performance extension
|
|
.ie n .IP """\-m[no\-]perf2\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]perf2\-ext\fR" 4
|
|
.IX Item "-m[no-]perf2-ext"
|
|
Enable/Disable Performance extension 2
|
|
.ie n .IP """\-m[no\-]string\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]string\-ext\fR" 4
|
|
.IX Item "-m[no-]string-ext"
|
|
Enable/Disable String extension
|
|
.ie n .IP """\-m[no\-]reduced\-regs""" 4
|
|
.el .IP "\f(CW\-m[no\-]reduced\-regs\fR" 4
|
|
.IX Item "-m[no-]reduced-regs"
|
|
Enable/Disable Reduced Register configuration (\s-1GPR16\s0) option
|
|
.ie n .IP """\-m[no\-]audio\-isa\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]audio\-isa\-ext\fR" 4
|
|
.IX Item "-m[no-]audio-isa-ext"
|
|
Enable/Disable \s-1AUDIO ISA\s0 extension
|
|
.ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]fpu\-sp\-ext\fR" 4
|
|
.IX Item "-m[no-]fpu-sp-ext"
|
|
Enable/Disable \s-1FPU SP\s0 extension
|
|
.ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4
|
|
.el .IP "\f(CW\-m[no\-]fpu\-dp\-ext\fR" 4
|
|
.IX Item "-m[no-]fpu-dp-ext"
|
|
Enable/Disable \s-1FPU DP\s0 extension
|
|
.ie n .IP """\-m[no\-]fpu\-fma""" 4
|
|
.el .IP "\f(CW\-m[no\-]fpu\-fma\fR" 4
|
|
.IX Item "-m[no-]fpu-fma"
|
|
Enable/Disable \s-1FPU\s0 fused-multiply-add instructions
|
|
.ie n .IP """\-mall\-ext""" 4
|
|
.el .IP "\f(CW\-mall\-ext\fR" 4
|
|
.IX Item "-mall-ext"
|
|
Turn on all extensions and instructions support
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
PowerPC processor.
|
|
.IP "\fB\-a32\fR" 4
|
|
.IX Item "-a32"
|
|
Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0
|
|
.IP "\fB\-a64\fR" 4
|
|
.IX Item "-a64"
|
|
Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0
|
|
.IP "\fB\-K \s-1PIC\s0\fR" 4
|
|
.IX Item "-K PIC"
|
|
Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags.
|
|
.IP "\fB\-mpwrx | \-mpwr2\fR" 4
|
|
.IX Item "-mpwrx | -mpwr2"
|
|
Generate code for \s-1POWER/2\s0 (\s-1RIOS2\s0).
|
|
.IP "\fB\-mpwr\fR" 4
|
|
.IX Item "-mpwr"
|
|
Generate code for \s-1POWER\s0 (\s-1RIOS1\s0)
|
|
.IP "\fB\-m601\fR" 4
|
|
.IX Item "-m601"
|
|
Generate code for PowerPC 601.
|
|
.IP "\fB\-mppc, \-mppc32, \-m603, \-m604\fR" 4
|
|
.IX Item "-mppc, -mppc32, -m603, -m604"
|
|
Generate code for PowerPC 603/604.
|
|
.IP "\fB\-m403, \-m405\fR" 4
|
|
.IX Item "-m403, -m405"
|
|
Generate code for PowerPC 403/405.
|
|
.IP "\fB\-m440\fR" 4
|
|
.IX Item "-m440"
|
|
Generate code for PowerPC 440. BookE and some 405 instructions.
|
|
.IP "\fB\-m464\fR" 4
|
|
.IX Item "-m464"
|
|
Generate code for PowerPC 464.
|
|
.IP "\fB\-m476\fR" 4
|
|
.IX Item "-m476"
|
|
Generate code for PowerPC 476.
|
|
.IP "\fB\-m7400, \-m7410, \-m7450, \-m7455\fR" 4
|
|
.IX Item "-m7400, -m7410, -m7450, -m7455"
|
|
Generate code for PowerPC 7400/7410/7450/7455.
|
|
.IP "\fB\-m750cl\fR" 4
|
|
.IX Item "-m750cl"
|
|
Generate code for PowerPC 750CL.
|
|
.IP "\fB\-m821, \-m850, \-m860\fR" 4
|
|
.IX Item "-m821, -m850, -m860"
|
|
Generate code for PowerPC 821/850/860.
|
|
.IP "\fB\-mppc64, \-m620\fR" 4
|
|
.IX Item "-mppc64, -m620"
|
|
Generate code for PowerPC 620/625/630.
|
|
.IP "\fB\-me500, \-me500x2\fR" 4
|
|
.IX Item "-me500, -me500x2"
|
|
Generate code for Motorola e500 core complex.
|
|
.IP "\fB\-me500mc\fR" 4
|
|
.IX Item "-me500mc"
|
|
Generate code for Freescale e500mc core complex.
|
|
.IP "\fB\-me500mc64\fR" 4
|
|
.IX Item "-me500mc64"
|
|
Generate code for Freescale e500mc64 core complex.
|
|
.IP "\fB\-me5500\fR" 4
|
|
.IX Item "-me5500"
|
|
Generate code for Freescale e5500 core complex.
|
|
.IP "\fB\-me6500\fR" 4
|
|
.IX Item "-me6500"
|
|
Generate code for Freescale e6500 core complex.
|
|
.IP "\fB\-mspe\fR" 4
|
|
.IX Item "-mspe"
|
|
Generate code for Motorola \s-1SPE\s0 instructions.
|
|
.IP "\fB\-mspe2\fR" 4
|
|
.IX Item "-mspe2"
|
|
Generate code for Freescale \s-1SPE2\s0 instructions.
|
|
.IP "\fB\-mtitan\fR" 4
|
|
.IX Item "-mtitan"
|
|
Generate code for AppliedMicro Titan core complex.
|
|
.IP "\fB\-mppc64bridge\fR" 4
|
|
.IX Item "-mppc64bridge"
|
|
Generate code for PowerPC 64, including bridge insns.
|
|
.IP "\fB\-mbooke\fR" 4
|
|
.IX Item "-mbooke"
|
|
Generate code for 32\-bit BookE.
|
|
.IP "\fB\-ma2\fR" 4
|
|
.IX Item "-ma2"
|
|
Generate code for A2 architecture.
|
|
.IP "\fB\-me300\fR" 4
|
|
.IX Item "-me300"
|
|
Generate code for PowerPC e300 family.
|
|
.IP "\fB\-maltivec\fR" 4
|
|
.IX Item "-maltivec"
|
|
Generate code for processors with AltiVec instructions.
|
|
.IP "\fB\-mvle\fR" 4
|
|
.IX Item "-mvle"
|
|
Generate code for Freescale PowerPC \s-1VLE\s0 instructions.
|
|
.IP "\fB\-mvsx\fR" 4
|
|
.IX Item "-mvsx"
|
|
Generate code for processors with Vector-Scalar (\s-1VSX\s0) instructions.
|
|
.IP "\fB\-mhtm\fR" 4
|
|
.IX Item "-mhtm"
|
|
Generate code for processors with Hardware Transactional Memory instructions.
|
|
.IP "\fB\-mpower4, \-mpwr4\fR" 4
|
|
.IX Item "-mpower4, -mpwr4"
|
|
Generate code for Power4 architecture.
|
|
.IP "\fB\-mpower5, \-mpwr5, \-mpwr5x\fR" 4
|
|
.IX Item "-mpower5, -mpwr5, -mpwr5x"
|
|
Generate code for Power5 architecture.
|
|
.IP "\fB\-mpower6, \-mpwr6\fR" 4
|
|
.IX Item "-mpower6, -mpwr6"
|
|
Generate code for Power6 architecture.
|
|
.IP "\fB\-mpower7, \-mpwr7\fR" 4
|
|
.IX Item "-mpower7, -mpwr7"
|
|
Generate code for Power7 architecture.
|
|
.IP "\fB\-mpower8, \-mpwr8\fR" 4
|
|
.IX Item "-mpower8, -mpwr8"
|
|
Generate code for Power8 architecture.
|
|
.IP "\fB\-mpower9, \-mpwr9\fR" 4
|
|
.IX Item "-mpower9, -mpwr9"
|
|
Generate code for Power9 architecture.
|
|
.IP "\fB\-mcell\fR" 4
|
|
.IX Item "-mcell"
|
|
.PD 0
|
|
.IP "\fB\-mcell\fR" 4
|
|
.IX Item "-mcell"
|
|
.PD
|
|
Generate code for Cell Broadband Engine architecture.
|
|
.IP "\fB\-mcom\fR" 4
|
|
.IX Item "-mcom"
|
|
Generate code Power/PowerPC common instructions.
|
|
.IP "\fB\-many\fR" 4
|
|
.IX Item "-many"
|
|
Generate code for any architecture (\s-1PWR/PWRX/PPC\s0).
|
|
.IP "\fB\-mregnames\fR" 4
|
|
.IX Item "-mregnames"
|
|
Allow symbolic names for registers.
|
|
.IP "\fB\-mno\-regnames\fR" 4
|
|
.IX Item "-mno-regnames"
|
|
Do not allow symbolic names for registers.
|
|
.IP "\fB\-mrelocatable\fR" 4
|
|
.IX Item "-mrelocatable"
|
|
Support for \s-1GCC\s0's \-mrelocatable option.
|
|
.IP "\fB\-mrelocatable\-lib\fR" 4
|
|
.IX Item "-mrelocatable-lib"
|
|
Support for \s-1GCC\s0's \-mrelocatable\-lib option.
|
|
.IP "\fB\-memb\fR" 4
|
|
.IX Item "-memb"
|
|
Set \s-1PPC_EMB\s0 bit in \s-1ELF\s0 flags.
|
|
.IP "\fB\-mlittle, \-mlittle\-endian, \-le\fR" 4
|
|
.IX Item "-mlittle, -mlittle-endian, -le"
|
|
Generate code for a little endian machine.
|
|
.IP "\fB\-mbig, \-mbig\-endian, \-be\fR" 4
|
|
.IX Item "-mbig, -mbig-endian, -be"
|
|
Generate code for a big endian machine.
|
|
.IP "\fB\-msolaris\fR" 4
|
|
.IX Item "-msolaris"
|
|
Generate code for Solaris.
|
|
.IP "\fB\-mno\-solaris\fR" 4
|
|
.IX Item "-mno-solaris"
|
|
Do not generate code for Solaris.
|
|
.IP "\fB\-nops=\fR\fIcount\fR" 4
|
|
.IX Item "-nops=count"
|
|
If an alignment directive inserts more than \fIcount\fR nops, put a
|
|
branch at the beginning to skip execution of the nops.
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
RISC-V processor.
|
|
.IP "\fB\-fpic\fR" 4
|
|
.IX Item "-fpic"
|
|
.PD 0
|
|
.IP "\fB\-fPIC\fR" 4
|
|
.IX Item "-fPIC"
|
|
.PD
|
|
Generate position-independent code
|
|
.IP "\fB\-fno\-pic\fR" 4
|
|
.IX Item "-fno-pic"
|
|
Don't generate position-independent code (default)
|
|
.IP "\fB\-march=ISA\fR" 4
|
|
.IX Item "-march=ISA"
|
|
Select the base isa, as specified by \s-1ISA.\s0 For example \-march=rv32ima.
|
|
.IP "\fB\-mabi=ABI\fR" 4
|
|
.IX Item "-mabi=ABI"
|
|
Selects the \s-1ABI,\s0 which is either \*(L"ilp32\*(R" or \*(L"lp64\*(R", optionally followed
|
|
by \*(L"f\*(R", \*(L"d\*(R", or \*(L"q\*(R" to indicate single-precision, double-precision, or
|
|
quad-precision floating-point calling convention, or none to indicate
|
|
the soft-float calling convention. Also, \*(L"ilp32\*(R" can optionally be followed
|
|
by \*(L"e\*(R" to indicate the \s-1RVE ABI,\s0 which is always soft-float.
|
|
.IP "\fB\-mrelax\fR" 4
|
|
.IX Item "-mrelax"
|
|
Take advantage of linker relaxations to reduce the number of instructions
|
|
required to materialize symbol addresses. (default)
|
|
.IP "\fB\-mno\-relax\fR" 4
|
|
.IX Item "-mno-relax"
|
|
Don't do linker relaxations.
|
|
.PP
|
|
See the info pages for documentation of the RX-specific options.
|
|
.PP
|
|
The following options are available when as is configured for the s390
|
|
processor family.
|
|
.IP "\fB\-m31\fR" 4
|
|
.IX Item "-m31"
|
|
.PD 0
|
|
.IP "\fB\-m64\fR" 4
|
|
.IX Item "-m64"
|
|
.PD
|
|
Select the word size, either 31/32 bits or 64 bits.
|
|
.IP "\fB\-mesa\fR" 4
|
|
.IX Item "-mesa"
|
|
.PD 0
|
|
.IP "\fB\-mzarch\fR" 4
|
|
.IX Item "-mzarch"
|
|
.PD
|
|
Select the architecture mode, either the Enterprise System
|
|
Architecture (esa) or the z/Architecture mode (zarch).
|
|
.IP "\fB\-march=\fR\fIprocessor\fR" 4
|
|
.IX Item "-march=processor"
|
|
Specify which s390 processor variant is the target, \fBg5\fR (or
|
|
\&\fBarch3\fR), \fBg6\fR, \fBz900\fR (or \fBarch5\fR), \fBz990\fR (or
|
|
\&\fBarch6\fR), \fBz9\-109\fR, \fBz9\-ec\fR (or \fBarch7\fR), \fBz10\fR (or
|
|
\&\fBarch8\fR), \fBz196\fR (or \fBarch9\fR), \fBzEC12\fR (or \fBarch10\fR),
|
|
\&\fBz13\fR (or \fBarch11\fR), or \fBz14\fR (or \fBarch12\fR).
|
|
.IP "\fB\-mregnames\fR" 4
|
|
.IX Item "-mregnames"
|
|
.PD 0
|
|
.IP "\fB\-mno\-regnames\fR" 4
|
|
.IX Item "-mno-regnames"
|
|
.PD
|
|
Allow or disallow symbolic names for registers.
|
|
.IP "\fB\-mwarn\-areg\-zero\fR" 4
|
|
.IX Item "-mwarn-areg-zero"
|
|
Warn whenever the operand for a base or index register has been specified
|
|
but evaluates to zero.
|
|
.PP
|
|
The following options are available when as is configured for a
|
|
\&\s-1TMS320C6000\s0 processor.
|
|
.IP "\fB\-march=\fR\fIarch\fR" 4
|
|
.IX Item "-march=arch"
|
|
Enable (only) instructions from architecture \fIarch\fR. By default,
|
|
all instructions are permitted.
|
|
.Sp
|
|
The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR,
|
|
\&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
|
|
.IP "\fB\-mdsbt\fR" 4
|
|
.IX Item "-mdsbt"
|
|
.PD 0
|
|
.IP "\fB\-mno\-dsbt\fR" 4
|
|
.IX Item "-mno-dsbt"
|
|
.PD
|
|
The \fB\-mdsbt\fR option causes the assembler to generate the
|
|
\&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the
|
|
code is using \s-1DSBT\s0 addressing. The \fB\-mno\-dsbt\fR option, the
|
|
default, causes the tag to have a value of 0, indicating that the code
|
|
does not use \s-1DSBT\s0 addressing. The linker will emit a warning if
|
|
objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together.
|
|
.IP "\fB\-mpid=no\fR" 4
|
|
.IX Item "-mpid=no"
|
|
.PD 0
|
|
.IP "\fB\-mpid=near\fR" 4
|
|
.IX Item "-mpid=near"
|
|
.IP "\fB\-mpid=far\fR" 4
|
|
.IX Item "-mpid=far"
|
|
.PD
|
|
The \fB\-mpid=\fR option causes the assembler to generate the
|
|
\&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data
|
|
addressing used by the code. \fB\-mpid=no\fR, the default,
|
|
indicates position-dependent data addressing, \fB\-mpid=near\fR
|
|
indicates position-independent addressing with \s-1GOT\s0 accesses using near
|
|
\&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent
|
|
addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing. The linker will
|
|
emit a warning if objects built with different settings of this option
|
|
are linked together.
|
|
.IP "\fB\-mpic\fR" 4
|
|
.IX Item "-mpic"
|
|
.PD 0
|
|
.IP "\fB\-mno\-pic\fR" 4
|
|
.IX Item "-mno-pic"
|
|
.PD
|
|
The \fB\-mpic\fR option causes the assembler to generate the
|
|
\&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the
|
|
code is using position-independent code addressing, The
|
|
\&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of
|
|
0, indicating position-dependent code addressing. The linker will
|
|
emit a warning if objects of different type (position-dependent and
|
|
position-independent) are linked together.
|
|
.IP "\fB\-mbig\-endian\fR" 4
|
|
.IX Item "-mbig-endian"
|
|
.PD 0
|
|
.IP "\fB\-mlittle\-endian\fR" 4
|
|
.IX Item "-mlittle-endian"
|
|
.PD
|
|
Generate code for the specified endianness. The default is
|
|
little-endian.
|
|
.PP
|
|
The following options are available when as is configured for a TILE-Gx
|
|
processor.
|
|
.IP "\fB\-m32 | \-m64\fR" 4
|
|
.IX Item "-m32 | -m64"
|
|
Select the word size, either 32 bits or 64 bits.
|
|
.IP "\fB\-EB | \-EL\fR" 4
|
|
.IX Item "-EB | -EL"
|
|
Select the endianness, either big-endian (\-EB) or little-endian (\-EL).
|
|
.PP
|
|
The following option is available when as is configured for a Visium
|
|
processor.
|
|
.IP "\fB\-mtune=\fR\fIarch\fR" 4
|
|
.IX Item "-mtune=arch"
|
|
This option specifies the target architecture. If an attempt is made to
|
|
assemble an instruction that will not execute on the target architecture,
|
|
the assembler will issue an error message.
|
|
.Sp
|
|
The following names are recognized:
|
|
\&\f(CW\*(C`mcm24\*(C'\fR
|
|
\&\f(CW\*(C`mcm\*(C'\fR
|
|
\&\f(CW\*(C`gr5\*(C'\fR
|
|
\&\f(CW\*(C`gr6\*(C'\fR
|
|
.PP
|
|
The following options are available when as is configured for an
|
|
Xtensa processor.
|
|
.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
|
|
.IX Item "--text-section-literals | --no-text-section-literals"
|
|
Control the treatment of literal pools. The default is
|
|
\&\fB\-\-no\-text\-section\-literals\fR, which places literals in
|
|
separate sections in the output file. This allows the literal pool to be
|
|
placed in a data \s-1RAM/ROM.\s0 With \fB\-\-text\-section\-literals\fR, the
|
|
literals are interspersed in the text section in order to keep them as
|
|
close as possible to their references. This may be necessary for large
|
|
assembly files, where the literals would otherwise be out of range of the
|
|
\&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into
|
|
pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding
|
|
\&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced
|
|
via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode
|
|
\&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
|
|
.IP "\fB\-\-auto\-litpools | \-\-no\-auto\-litpools\fR" 4
|
|
.IX Item "--auto-litpools | --no-auto-litpools"
|
|
Control the treatment of literal pools. The default is
|
|
\&\fB\-\-no\-auto\-litpools\fR, which in the absence of
|
|
\&\fB\-\-text\-section\-literals\fR places literals in separate sections
|
|
in the output file. This allows the literal pool to be placed in a data
|
|
\&\s-1RAM/ROM.\s0 With \fB\-\-auto\-litpools\fR, the literals are interspersed
|
|
in the text section in order to keep them as close as possible to their
|
|
references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not
|
|
required. This may be necessary for very large functions, where single
|
|
literal pool at the beginning of the function may not be reachable by
|
|
\&\f(CW\*(C`L32R\*(C'\fR instructions at the end. These options only affect
|
|
literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals
|
|
for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
|
|
When used together with \fB\-\-text\-section\-literals\fR,
|
|
\&\fB\-\-auto\-litpools\fR takes precedence.
|
|
.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
|
|
.IX Item "--absolute-literals | --no-absolute-literals"
|
|
Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
|
|
or PC-relative addressing. If the processor includes the absolute
|
|
addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR
|
|
relocations. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR relocations
|
|
can be used.
|
|
.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
|
|
.IX Item "--target-align | --no-target-align"
|
|
Enable or disable automatic alignment to reduce branch penalties at some
|
|
expense in code size. This optimization is enabled by default. Note
|
|
that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR that
|
|
have fixed alignment requirements.
|
|
.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
|
|
.IX Item "--longcalls | --no-longcalls"
|
|
Enable or disable transformation of call instructions to allow calls
|
|
across a greater range of addresses. This option should be used when call
|
|
targets can potentially be out of range. It may degrade both code size
|
|
and performance, but the linker can generally optimize away the
|
|
unnecessary overhead when a call ends up within range. The default is
|
|
\&\fB\-\-no\-longcalls\fR.
|
|
.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
|
|
.IX Item "--transform | --no-transform"
|
|
Enable or disable all assembler transformations of Xtensa instructions,
|
|
including both relaxation and optimization. The default is
|
|
\&\fB\-\-transform\fR; \fB\-\-no\-transform\fR should only be used in the
|
|
rare cases when the instructions must be exactly as specified in the
|
|
assembly source. Using \fB\-\-no\-transform\fR causes out of range
|
|
instruction operands to be errors.
|
|
.IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
|
|
.IX Item "--rename-section oldname=newname"
|
|
Rename the \fIoldname\fR section to \fInewname\fR. This option can be used
|
|
multiple times to rename multiple sections.
|
|
.IP "\fB\-\-trampolines | \-\-no\-trampolines\fR" 4
|
|
.IX Item "--trampolines | --no-trampolines"
|
|
Enable or disable transformation of jump instructions to allow jumps
|
|
across a greater range of addresses. This option should be used when jump targets can
|
|
potentially be out of range. In the absence of such jumps this option
|
|
does not affect code size or performance. The default is
|
|
\&\fB\-\-trampolines\fR.
|
|
.PP
|
|
The following options are available when as is configured for
|
|
a Z80 family processor.
|
|
.IP "\fB\-z80\fR" 4
|
|
.IX Item "-z80"
|
|
Assemble for Z80 processor.
|
|
.IP "\fB\-r800\fR" 4
|
|
.IX Item "-r800"
|
|
Assemble for R800 processor.
|
|
.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
|
|
.IX Item "-ignore-undocumented-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Wnud\fR" 4
|
|
.IX Item "-Wnud"
|
|
.PD
|
|
Assemble undocumented Z80 instructions that also work on R800 without warning.
|
|
.IP "\fB\-ignore\-unportable\-instructions\fR" 4
|
|
.IX Item "-ignore-unportable-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Wnup\fR" 4
|
|
.IX Item "-Wnup"
|
|
.PD
|
|
Assemble all undocumented Z80 instructions without warning.
|
|
.IP "\fB\-warn\-undocumented\-instructions\fR" 4
|
|
.IX Item "-warn-undocumented-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Wud\fR" 4
|
|
.IX Item "-Wud"
|
|
.PD
|
|
Issue a warning for undocumented Z80 instructions that also work on R800.
|
|
.IP "\fB\-warn\-unportable\-instructions\fR" 4
|
|
.IX Item "-warn-unportable-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Wup\fR" 4
|
|
.IX Item "-Wup"
|
|
.PD
|
|
Issue a warning for undocumented Z80 instructions that do not work on R800.
|
|
.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
|
|
.IX Item "-forbid-undocumented-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Fud\fR" 4
|
|
.IX Item "-Fud"
|
|
.PD
|
|
Treat all undocumented instructions as errors.
|
|
.IP "\fB\-forbid\-unportable\-instructions\fR" 4
|
|
.IX Item "-forbid-unportable-instructions"
|
|
.PD 0
|
|
.IP "\fB\-Fup\fR" 4
|
|
.IX Item "-Fup"
|
|
.PD
|
|
Treat undocumented Z80 instructions that do not work on R800 as errors.
|
|
.SH "SEE ALSO"
|
|
.IX Header "SEE ALSO"
|
|
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
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.SH "COPYRIGHT"
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.IX Header "COPYRIGHT"
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Copyright (c) 1991\-2018 Free Software Foundation, Inc.
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.PP
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
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