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154 lines
3.8 KiB
ArmAsm
154 lines
3.8 KiB
ArmAsm
/* This file contains code to do profiling.
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Copyright (C) 2007-2015 Free Software Foundation, Inc.
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Contributor: Joern Rennecke <joern.rennecke@embecosm.com>
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on behalf of Synopsys Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "../asm.h"
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#include "auxreg.h"
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/* This file contains code to do profiling. */
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.weak __profile_timer_cycles
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.global __profile_timer_cycles
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.set __profile_timer_cycles, 200
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.section .bss
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.global __profil_offset
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.align 4
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.type __profil_offset, @object
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.size __profil_offset, 4
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__profil_offset:
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.zero 4
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.text
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.global __dcache_linesz
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.global __profil
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FUNC(__profil)
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.Lstop_profiling:
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sr r0,[CONTROL0]
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j_s [blink]
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.balign 4
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__profil:
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.Lprofil:
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breq_s r0,0,.Lstop_profiling
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; r0: buf r1: bufsiz r2: offset r3: scale
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bxor.f r3,r3,15; scale must be 0x8000, i.e. 1/2; generate 0.
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push_s blink
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lsr_s r2,r2,1
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mov_s r8,r0
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flag.ne 1 ; halt if wrong scale
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sub_s r0,r0,r2
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st r0,[__profil_offset]
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bl __dcache_linesz
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pop_s blink
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bbit1.d r0,0,nocache
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mov_s r0,r8
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#ifdef __ARC700__
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add_s r1,r1,31
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lsr.f lp_count,r1,5
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lpne 2f
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sr r0,[DC_FLDL]
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add_s r0,r0,32
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#else /* !__ARC700__ */
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# FIX ME: set up loop according to cache line size
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lr r12,[D_CACHE_BUILD]
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sub_s r0,r0,16
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sub_s r1,r1,1
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lsr_s r12,r12,16
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asr_s r1,r1,4
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bmsk_s r12,r12,3
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asr_s r1,r1,r12
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add.f lp_count,r1,1
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mov_s r1,16
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asl_s r1,r1,r12
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lpne 2f
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add r0,r0,r1
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sr r0,[DC_FLDL]
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#endif /* __ARC700__ */
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2: b_s .Lcounters_cleared
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nocache:
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.Lcounters_cleared:
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lr r1,[INT_VECTOR_BASE] ; disable timer0 interrupts
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sr r3,[CONTROL0]
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sr r3,[COUNT0]
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0: ld_s r0,[pcl,1f-0b+((0b-.Lprofil) & 2)] ; 1f@GOTOFF
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0: ld_s r12,[pcl,1f+4-0b+((0b-.Lprofil) & 2)] ; 1f@GOTOFF + 4
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st_s r0,[r1,24]; timer0 uses vector3
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st_s r12,[r1,24+4]; timer0 uses vector3
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;sr 10000,[LIMIT0]
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sr __profile_timer_cycles,[LIMIT0]
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mov_s r12,3 ; enable timer interrupts; count only when not halted.
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sr r12,[CONTROL0]
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lr r12,[STATUS32]
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bset_s r12,r12,1 ; allow level 1 interrupts
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flag r12
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mov_s r0,0
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j_s [blink]
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.balign 4
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1: j __profil_irq
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ENDFUNC(__profil)
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FUNC(__profil_irq)
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.balign 4 ; make final jump unaligned to avoid delay penalty
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.balign 32,0,12 ; make sure the code spans no more that two cache lines
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nop_s
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__profil_irq:
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push_s r0
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ld r0,[__profil_offset]
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push_s r1
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lsr r1,ilink1,2
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push_s r2
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ldw.as.di r2,[r0,r1]
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add1 r0,r0,r1
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ld_s r1,[sp,4]
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add_s r2,r2,1
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bbit1 r2,16,nostore
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stw.di r2,[r0]
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nostore:ld.ab r2,[sp,8]
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pop_s r0
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j.f [ilink1]
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ENDFUNC(__profil_irq)
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; could save one cycle if the counters were allocated at link time and
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; the contents of __profil_offset were pre-computed at link time, like this:
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#if 0
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; __profil_offset needs to be PROVIDEd as __profile_base-text/4
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.global __profil_offset
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.balign 4
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__profil_irq:
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push_s r0
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lsr r0,ilink1,2
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add1 r0,__profil_offset,r0
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push_s r1
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ldw.di r1,[r0]
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add_s r1,r1,1
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bbit1 r1,16,nostore
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stw.di r1,[r0]
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nostore:pop_s r1
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pop_s r0
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j [ilink1]
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#endif /* 0 */
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