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342 lines
10 KiB
ArmAsm
342 lines
10 KiB
ArmAsm
/*
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strcpy/stpcpy - copy a string returning pointer to start/end.
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Copyright (c) 2013, 2014, 2015 ARM Ltd.
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All Rights Reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the company nor the names of its contributors
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may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
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/* See strchr-stub.c */
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#else
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses, min page size 4k.
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*/
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/* To build as stpcpy, define BUILD_STPCPY before compiling this file.
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To test the page crossing code path more thoroughly, compile with
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-DSTRCPY_TEST_PAGE_CROSS - this will force all copies through the slower
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entry path. This option is not intended for production use. */
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/* Arguments and results. */
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#define dstin x0
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#define srcin x1
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/* Locals and temporaries. */
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#define src x2
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#define dst x3
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#define data1 x4
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#define data1w w4
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#define data2 x5
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#define data2w w5
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#define has_nul1 x6
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#define has_nul2 x7
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#define tmp1 x8
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#define tmp2 x9
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#define tmp3 x10
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#define tmp4 x11
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#define zeroones x12
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#define data1a x13
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#define data2a x14
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#define pos x15
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#define len x16
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#define to_align x17
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#ifdef BUILD_STPCPY
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#define STRCPY stpcpy
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#else
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#define STRCPY strcpy
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#endif
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.macro def_fn f p2align=0
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.text
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.p2align \p2align
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.global \f
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.type \f, %function
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\f:
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.endm
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word. */
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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/* AArch64 systems have a minimum page size of 4k. We can do a quick
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page size check for crossing this boundary on entry and if we
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do not, then we can short-circuit much of the entry code. We
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expect early page-crossing strings to be rare (probability of
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16/MIN_PAGE_SIZE ~= 0.4%), so the branch should be quite
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predictable, even with random strings.
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We don't bother checking for larger page sizes, the cost of setting
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up the correct page size is just not worth the extra gain from
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a small reduction in the cases taking the slow path. Note that
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we only care about whether the first fetch, which may be
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misaligned, crosses a page boundary - after that we move to aligned
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fetches for the remainder of the string. */
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#ifdef STRCPY_TEST_PAGE_CROSS
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/* Make everything that isn't Qword aligned look like a page cross. */
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#define MIN_PAGE_P2 4
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#else
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#define MIN_PAGE_P2 12
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#endif
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#define MIN_PAGE_SIZE (1 << MIN_PAGE_P2)
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def_fn STRCPY p2align=6
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/* For moderately short strings, the fastest way to do the copy is to
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calculate the length of the string in the same way as strlen, then
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essentially do a memcpy of the result. This avoids the need for
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multiple byte copies and further means that by the time we
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reach the bulk copy loop we know we can always use DWord
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accesses. We expect strcpy to rarely be called repeatedly
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with the same source string, so branch prediction is likely to
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always be difficult - we mitigate against this by preferring
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conditional select operations over branches whenever this is
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feasible. */
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and tmp2, srcin, #(MIN_PAGE_SIZE - 1)
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mov zeroones, #REP8_01
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and to_align, srcin, #15
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cmp tmp2, #(MIN_PAGE_SIZE - 16)
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neg tmp1, to_align
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/* The first fetch will straddle a (possible) page boundary iff
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srcin + 15 causes bit[MIN_PAGE_P2] to change value. A 16-byte
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aligned string will never fail the page align check, so will
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always take the fast path. */
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b.gt .Lpage_cross
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.Lpage_cross_ok:
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ldp data1, data2, [srcin]
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#ifdef __AARCH64EB__
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/* Because we expect the end to be found within 16 characters
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(profiling shows this is the most common case), it's worth
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swapping the bytes now to save having to recalculate the
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termination syndrome later. We preserve data1 and data2
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so that we can re-use the values later on. */
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rev tmp2, data1
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sub tmp1, tmp2, zeroones
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orr tmp2, tmp2, #REP8_7f
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bics has_nul1, tmp1, tmp2
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b.ne .Lfp_le8
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rev tmp4, data2
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sub tmp3, tmp4, zeroones
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orr tmp4, tmp4, #REP8_7f
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#else
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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bics has_nul1, tmp1, tmp2
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b.ne .Lfp_le8
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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#endif
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bics has_nul2, tmp3, tmp4
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b.eq .Lbulk_entry
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/* The string is short (<=16 bytes). We don't know exactly how
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short though, yet. Work out the exact length so that we can
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quickly select the optimal copy strategy. */
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.Lfp_gt8:
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rev has_nul2, has_nul2
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clz pos, has_nul2
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mov tmp2, #56
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add dst, dstin, pos, lsr #3 /* Bits to bytes. */
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sub pos, tmp2, pos
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#ifdef __AARCH64EB__
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lsr data2, data2, pos
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#else
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lsl data2, data2, pos
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#endif
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str data2, [dst, #1]
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str data1, [dstin]
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#ifdef BUILD_STPCPY
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add dstin, dst, #8
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#endif
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ret
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.Lfp_le8:
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rev has_nul1, has_nul1
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clz pos, has_nul1
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add dst, dstin, pos, lsr #3 /* Bits to bytes. */
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subs tmp2, pos, #24 /* Pos in bits. */
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b.lt .Lfp_lt4
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#ifdef __AARCH64EB__
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mov tmp2, #56
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sub pos, tmp2, pos
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lsr data2, data1, pos
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lsr data1, data1, #32
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#else
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lsr data2, data1, tmp2
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#endif
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/* 4->7 bytes to copy. */
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str data2w, [dst, #-3]
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str data1w, [dstin]
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#ifdef BUILD_STPCPY
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mov dstin, dst
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#endif
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ret
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.Lfp_lt4:
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cbz pos, .Lfp_lt2
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/* 2->3 bytes to copy. */
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#ifdef __AARCH64EB__
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lsr data1, data1, #48
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#endif
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strh data1w, [dstin]
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/* Fall-through, one byte (max) to go. */
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.Lfp_lt2:
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/* Null-terminated string. Last character must be zero! */
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strb wzr, [dst]
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#ifdef BUILD_STPCPY
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mov dstin, dst
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#endif
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ret
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.p2align 6
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/* Aligning here ensures that the entry code and main loop all lies
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within one 64-byte cache line. */
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.Lbulk_entry:
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sub to_align, to_align, #16
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stp data1, data2, [dstin]
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sub src, srcin, to_align
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sub dst, dstin, to_align
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b .Lentry_no_page_cross
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/* The inner loop deals with two Dwords at a time. This has a
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slightly higher start-up cost, but we should win quite quickly,
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especially on cores with a high number of issue slots per
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cycle, as we get much better parallelism out of the operations. */
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.Lmain_loop:
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stp data1, data2, [dst], #16
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.Lentry_no_page_cross:
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ldp data1, data2, [src], #16
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul1, tmp1, tmp2
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bics has_nul2, tmp3, tmp4
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ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
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b.eq .Lmain_loop
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/* Since we know we are copying at least 16 bytes, the fastest way
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to deal with the tail is to determine the location of the
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trailing NUL, then (re)copy the 16 bytes leading up to that. */
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cmp has_nul1, #0
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#ifdef __AARCH64EB__
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/* For big-endian, carry propagation (if the final byte in the
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string is 0x01) means we cannot use has_nul directly. The
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easiest way to get the correct byte is to byte-swap the data
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and calculate the syndrome a second time. */
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csel data1, data1, data2, ne
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rev data1, data1
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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bic has_nul1, tmp1, tmp2
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#else
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csel has_nul1, has_nul1, has_nul2, ne
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#endif
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rev has_nul1, has_nul1
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clz pos, has_nul1
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add tmp1, pos, #72
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add pos, pos, #8
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csel pos, pos, tmp1, ne
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add src, src, pos, lsr #3
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add dst, dst, pos, lsr #3
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ldp data1, data2, [src, #-32]
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stp data1, data2, [dst, #-16]
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#ifdef BUILD_STPCPY
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sub dstin, dst, #1
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#endif
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ret
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.Lpage_cross:
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bic src, srcin, #15
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/* Start by loading two words at [srcin & ~15], then forcing the
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bytes that precede srcin to 0xff. This means they never look
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like termination bytes. */
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ldp data1, data2, [src]
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lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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tst to_align, #7
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csetm tmp2, ne
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#ifdef __AARCH64EB__
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lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#else
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lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#endif
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orr data1, data1, tmp2
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orr data2a, data2, tmp2
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cmp to_align, #8
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csinv data1, data1, xzr, lt
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csel data2, data2, data2a, lt
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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bic has_nul1, tmp1, tmp2
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bics has_nul2, tmp3, tmp4
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ccmp has_nul1, #0, #0, eq /* NZCV = 0000 */
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b.eq .Lpage_cross_ok
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/* We now need to make data1 and data2 look like they've been
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loaded directly from srcin. Do a rotate on the 128-bit value. */
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lsl tmp1, to_align, #3 /* Bytes->bits. */
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neg tmp2, to_align, lsl #3
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#ifdef __AARCH64EB__
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lsl data1a, data1, tmp1
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lsr tmp4, data2, tmp2
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lsl data2, data2, tmp1
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orr tmp4, tmp4, data1a
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cmp to_align, #8
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csel data1, tmp4, data2, lt
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rev tmp2, data1
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rev tmp4, data2
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sub tmp1, tmp2, zeroones
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orr tmp2, tmp2, #REP8_7f
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sub tmp3, tmp4, zeroones
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orr tmp4, tmp4, #REP8_7f
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#else
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lsr data1a, data1, tmp1
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lsl tmp4, data2, tmp2
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lsr data2, data2, tmp1
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orr tmp4, tmp4, data1a
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cmp to_align, #8
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csel data1, tmp4, data2, lt
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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sub tmp3, data2, zeroones
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orr tmp4, data2, #REP8_7f
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#endif
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bic has_nul1, tmp1, tmp2
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cbnz has_nul1, .Lfp_le8
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bic has_nul2, tmp3, tmp4
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b .Lfp_gt8
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.size STRCPY, . - STRCPY
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#endif
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