mirror of
https://github.com/autc04/Retro68.git
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194 lines
4.0 KiB
Makefile
194 lines
4.0 KiB
Makefile
#source: icache1.s
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#ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
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#objdump: -D
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.* elf32-spu
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Disassembly of section \.text:
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00000000 <_start>:
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.* 41 00 02 03 ilhu \$3,4
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.* 60 88 00 03 iohl \$3,4096 # 1000
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.* 32 00 03 80 br 24.*
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0000000c <__icache_br_handler>:
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c: 00 00 00 00 stop
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00000010 <__icache_call_handler>:
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\.\.\.
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20: 00 04 08 00.*
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24: 31 00 02 4b brasl \$75,10 <__icache_call_handler>
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28: a0 00 00 08.*
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2c: 00 00 fc 80.*
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\.\.\.
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Disassembly of section \.data:
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.* <(\.data|_edata-0x10)>:
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.* 00 04 08 00 .*
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.* 00 04 0d 04 .*
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.* 00 04 0c 00 .*
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.* 00 08 10 00 .*
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Disassembly of section \.bss:
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.* <(__icache_tag_array|__bss_start)>:
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\.\.\.
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.* <__icache_rewrite_to>:
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\.\.\.
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.* <__icache_rewrite_from>:
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\.\.\.
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Disassembly of section \.ovl\.init:
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00000400 <__icache_fileoff>:
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.* 00 00 00 00.*
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.* 00 00 02 00.*
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\.\.\.
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Disassembly of section \.ovly1:
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00000400 <\.ovly1>:
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.* ai \$1,\$1,64 # 40
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.* lqd \$0,16\(\$1\)
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.* bi \$0
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\.\.\.
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Disassembly of section \.ovly2:
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00000800 <f1>:
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.* 40 20 00 00 nop \$0
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 1c f0 00 81 ai \$1,\$1,-64
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.* 24 00 00 81 stqd \$1,0\(\$1\)
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.* 33 00 78 80 brsl \$0,bd4 .*
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.* 33 00 7a 00 brsl \$0,be4 .*
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\.\.\.
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.* 32 00 17 80 br bf4 .*
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\.\.\.
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bd0: 00 04 0d 04.*
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bd4: 31 00 01 cb brasl \$75,c .*
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bd8: a0 00 08 10.*
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bdc: 00 00 e6 00.*
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be0: 00 04 0c 00.*
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be4: 31 00 01 cb brasl \$75,c .*
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be8: a0 00 08 14.*
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bec: 00 00 07 80.*
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bf0: 00 04 04 00.*
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bf4: 31 00 01 cb brasl \$75,c .*
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bf8: 20 00 0b 38.*
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bfc: 00 7f 0e 80.*
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Disassembly of section \.ovly3:
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00000c00 <f3>:
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\.\.\.
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.* 35 00 00 00 bi \$0
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00000d04 <f2>:
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.* 1c e0 00 81 ai \$1,\$1,-128
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.* 24 00 00 81 stqd \$1,0\(\$1\)
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\.\.\.
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.* 1c 20 00 81 ai \$1,\$1,128 # 80
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.* 35 00 00 00 bi \$0
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\.\.\.
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Disassembly of section \.ovly4:
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00001000 <f5>:
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 24 f8 00 81 stqd \$1,-512\(\$1\)
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.* 1c 80 00 81 ai \$1,\$1,-512
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.* 33 7f fe 80 brsl \$0,1000 <f5> # 1000
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\.\.\.
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.* 42 01 00 03 ila \$3,200.*
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.* 18 00 c0 81 a \$1,\$1,\$3
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.* 34 00 40 80 lqd \$0,16\(\$1\)
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.* 35 00 00 00 bi \$0
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\.\.\.
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Disassembly of section \.ovly5:
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00000400 <\.ovly5>:
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\.\.\.
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.* 42 01 00 03 ila \$3,200 .*
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.* 18 00 c0 81 a \$1,\$1,\$3
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.* 34 00 40 80 lqd \$0,16\(\$1\)
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.* 30 00 fe 80 bra 7f4 .*
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\.\.\.
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7f0: 00 04 10 00.*
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7f4: 31 00 01 cb brasl \$75,c .*
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7f8: a0 00 07 2c.*
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7fc: 00 02 fe 80.*
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Disassembly of section \.ovly6:
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00000800 <\.ovly6>:
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.* 31 01 7a 80 brasl \$0,bd4 .*
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.* 33 00 7c 00 brsl \$0,be4 .*
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\.\.\.
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.* 32 00 19 80 br bf4 .*
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\.\.\.
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bd0: 00 08 10 00.*
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bd4: 31 00 01 cb brasl \$75,c .*
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bd8: a0 00 08 00.*
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bdc: 00 03 7a 80.*
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be0: 00 08 10 00.*
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be4: 31 00 01 cb brasl \$75,c .*
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be8: a0 00 08 04.*
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bec: 00 00 83 80.*
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bf0: 00 08 04 00.*
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bf4: 31 00 01 cb brasl \$75,c .*
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bf8: 20 00 0b 28.*
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bfc: 00 7f 02 80.*
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Disassembly of section \.ovly7:
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00000c00 <\.ovly7>:
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.* 41 7f ff 83 ilhu \$3,65535 # ffff
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.* 60 f8 30 03 iohl \$3,61536 # f060
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.* 18 00 c0 84 a \$4,\$1,\$3
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.* 00 20 00 00 lnop
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.* 04 00 02 01 ori \$1,\$4,0
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.* 24 00 02 04 stqd \$4,0\(\$4\)
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.* 33 00 77 80 brsl \$0,fd4 .*
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.* 33 00 79 00 brsl \$0,fe4 .*
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.* 34 00 00 81 lqd \$1,0\(\$1\)
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\.\.\.
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.* 32 00 16 00 br ff4 .*
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\.\.\.
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fd0: 00 04 10 00.*
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fd4: 31 00 01 cb brasl \$75,c .*
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fd8: a0 00 0c 18.*
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fdc: 00 00 0a 80.*
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fe0: 00 08 10 00.*
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fe4: 31 00 01 cb brasl \$75,c .*
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fe8: a0 00 0c 1c.*
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fec: 00 00 05 80.*
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ff0: 00 08 08 00.*
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ff4: 31 00 01 cb brasl \$75,c .*
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ff8: 20 00 0f 44.*
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ffc: 00 7f 01 80.*
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Disassembly of section \.ovly8:
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00001000 <f4>:
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.* 24 00 40 80 stqd \$0,16\(\$1\)
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.* 24 f8 00 81 stqd \$1,-512\(\$1\)
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.* 1c 80 00 81 ai \$1,\$1,-512
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.* 31 02 7c 80 brasl \$0,13e4 .*
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\.\.\.
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.* 32 00 18 80 br 13f4 .*
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\.\.\.
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13e0: 00 04 0d 04.*
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13e4: 31 00 01 cb brasl \$75,c .*
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13e8: a0 00 10 0c.*
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13ec: 00 03 dc 00.*
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13f0: 00 08 0c 00.*
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13f4: 31 00 01 cb brasl \$75,c .*
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13f8: 20 00 13 30.*
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13fc: 00 7f 02 80.*
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#pass
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