mirror of
https://github.com/autc04/Retro68.git
synced 2024-12-25 09:30:58 +00:00
63196 lines
4.1 MiB
63196 lines
4.1 MiB
/* CPU data for m32c.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2010 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "sysdep.h"
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#include <stdio.h>
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#include <stdarg.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "m32c-desc.h"
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#include "m32c-opc.h"
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#include "opintl.h"
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#include "libiberty.h"
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#include "xregex.h"
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/* Attributes. */
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static const CGEN_ATTR_ENTRY bool_attr[] =
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{
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{ "#f", 0 },
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{ "#t", 1 },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
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{
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{ "base", MACH_BASE },
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{ "m16c", MACH_M16C },
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{ "m32c", MACH_M32C },
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{ "max", MACH_MAX },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
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{
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{ "m16c", ISA_M16C },
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{ "m32c", ISA_M32C },
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{ "max", ISA_MAX },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY RL_TYPE_attr[] ATTRIBUTE_UNUSED =
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{
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{ "NONE", RL_TYPE_NONE },
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{ "JUMP", RL_TYPE_JUMP },
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{ "1ADDR", RL_TYPE_1ADDR },
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{ "2ADDR", RL_TYPE_2ADDR },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "RESERVED", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "PC", &bool_attr[0], &bool_attr[0] },
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{ "PROFILE", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
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{ "RELAX", &bool_attr[0], &bool_attr[0] },
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{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "RL_TYPE", & RL_TYPE_attr[0], & RL_TYPE_attr[0] },
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{ "ALIAS", &bool_attr[0], &bool_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
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{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
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{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
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{ "RELAXED", &bool_attr[0], &bool_attr[0] },
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{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
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{ "PBB", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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/* Instruction set variants. */
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static const CGEN_ISA m32c_cgen_isa_table[] = {
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{ "m16c", 32, 32, 8, 56 },
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{ "m32c", 32, 32, 8, 80 },
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{ 0, 0, 0, 0, 0 }
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};
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/* Machine variants. */
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static const CGEN_MACH m32c_cgen_mach_table[] = {
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{ "m16c", "m16c", MACH_M16C, 0 },
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{ "m32c", "m32c", MACH_M32C, 0 },
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{ 0, 0, 0, 0 }
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
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{
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{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
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{ "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
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{ "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr =
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{
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& m32c_cgen_opval_h_gr_entries[0],
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4,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
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{
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{ "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r0h", 1, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1l", 2, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1h", 3, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
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{
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& m32c_cgen_opval_h_gr_QI_entries[0],
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4,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
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{
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{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
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{ "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
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{ "r3", 3, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
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{
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& m32c_cgen_opval_h_gr_HI_entries[0],
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4,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
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{
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{ "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r3r1", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
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{
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& m32c_cgen_opval_h_gr_SI_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
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{
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{ "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1l", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
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{
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& m32c_cgen_opval_h_gr_ext_QI_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
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{
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{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
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{
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& m32c_cgen_opval_h_gr_ext_HI_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
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{
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{ "r0l", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r0l =
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{
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& m32c_cgen_opval_h_r0l_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
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{
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{ "r0h", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r0h =
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{
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& m32c_cgen_opval_h_r0h_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
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{
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{ "r1l", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r1l =
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{
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& m32c_cgen_opval_h_r1l_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
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{
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{ "r1h", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r1h =
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{
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& m32c_cgen_opval_h_r1h_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
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{
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{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r0 =
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{
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& m32c_cgen_opval_h_r0_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
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{
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{ "r1", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r1 =
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{
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& m32c_cgen_opval_h_r1_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
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{
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{ "r2", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r2 =
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{
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& m32c_cgen_opval_h_r2_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
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{
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{ "r3", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r3 =
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{
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& m32c_cgen_opval_h_r3_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
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{
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{ "r0l", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r0h", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
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{
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& m32c_cgen_opval_h_r0l_r0h_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
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{
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{ "r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
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{
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& m32c_cgen_opval_h_r2r0_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
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{
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{ "r3r1", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
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{
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& m32c_cgen_opval_h_r3r1_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
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{
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{ "r1r2r0", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
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{
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& m32c_cgen_opval_h_r1r2r0_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
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{
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{ "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_ar =
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{
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& m32c_cgen_opval_h_ar_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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|
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
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{
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{ "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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|
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CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
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{
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& m32c_cgen_opval_h_ar_QI_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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|
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
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{
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{ "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
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};
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|
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CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
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{
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& m32c_cgen_opval_h_ar_HI_entries[0],
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2,
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0, 0, 0, 0, ""
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};
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|
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
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{
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{ "a1a0", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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|
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CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
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{
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|
& m32c_cgen_opval_h_ar_SI_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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|
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
|
|
{
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{ "a0", 0, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD m32c_cgen_opval_h_a0 =
|
|
{
|
|
& m32c_cgen_opval_h_a0_entries[0],
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1,
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0, 0, 0, 0, ""
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};
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|
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static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
|
|
{
|
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{ "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
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|
};
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|
|
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CGEN_KEYWORD m32c_cgen_opval_h_a1 =
|
|
{
|
|
& m32c_cgen_opval_h_a1_entries[0],
|
|
1,
|
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0, 0, 0, 0, ""
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|
};
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|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
|
|
{
|
|
{ "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
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|
{ "c", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "z", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "n", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "le", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "o", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ltu", 248, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nc", 248, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "leu", 249, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ne", 250, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nz", 250, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "pz", 251, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gt", 252, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "no", 253, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "lt", 254, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
|
|
{
|
|
& m32c_cgen_opval_h_cond16_entries[0],
|
|
18,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
|
|
{
|
|
{ "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "c", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "z", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "n", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "pz", 7, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "le", 8, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "o", 9, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "no", 13, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
|
|
{
|
|
& m32c_cgen_opval_h_cond16c_entries[0],
|
|
18,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
|
|
{
|
|
{ "le", 8, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "o", 9, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gt", 12, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "no", 13, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
|
|
{
|
|
& m32c_cgen_opval_h_cond16j_entries[0],
|
|
6,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
|
|
{
|
|
{ "geu", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "c", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gtu", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "eq", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "z", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "n", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ltu", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nc", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "leu", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ne", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nz", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "pz", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
|
|
{
|
|
& m32c_cgen_opval_h_cond16j_5_entries[0],
|
|
12,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
|
|
{
|
|
{ "ltu", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nc", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "leu", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "pz", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "no", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gt", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "ge", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "geu", 8, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "c", 8, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "gtu", 9, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "eq", 10, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "z", 10, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "n", 11, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "o", 12, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "le", 13, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "lt", 14, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
|
|
{
|
|
& m32c_cgen_opval_h_cond32_entries[0],
|
|
18,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
|
|
{
|
|
{ "dct0", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dct1", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "flg", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "svf", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "drc0", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "drc1", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dmd0", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dmd1", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
|
|
{
|
|
& m32c_cgen_opval_h_cr1_32_entries[0],
|
|
8,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
|
|
{
|
|
{ "intb", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "sb", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "fb", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "svp", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "vct", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "isp", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
|
|
{
|
|
& m32c_cgen_opval_h_cr2_32_entries[0],
|
|
7,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
|
|
{
|
|
{ "dma0", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dma1", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dra0", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dra1", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dsa0", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "dsa1", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
|
|
{
|
|
& m32c_cgen_opval_h_cr3_32_entries[0],
|
|
6,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
|
|
{
|
|
{ "intbl", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "intbh", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "flg", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "isp", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "sp", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "sb", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "fb", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
|
|
{
|
|
& m32c_cgen_opval_h_cr_16_entries[0],
|
|
7,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
|
|
{
|
|
{ "c", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "d", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "z", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "s", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "b", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "o", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "i", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "u", 7, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_flags =
|
|
{
|
|
& m32c_cgen_opval_h_flags_entries[0],
|
|
8,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
|
|
{
|
|
{ "1", 0, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "2", 1, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "3", 2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "4", 3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "5", 4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "6", 5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "7", 6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "8", 7, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-1", -8, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-2", -7, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-3", -6, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-4", -5, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-5", -4, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-6", -3, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-7", -2, {0, {{{0, 0}}}}, 0, 0 },
|
|
{ "-8", -1, {0, {{{0, 0}}}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD m32c_cgen_opval_h_shimm =
|
|
{
|
|
& m32c_cgen_opval_h_shimm_entries[0],
|
|
16,
|
|
0, 0, 0, 0, ""
|
|
};
|
|
|
|
|
|
/* The hardware table. */
|
|
|
|
#define A(a) (1 << CGEN_HW_##a)
|
|
|
|
const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
|
|
{
|
|
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
|
|
};
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|
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|
#undef A
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/* The instruction field table. */
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|
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#define A(a) (1 << CGEN_IFLD_##a)
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|
|
const CGEN_IFLD m32c_cgen_ifld_table[] =
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|
{
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|
{ M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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|
{ M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
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{ M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
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{ M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_U20, "f-dsp-40-u20", 32, 32, 8, 20, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_U20, "f-dsp-48-u20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
|
|
};
|
|
|
|
#undef A
|
|
|
|
|
|
|
|
/* multi ifield declarations */
|
|
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U20_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
|
|
|
|
|
|
/* multi ifield definitions */
|
|
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U20_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
|
|
{
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
|
|
{ 0, { (const PTR) 0 } }
|
|
};
|
|
|
|
/* The operand table. */
|
|
|
|
#define A(a) (1 << CGEN_OPERAND_##a)
|
|
#define OPERAND(op) M32C_OPERAND_##op
|
|
|
|
const CGEN_OPERAND m32c_cgen_operand_table[] =
|
|
{
|
|
/* pc: program counter */
|
|
{ "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src16RnQI: general register QI view */
|
|
{ "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src16RnHI: general register QH view */
|
|
{ "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnUnprefixedQI: general register QI view */
|
|
{ "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnUnprefixedHI: general register HI view */
|
|
{ "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnUnprefixedSI: general register SI view */
|
|
{ "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnPrefixedQI: general register QI view */
|
|
{ "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnPrefixedHI: general register HI view */
|
|
{ "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32RnPrefixedSI: general register SI view */
|
|
{ "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src16An: address register */
|
|
{ "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src16AnQI: address register QI view */
|
|
{ "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src16AnHI: address register HI view */
|
|
{ "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnUnprefixed: address register */
|
|
{ "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnUnprefixedQI: address register QI view */
|
|
{ "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnUnprefixedHI: address register HI view */
|
|
{ "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnUnprefixedSI: address register SI view */
|
|
{ "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnPrefixed: address register */
|
|
{ "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnPrefixedQI: address register QI view */
|
|
{ "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnPrefixedHI: address register HI view */
|
|
{ "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Src32AnPrefixedSI: address register SI view */
|
|
{ "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16RnQI: general register QI view */
|
|
{ "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16RnHI: general register HI view */
|
|
{ "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16RnSI: general register SI view */
|
|
{ "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
|
|
{ "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32R0QI-S: general register QI view */
|
|
{ "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32R0HI-S: general register HI view */
|
|
{ "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnUnprefixedQI: general register QI view */
|
|
{ "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnUnprefixedHI: general register HI view */
|
|
{ "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnUnprefixedSI: general register SI view */
|
|
{ "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnExtUnprefixedQI: general register QI view */
|
|
{ "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnExtUnprefixedHI: general register HI view */
|
|
{ "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnPrefixedQI: general register QI view */
|
|
{ "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnPrefixedHI: general register HI view */
|
|
{ "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32RnPrefixedSI: general register SI view */
|
|
{ "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16RnQI-S: general register QI view */
|
|
{ "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16AnQI-S: address register QI view */
|
|
{ "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit16Rn: general register bit view */
|
|
{ "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit32RnPrefixed: general register bit view */
|
|
{ "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit32RnUnprefixed: general register bit view */
|
|
{ "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R0: r0 */
|
|
{ "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R1: r1 */
|
|
{ "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R2: r2 */
|
|
{ "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R3: r3 */
|
|
{ "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R0l: r0l */
|
|
{ "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R0h: r0h */
|
|
{ "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R2R0: r2r0 */
|
|
{ "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R3R1: r3r1 */
|
|
{ "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* R1R2R0: r1r2r0 */
|
|
{ "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16An: address register */
|
|
{ "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16AnQI: address register QI view */
|
|
{ "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16AnHI: address register HI view */
|
|
{ "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16AnSI: address register SI view */
|
|
{ "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst16An-S: address register HI view */
|
|
{ "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnUnprefixed: address register */
|
|
{ "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnUnprefixedQI: address register QI view */
|
|
{ "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnUnprefixedHI: address register HI view */
|
|
{ "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnUnprefixedSI: address register SI view */
|
|
{ "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnExtUnprefixed: address register */
|
|
{ "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnPrefixed: address register */
|
|
{ "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnPrefixedQI: address register QI view */
|
|
{ "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnPrefixedHI: address register HI view */
|
|
{ "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dst32AnPrefixedSI: address register SI view */
|
|
{ "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit16An: address register bit view */
|
|
{ "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit32AnPrefixed: address register bit */
|
|
{ "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit32AnUnprefixed: address register bit */
|
|
{ "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* A0: a0 */
|
|
{ "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* A1: a1 */
|
|
{ "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* sb: SB register */
|
|
{ "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* fb: FB register */
|
|
{ "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* sp: SP register */
|
|
{ "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
|
|
{ "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Regsetpop: popm regset */
|
|
{ "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Regsetpush: pushm regset */
|
|
{ "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Rn16-push-S: r0[lh] */
|
|
{ "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* An16-push-S: a[01] */
|
|
{ "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
|
|
{ 0, { { { (1<<MACH_M16C), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
|
|
{ "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
|
|
{ "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
|
|
{ "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
|
|
{ "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
|
|
{ "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-u20: unsigned 20 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-u20", M32C_OPERAND_DSP_40_U20, HW_H_UINT, 8, 20,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U20] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
|
|
{ "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
|
|
{ "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
|
|
{ "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
|
|
{ "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
|
|
{ "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-u20: unsigned 24 bit displacement at offset 40 bits */
|
|
{ "Dsp-48-u20", M32C_OPERAND_DSP_48_U20, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_48_U20_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
|
|
{ "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
|
|
{ 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
|
|
{ "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
|
|
{ "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
|
|
{ "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
|
|
{ "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
|
|
{ "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
|
|
{ "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
|
|
{ "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
|
|
{ "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
|
|
{ "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
|
|
{ "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
|
|
{ "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
|
|
{ "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
|
|
{ "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
|
|
{ "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
|
|
{ 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
|
|
{ "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
|
|
{ "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
|
|
{ "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
|
|
{ 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
|
|
{ "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
|
|
{ "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
|
|
{ "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
|
|
{ "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
|
|
{ "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
|
|
{ "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
|
|
{ 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
|
|
{ "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
|
|
{ "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
|
|
{ "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
|
|
{ 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
|
|
{ "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
|
|
{ "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
|
|
{ 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
|
|
{ "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm1-S: signed 1 bit immediate for short format binary insns */
|
|
{ "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
|
|
{ 0, { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Imm3-S: signed 3 bit immediate for short format binary insns */
|
|
{ "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
|
|
{ 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bit3-S: 3 bit bit number */
|
|
{ "Bit3-S", M32C_OPERAND_BIT3_S, HW_H_SINT, 2, 3,
|
|
{ 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bitno16R: bit number for indexing registers */
|
|
{ "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bitno32Prefixed: bit number for indexing objects */
|
|
{ "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Bitno32Unprefixed: bit number for indexing objects */
|
|
{ "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
|
|
{ "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
|
|
{ "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
|
|
{ "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
|
|
{ "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
|
|
{ "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
|
|
{ "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
|
|
{ "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
|
|
{ "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
|
|
{ "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
|
|
{ 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
|
|
{ "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
|
|
{ "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
|
|
{ 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
|
|
{ "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
|
|
{ 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
|
|
{ "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
|
|
{ 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
|
|
{ "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
|
|
{ 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-5-3: 3 bit label */
|
|
{ "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab32-jmp-s: 3 bit label */
|
|
{ "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
|
|
{ 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-8-8: 8 bit label */
|
|
{ "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-8-16: 16 bit label */
|
|
{ "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
|
|
{ 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-8-24: 24 bit label */
|
|
{ "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
|
|
{ 0|A(RELAX)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-16-8: 8 bit label */
|
|
{ "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-24-8: 8 bit label */
|
|
{ "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-32-8: 8 bit label */
|
|
{ "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Lab-40-8: 8 bit label */
|
|
{ "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
|
|
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* sbit: negative bit */
|
|
{ "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* obit: overflow bit */
|
|
{ "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* zbit: zero bit */
|
|
{ "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cbit: carry bit */
|
|
{ "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* ubit: stack ptr select bit */
|
|
{ "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* ibit: interrupt enable bit */
|
|
{ "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* bbit: reg bank select bit */
|
|
{ "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* dbit: debug bit */
|
|
{ "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16-16: condition */
|
|
{ "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16-24: condition */
|
|
{ "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16-32: condition */
|
|
{ "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32-16: condition */
|
|
{ "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32-24: condition */
|
|
{ "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32-32: condition */
|
|
{ "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32-40: condition */
|
|
{ "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16c: condition */
|
|
{ "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16j: condition */
|
|
{ "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond16j5: condition */
|
|
{ "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32: condition */
|
|
{ "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
|
|
{ 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cond32j: condition */
|
|
{ "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
|
|
{ 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
|
|
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* sccond32: scCND condition */
|
|
{ "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* flags16: flags */
|
|
{ "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* flags32: flags */
|
|
{ "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr16: control */
|
|
{ "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr1-Unprefixed-32: control */
|
|
{ "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr1-Prefixed-32: control */
|
|
{ "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr2-32: control */
|
|
{ "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr3-Unprefixed-32: control */
|
|
{ "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* cr3-Prefixed-32: control */
|
|
{ "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
|
|
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Z: Suffix for zero format insns */
|
|
{ "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* S: Suffix for short format insns */
|
|
{ "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* Q: Suffix for quick format insns */
|
|
{ "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* G: Suffix for general format insns */
|
|
{ "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* X: Empty suffix */
|
|
{ "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* size: any size specifier */
|
|
{ "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* BitIndex: Bit Index for the next insn */
|
|
{ "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* SrcIndex: Source Index for the next insn */
|
|
{ "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* DstIndex: Destination Index for the next insn */
|
|
{ "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* NoRemainder: Place holder for when the remainder is not kept */
|
|
{ "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0|A(SEM_ONLY), { { { (1<<MACH_M32C), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* src16-Rn-direct-QI: m16c Rn direct source QI */
|
|
/* src16-Rn-direct-HI: m16c Rn direct source HI */
|
|
/* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
|
|
/* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
|
|
/* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
|
|
/* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
|
|
/* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
|
|
/* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
|
|
/* src16-An-direct-QI: m16c An direct destination QI */
|
|
/* src16-An-direct-HI: m16c An direct destination HI */
|
|
/* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
|
|
/* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
|
|
/* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
|
|
/* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
|
|
/* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
|
|
/* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
|
|
/* src16-An-indirect-QI: m16c An indirect destination QI */
|
|
/* src16-An-indirect-HI: m16c An indirect destination HI */
|
|
/* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
|
|
/* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
|
|
/* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
|
|
/* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
|
|
/* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
|
|
/* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
|
|
/* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* src16-16-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* src16-16-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* src16-16-16-absolute-QI: m16c absolute address QI */
|
|
/* src16-16-16-absolute-HI: m16c absolute address HI */
|
|
/* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* src16-2-S-8-SB-relative-QI: m16c SB relative address */
|
|
/* src16-2-S-8-FB-relative-QI: m16c FB relative address */
|
|
/* src16-2-S-16-absolute-QI: m16c absolute address */
|
|
/* src32-2-S-8-SB-relative-QI: m32c SB relative address */
|
|
/* src32-2-S-8-FB-relative-QI: m32c FB relative address */
|
|
/* src32-2-S-16-absolute-QI: m32c absolute address */
|
|
/* src32-2-S-8-SB-relative-HI: m32c SB relative address */
|
|
/* src32-2-S-8-FB-relative-HI: m32c FB relative address */
|
|
/* src32-2-S-16-absolute-HI: m32c absolute address */
|
|
/* dst16-Rn-direct-QI: m16c Rn direct destination QI */
|
|
/* dst16-Rn-direct-HI: m16c Rn direct destination HI */
|
|
/* dst16-Rn-direct-SI: m16c Rn direct destination SI */
|
|
/* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
|
|
/* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
|
|
/* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
|
|
/* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
|
|
/* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
|
|
/* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
|
|
/* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
|
|
/* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
|
|
/* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
|
|
/* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
|
|
/* dst16-An-direct-QI: m16c An direct destination QI */
|
|
/* dst16-An-direct-HI: m16c An direct destination HI */
|
|
/* dst16-An-direct-SI: m16c An direct destination SI */
|
|
/* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
|
|
/* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
|
|
/* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
|
|
/* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
|
|
/* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
|
|
/* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
|
|
/* dst16-An-indirect-QI: m16c An indirect destination QI */
|
|
/* dst16-An-indirect-HI: m16c An indirect destination HI */
|
|
/* dst16-An-indirect-SI: m16c An indirect destination SI */
|
|
/* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
|
|
/* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
|
|
/* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
|
|
/* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
|
|
/* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
|
|
/* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
|
|
/* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
|
|
/* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
|
|
/* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
|
|
/* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst16-16-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst16-24-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst16-32-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst16-40-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst16-48-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
|
|
/* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* dst16-16-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* dst16-24-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* dst16-32-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* dst16-40-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
|
|
/* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
|
|
/* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
|
|
/* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
|
|
/* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
|
|
/* dst16-48-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
|
|
/* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
|
|
/* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
|
|
/* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
|
|
/* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
|
|
/* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
|
|
/* dst16-16-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
|
|
/* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
|
|
/* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
|
|
/* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
|
|
/* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
|
|
/* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
|
|
/* dst16-24-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
|
|
/* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
|
|
/* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
|
|
/* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
|
|
/* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
|
|
/* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
|
|
/* dst16-32-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
|
|
/* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
|
|
/* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
|
|
/* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
|
|
/* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
|
|
/* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
|
|
/* dst16-40-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
|
|
/* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
|
|
/* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
|
|
/* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
|
|
/* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
|
|
/* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
|
|
/* dst16-48-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
|
|
/* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
|
|
/* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
|
|
/* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
|
|
/* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
|
|
/* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
|
|
/* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
|
|
/* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
|
|
/* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
|
|
/* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
|
|
/* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
|
|
/* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
|
|
/* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
|
|
/* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
|
|
/* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
|
|
/* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
|
|
/* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
|
|
/* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
|
|
/* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
|
|
/* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
|
|
/* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
|
|
/* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
|
|
/* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
|
|
/* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
|
|
/* dst16-16-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-24-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-32-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-40-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-48-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-16-16-absolute-HI: m16c absolute address HI */
|
|
/* dst16-24-16-absolute-HI: m16c absolute address HI */
|
|
/* dst16-32-16-absolute-HI: m16c absolute address HI */
|
|
/* dst16-40-16-absolute-HI: m16c absolute address HI */
|
|
/* dst16-48-16-absolute-HI: m16c absolute address HI */
|
|
/* dst16-16-16-absolute-SI: m16c absolute address SI */
|
|
/* dst16-24-16-absolute-SI: m16c absolute address SI */
|
|
/* dst16-32-16-absolute-SI: m16c absolute address SI */
|
|
/* dst16-40-16-absolute-SI: m16c absolute address SI */
|
|
/* dst16-48-16-absolute-SI: m16c absolute address SI */
|
|
/* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
|
|
/* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
|
|
/* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
|
|
/* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
|
|
/* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
|
|
/* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
|
|
/* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
|
|
/* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
|
|
/* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
|
|
/* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
|
|
/* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
|
|
/* bit16-Rn-direct: m16c Rn direct bit */
|
|
/* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
|
|
/* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
|
|
/* bit16-An-direct: m16c An direct bit */
|
|
/* bit32-An-direct-Unprefixed: m32c An direct bit */
|
|
/* bit32-An-direct-Prefixed: m32c An direct bit */
|
|
/* bit16-An-indirect: m16c An indirect bit */
|
|
/* bit32-An-indirect-Unprefixed: m32c An indirect destination */
|
|
/* bit32-An-indirect-Prefixed: m32c An indirect destination */
|
|
/* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
|
|
/* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
|
|
/* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
|
|
/* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
|
|
/* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
|
|
/* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
|
|
/* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
|
|
/* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
|
|
/* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
|
|
/* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
|
|
/* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
|
|
/* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
|
|
/* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
|
|
/* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
|
|
/* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
|
|
/* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
|
|
/* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
|
|
/* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
|
|
/* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
|
|
/* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
|
|
/* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
|
|
/* An16-push-S-derived: m16c r0[lh] for push,pop short version */
|
|
/* bit16-16-16-absolute: m16c absolute address */
|
|
/* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
|
|
/* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
|
|
/* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
|
|
/* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
|
|
/* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
|
|
/* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
|
|
/* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
|
|
/* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
|
|
/* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
|
|
/* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
|
|
/* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
|
|
/* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
|
|
/* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
|
|
/* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
|
|
/* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
|
|
/* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
|
|
/* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
|
|
/* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
|
|
/* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
|
|
/* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
|
|
/* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
|
|
/* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
|
|
/* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
|
|
/* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
|
|
/* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
|
|
/* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
|
|
/* src16-basic-QI: m16c source operand of size QI with no additional fields */
|
|
/* src16-basic-HI: m16c source operand of size HI with no additional fields */
|
|
/* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
|
|
/* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
|
|
/* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
|
|
/* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
|
|
/* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
|
|
/* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
|
|
/* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
|
|
/* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
|
|
/* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
|
|
/* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
|
|
/* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
|
|
/* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
|
|
/* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
|
|
/* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
|
|
/* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
|
|
/* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
|
|
/* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
|
|
/* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
|
|
/* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
|
|
/* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
|
|
/* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
|
|
/* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
|
|
/* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
|
|
/* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
|
|
/* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
|
|
/* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
|
|
/* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
|
|
/* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
|
|
/* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
|
|
/* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
|
|
/* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
|
|
/* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
|
|
/* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
|
|
/* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
|
|
/* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
|
|
/* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
|
|
/* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
|
|
/* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
|
|
/* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst16-16-16sa-QI: m16c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst16-16-20ar-QI: m16c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-16-16sa-HI: m16c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-16-20ar-HI: m16c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst16-16-16sa-SI: m16c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst16-16-20ar-SI: m16c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
|
|
/* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
|
|
/* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
|
|
/* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
|
|
/* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
|
|
/* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
|
|
/* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
|
|
/* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
|
|
/* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
|
|
/* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
|
|
/* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
|
|
/* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
|
|
/* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
|
|
/* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
|
|
/* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
|
|
/* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
|
|
/* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
|
|
/* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
|
|
/* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-16sa-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-16sa-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-16sa-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
|
|
/* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
|
|
/* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
|
|
/* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
|
|
/* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
|
|
/* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
|
|
/* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
|
|
/* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
|
|
/* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
|
|
/* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
|
|
/* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
|
|
/* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
|
|
/* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
|
|
/* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
|
|
/* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
|
|
/* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
|
|
/* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
|
|
/* bit16-16: m16c bit operand with possible additional fields at offset 24 */
|
|
/* bit16-16-basic: m16c bit operand with no additional fields */
|
|
/* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
|
|
/* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
|
|
/* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
|
|
/* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
|
|
/* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
|
|
/* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
|
|
/* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
|
|
/* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
|
|
/* src16-2-S: m16c source operand of size QI for short format insns */
|
|
/* src32-2-S-QI: m32c source operand of size QI for short format insns */
|
|
/* src32-2-S-HI: m32c source operand of size QI for short format insns */
|
|
/* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
|
|
/* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
|
|
/* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
|
|
/* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
|
|
/* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
|
|
/* dst32-2-S-8-QI: m32c operand of size */
|
|
/* dst32-2-S-16-QI: m32c operand of size */
|
|
/* dst32-2-S-8-HI: m32c operand of size */
|
|
/* dst32-2-S-16-HI: m32c operand of size */
|
|
/* dst32-2-S-8-SI: m32c operand of size */
|
|
/* dst32-2-S-16-SI: m32c operand of size */
|
|
/* dst32-an-S: m32c An operand for short format binary insns */
|
|
/* bit16-11-S: m16c bit operand for short format insns */
|
|
/* Rn16-push-S-anyof: m16c bit operand for short format insns */
|
|
/* An16-push-S-anyof: m16c bit operand for short format insns */
|
|
/* sentinel */
|
|
{ 0, 0, 0, 0, 0,
|
|
{ 0, { (const PTR) 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } }
|
|
};
|
|
|
|
#undef A
|
|
|
|
|
|
/* The instruction table. */
|
|
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
#define A(a) (1 << CGEN_INSN_##a)
|
|
|
|
static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
|
{
|
|
/* Special null first entry.
|
|
A `num' value of zero is thus invalid.
|
|
Also, the special `invalid' insn resides here. */
|
|
{ 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* extz [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w $Dst32RnExtUnprefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w $Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w [$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Dst32RnExtUnprefixedQI */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b $Dst16RnExtQI */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* xchg.w r3,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a1,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w a0,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a1,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b a0,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r3,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r2,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r1,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.w r0,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r1l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* xchg.b r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stz${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stz${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* stnz${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stnz${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l r1h,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w r1h,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l r1h,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w r1h,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sc${sccond32} $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sc${sccond32} ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w r1h,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.b r1h,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rorc.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* rolc.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha [$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pusha ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l $Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l $Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.l ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${S} ${An16-push-S} */
|
|
{
|
|
M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.b${S} ${Rn16-push-S} */
|
|
{
|
|
M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} $Dst16RnHI */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} $Dst16AnHI */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.w${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} $Dst16RnQI */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} $Dst16AnQI */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* push.b${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${S} ${An16-push-S} */
|
|
{
|
|
M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pop.b${S} ${Rn16-push-S} */
|
|
{
|
|
M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pop.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} $Dst16RnHI */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} $Dst16AnHI */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.w${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} $Dst16RnQI */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} $Dst16AnQI */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* pop.b${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_OR16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "or16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "or.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "or16.b.S-src2-src16-2-S-8-SB-relative-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "or16.b.S-src2-src16-2-S-8-FB-relative-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_OR16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "or16.b.S-src2-src16-2-S-16-absolute-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b:s r0l */
|
|
{
|
|
M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* not.b:s r0h */
|
|
{
|
|
M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* not.b:s ${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* not.b:s ${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* not.b:s ${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* not.w${G} $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} $Dst16RnHI */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} $Dst16AnHI */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.w${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} $Dst16RnQI */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} $Dst16AnQI */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} [$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* not.b${G} ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* neg.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mulex $R3 */
|
|
{
|
|
M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulex ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l $Dst32RnPrefixedSI,r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_RN_DIRECT_PREFIXED_SI, "mulu_l-dst32-Rn-direct-Prefixed-SI", "mulu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l $Dst32AnPrefixedSI,r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_AN_DIRECT_PREFIXED_SI, "mulu_l-dst32-An-direct-Prefixed-SI", "mulu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l [$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_AN_INDIRECT_PREFIXED_SI, "mulu_l-dst32-An-indirect-Prefixed-SI", "mulu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-8-An-relative-Prefixed-SI", "mulu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-16-An-relative-Prefixed-SI", "mulu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-24-An-relative-Prefixed-SI", "mulu.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u8}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-8-SB-relative-Prefixed-SI", "mulu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u16}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-16-SB-relative-Prefixed-SI", "mulu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-s8}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-8-FB-relative-Prefixed-SI", "mulu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-s16}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "mulu_l-dst32-24-16-FB-relative-Prefixed-SI", "mulu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u16},r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_16_ABSOLUTE_PREFIXED_SI, "mulu_l-dst32-24-16-absolute-Prefixed-SI", "mulu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mulu.l ${Dsp-24-u24},r2r0 */
|
|
{
|
|
M32C_INSN_MULU_L_DST32_24_24_ABSOLUTE_PREFIXED_SI, "mulu_l-dst32-24-24-absolute-Prefixed-SI", "mulu.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l $Dst32RnPrefixedSI,r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_RN_DIRECT_PREFIXED_SI, "mul_l-dst32-Rn-direct-Prefixed-SI", "mul.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l $Dst32AnPrefixedSI,r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_AN_DIRECT_PREFIXED_SI, "mul_l-dst32-An-direct-Prefixed-SI", "mul.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l [$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_AN_INDIRECT_PREFIXED_SI, "mul_l-dst32-An-indirect-Prefixed-SI", "mul.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u8}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-8-An-relative-Prefixed-SI", "mul.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u16}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-16-An-relative-Prefixed-SI", "mul.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u24}[$Dst32AnPrefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-24-An-relative-Prefixed-SI", "mul.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u8}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-8-SB-relative-Prefixed-SI", "mul.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u16}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-16-SB-relative-Prefixed-SI", "mul.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-s8}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-8-FB-relative-Prefixed-SI", "mul.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-s16}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "mul_l-dst32-24-16-FB-relative-Prefixed-SI", "mul.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u16},r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_16_ABSOLUTE_PREFIXED_SI, "mul_l-dst32-24-16-absolute-Prefixed-SI", "mul.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.l ${Dsp-24-u24},r2r0 */
|
|
{
|
|
M32C_INSN_MUL_L_DST32_24_24_ABSOLUTE_PREFIXED_SI, "mul_l-dst32-24-24-absolute-Prefixed-SI", "mul.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* movhh $Dst32RnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh $Dst32AnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh [$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-s16}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-24-u24},r0l */
|
|
{
|
|
M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl $Dst32RnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl $Dst32AnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl [$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-s16}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-24-u24},r0l */
|
|
{
|
|
M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh $Dst32RnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh $Dst32AnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh [$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-s16}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-24-u24},r0l */
|
|
{
|
|
M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll $Dst32RnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll $Dst32AnPrefixedQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll [$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-s16}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-24-u24},r0l */
|
|
{
|
|
M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh $Dst16RnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh $Dst16AnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh [$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-u8}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-u16}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh ${Dsp-16-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl $Dst16RnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl $Dst16AnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl [$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-u8}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-u16}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl ${Dsp-16-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh $Dst16RnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh $Dst16AnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh [$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-u8}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-u16}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh ${Dsp-16-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll $Dst16RnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll $Dst16AnQI,r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll [$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-u8}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-u16}[$Dst16An],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-u16}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll ${Dsp-16-u16},r0l */
|
|
{
|
|
M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhh r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movhl r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movlh r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* movll r0l,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst32AnUnprefixed],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s16}[fb],a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24},a1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst32AnUnprefixed],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s16}[fb],a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24},a0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst32AnUnprefixed],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s16}[fb],r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24},r3r1 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst32AnUnprefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s16}[fb],r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u24},r2r0 */
|
|
{
|
|
M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},a1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},a0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r3 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r2 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r1 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova [$Dst16An],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[$Dst16An],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[$Dst16An],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u8}[sb],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16}[sb],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-s8}[fb],r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mova ${Dsp-16-u16},r0 */
|
|
{
|
|
M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
|
|
{
|
|
M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-u8}[sb],a1 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-s8}[fb],a1 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-u8}[sb],a0 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-s8}[fb],a0 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-u16},a1 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${S} ${Dsp-8-u16},a0 */
|
|
{
|
|
M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} r0,${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} r0,${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} r0l,${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} r0l,${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} r0,${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} r0l,${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-u8}[sb],r1 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-s8}[fb],r1 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u8}[sb],r1l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-s8}[fb],r1l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-u16},r1 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u16},r1l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} r0,r1 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} r0l,r1l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-u8}[sb],r0 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-s8}[fb],r0 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u8}[sb],r0l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-s8}[fb],r0l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} ${Dsp-8-u16},r0 */
|
|
{
|
|
M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u16},r0l */
|
|
{
|
|
M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Z} #0,${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${Z} #0,${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${Z} #0,${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${Z} #0,r0 */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,r0l */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,r0l */
|
|
{
|
|
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,r0h */
|
|
{
|
|
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${Z} #0,${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-Rn-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-direct-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "mov16.w-imm4-Q-16-dst16-An-indirect-HI", "mov.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16},[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16RnHI,[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16AnHI,[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w [$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16RnHI,${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w $Dst16AnHI,${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.w [$Dst16An],${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16},[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
|
{
|
|
M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16RnQI,[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16AnQI,[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b [$Dst16An],[a1a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16RnQI,${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b $Dst16AnQI,${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ste.b [$Dst16An],${Dsp-16-u20} */
|
|
{
|
|
M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w [a1a0],[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.w ${Dsp-16-u20},[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b [a1a0],[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* lde.b ${Dsp-16-u20},[$Dst16An] */
|
|
{
|
|
M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr2-32},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc pc,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stc ${cr16},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32RnUnprefixedSI,${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32AnUnprefixedSI,${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc [$Dst32AnUnprefixed],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u8}[sb],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16}[sb],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-s8}[fb],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-s16}[fb],${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16},${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u24},${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst16RnHI,${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc $Dst16AnHI,${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc [$Dst16An],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u8}[sb],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16}[sb],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-s8}[fb],${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc ${Dsp-16-u16},${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a $Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a $Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a $Dst16RnSI */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a $Dst16AnSI */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a [$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16sa-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16sa-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-24-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "jsri.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-24-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "jsri.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.a ${Dsp-16-u20}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16A_DST16_16_20AR_SI_DST16_16_20_AN_RELATIVE_SI, "jsri16a-dst16-16-20ar-SI-dst16-16-20-An-relative-SI", "jsri.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16sa-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16sa-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-24-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-24-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jsri.w ${Dsp-16-u20}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JSRI16W_DST16_16_20AR_HI_DST16_16_20_AN_RELATIVE_HI, "jsri16w-dst16-16-20ar-HI-dst16-16-20-An-relative-HI", "jsri.w", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a $Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a $Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a $Dst16RnSI */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a $Dst16AnSI */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a [$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.a ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* jmpi.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexws.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexwd.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexw.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexls.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexld.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexl.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbs.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexbd.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* indexb.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* inc.b r0l */
|
|
{
|
|
M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* inc.b r0h */
|
|
{
|
|
M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* inc.b ${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* divx.l $Dst32RnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l $Dst32AnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l [$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.l ${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l $Dst32RnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l $Dst32AnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l [$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.l ${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l $Dst32RnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l $Dst32AnPrefixedSI */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l [$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.l ${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dec.b r0l */
|
|
{
|
|
M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.b r0h */
|
|
{
|
|
M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.b ${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
|
|
{
|
|
M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
|
|
{
|
|
M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
|
|
{
|
|
M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
|
|
{
|
|
M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
|
|
{
|
|
M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
|
|
{
|
|
M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bxor${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btsts${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btstc${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BTST32_G_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-G-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${S} ${BitBase16-8-u11-S}[sb] */
|
|
{
|
|
M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst${G} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${X} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${S} ${BitBase16-8-u11-S}[sb] */
|
|
{
|
|
M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bset${G} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bor${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnxor${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bntst${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${X} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${S} ${BitBase16-8-u11-S}[sb] */
|
|
{
|
|
M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnot${G} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnor${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bnand${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-24} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-24} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-24} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-24} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-32} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-32} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm${cond16-16} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bitindex.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bitindex.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u19-Unprefixed} */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${X} ${BitBase32-16-u27-Unprefixed} */
|
|
{
|
|
M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${S} ${BitBase16-8-u11-S}[sb] */
|
|
{
|
|
M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bclr${G} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u19-Prefixed} */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase32-24-u27-Prefixed} */
|
|
{
|
|
M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} $Bitno16R,$Bit16Rn */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} $Bitno16R,$Bit16An */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} [$Bit16An] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${Dsp-16-u8}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${Dsp-16-u16}[$Bit16An] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase16-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase16-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase16-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* band${X} ${BitBase16-16-u16} */
|
|
{
|
|
M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
|
|
{
|
|
M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.w${S} #${Imm-8-HI},r0 */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l${S} #${Imm1-S},a0 */
|
|
{
|
|
M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l${S} #${Imm1-S},a1 */
|
|
{
|
|
M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
|
|
{
|
|
M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
|
|
{
|
|
M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16RnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} $Src16AnHI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16RnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} $Src16AnQI,${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} [$Src16An],${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_2ADDR, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},r0l */
|
|
{
|
|
M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},r0h */
|
|
{
|
|
M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},$Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},$Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-16-HI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},$Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},$Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-16-QI},[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* adcf.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w $Dst32RnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w $Dst32AnUnprefixedHI */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b $Dst32RnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b $Dst32AnUnprefixedQI */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b [$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-s16}[fb] */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u24} */
|
|
{
|
|
M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w $Dst16RnHI */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w $Dst16AnHI */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w [$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.w ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b $Dst16RnQI */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b $Dst16AnQI */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b [$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u8}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16}[$Dst16An] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16}[sb] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* abs.b ${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
|
|
},
|
|
/* add.w$Q #${Imm-12-s4},sp */
|
|
{
|
|
M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.b$G #${Imm-16-QI},sp */
|
|
{
|
|
M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.w$G #${Imm-16-HI},sp */
|
|
{
|
|
M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l$Q #${Imm3-S},sp */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l$S #${Imm-16-QI},sp */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* add.l$G #${Imm-16-HI},sp */
|
|
{
|
|
M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadc.b #${Imm-16-QI},r0l */
|
|
{
|
|
M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadc.w #${Imm-16-HI},r0 */
|
|
{
|
|
M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadc.b r0h,r0l */
|
|
{
|
|
M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadc.w r1,r0 */
|
|
{
|
|
M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadd.b #${Imm-16-QI},r0l */
|
|
{
|
|
M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadd.w #${Imm-16-HI},r0 */
|
|
{
|
|
M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadd.b r0h,r0l */
|
|
{
|
|
M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dadd.w r1,r0 */
|
|
{
|
|
M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm$cond16c c */
|
|
{
|
|
M32C_INSN_BM16_C, "bm16-c", "bm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* bm$cond32 c */
|
|
{
|
|
M32C_INSN_BM32_C, "bm32-c", "bm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* brk */
|
|
{
|
|
M32C_INSN_BRK16, "brk16", "brk", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* brk */
|
|
{
|
|
M32C_INSN_BRK32, "brk32", "brk", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* brk2 */
|
|
{
|
|
M32C_INSN_BRK232, "brk232", "brk2", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* btst:s ${Bit3-S},${Dsp-8-u16} */
|
|
{
|
|
M32C_INSN_BTST_S, "btst.s", "btst:s", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dec.w ${Dst16An-S} */
|
|
{
|
|
M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* div.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divu.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.b #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* divx.w #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsbb.b #${Imm-16-QI},r0l */
|
|
{
|
|
M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsbb.w #${Imm-16-HI},r0 */
|
|
{
|
|
M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsbb.b r0h,r0l */
|
|
{
|
|
M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsbb.w r1,r0 */
|
|
{
|
|
M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsub.b #${Imm-16-QI},r0l */
|
|
{
|
|
M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsub.w #${Imm-16-HI},r0 */
|
|
{
|
|
M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsub.b r0h,r0l */
|
|
{
|
|
M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dsub.w r1,r0 */
|
|
{
|
|
M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* enter #${Dsp-16-u8} */
|
|
{
|
|
M32C_INSN_ENTER16, "enter16", "enter", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exitd */
|
|
{
|
|
M32C_INSN_EXITD16, "exitd16", "exitd", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* enter #${Dsp-8-u8} */
|
|
{
|
|
M32C_INSN_ENTER32, "enter32", "enter", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exitd */
|
|
{
|
|
M32C_INSN_EXITD32, "exitd32", "exitd", 8,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* fclr ${flags16} */
|
|
{
|
|
M32C_INSN_FCLR16, "fclr16", "fclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* fset ${flags16} */
|
|
{
|
|
M32C_INSN_FSET16, "fset16", "fset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* fclr ${flags32} */
|
|
{
|
|
M32C_INSN_FCLR, "fclr", "fclr", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* fset ${flags32} */
|
|
{
|
|
M32C_INSN_FSET, "fset", "fset", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* inc.w ${Dst16An-S} */
|
|
{
|
|
M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* freit */
|
|
{
|
|
M32C_INSN_FREIT32, "freit32", "freit", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* int #${Dsp-10-u6} */
|
|
{
|
|
M32C_INSN_INT16, "int16", "int", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* into */
|
|
{
|
|
M32C_INSN_INTO16, "into16", "into", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* int #${Dsp-8-u6} */
|
|
{
|
|
M32C_INSN_INT32, "int32", "int", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* into */
|
|
{
|
|
M32C_INSN_INTO32, "into32", "into", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* j$cond16j5 ${Lab-8-8} */
|
|
{
|
|
M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* j$cond16j ${Lab-16-8} */
|
|
{
|
|
M32C_INSN_JCND16, "jcnd16", "j", 24,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* j$cond32j ${Lab-8-8} */
|
|
{
|
|
M32C_INSN_JCND32, "jcnd32", "j", 16,
|
|
{ 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.s ${Lab-5-3} */
|
|
{
|
|
M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.b ${Lab-8-8} */
|
|
{
|
|
M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.w ${Lab-8-16} */
|
|
{
|
|
M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.a ${Lab-8-24} */
|
|
{
|
|
M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmps #${Imm-8-QI} */
|
|
{
|
|
M32C_INSN_JMPS16, "jmps16", "jmps", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* jmp.s ${Lab32-jmp-s} */
|
|
{
|
|
M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.b ${Lab-8-8} */
|
|
{
|
|
M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.w ${Lab-8-16} */
|
|
{
|
|
M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmp.a ${Lab-8-24} */
|
|
{
|
|
M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jmps #${Imm-8-QI} */
|
|
{
|
|
M32C_INSN_JMPS32, "jmps32", "jmps", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jsr.w ${Lab-8-16} */
|
|
{
|
|
M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jsr.a ${Lab-8-24} */
|
|
{
|
|
M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jsr.w ${Lab-8-16} */
|
|
{
|
|
M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
|
|
{ 0|A(RELAXABLE)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jsr.a ${Lab-8-24} */
|
|
{
|
|
M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_JUMP, 0 } } } }
|
|
},
|
|
/* jsrs #${Imm-8-QI} */
|
|
{
|
|
M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* jsrs #${Imm-8-QI} */
|
|
{
|
|
M32C_INSN_JSRS, "jsrs", "jsrs", 16,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc #${Imm-16-HI},${cr16} */
|
|
{
|
|
M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc #${Dsp-16-u24},${cr2-32} */
|
|
{
|
|
M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
|
|
{
|
|
M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_STCTX16, "stctx16", "stctx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stctx ${Dsp-16-u16},${Dsp-32-u24} */
|
|
{
|
|
M32C_INSN_STCTX32, "stctx32", "stctx", 56,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldipl #${Imm-13-u3} */
|
|
{
|
|
M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* ldipl #${Imm-13-u3} */
|
|
{
|
|
M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b$S #${Imm-8-QI},a0 */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b$S #${Imm-8-QI},a1 */
|
|
{
|
|
M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w$S #${Imm-8-HI},a0 */
|
|
{
|
|
M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w$S #${Imm-8-HI},a1 */
|
|
{
|
|
M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w$S #${Imm-8-HI},a0 */
|
|
{
|
|
M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.w$S #${Imm-8-HI},a1 */
|
|
{
|
|
M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l$S #${Dsp-8-s24},a0 */
|
|
{
|
|
M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.l$S #${Dsp-8-s24},a1 */
|
|
{
|
|
M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b$S r0l,a1 */
|
|
{
|
|
M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* mov.b$S r0h,a0 */
|
|
{
|
|
M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* nop */
|
|
{
|
|
M32C_INSN_NOP16, "nop16", "nop", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* nop */
|
|
{
|
|
M32C_INSN_NOP32, "nop32", "nop", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* popc ${cr16} */
|
|
{
|
|
M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* popc ${cr1-Unprefixed-32} */
|
|
{
|
|
M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* popc ${cr2-32} */
|
|
{
|
|
M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pushc ${cr16} */
|
|
{
|
|
M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pushc ${cr1-Unprefixed-32} */
|
|
{
|
|
M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pushc ${cr2-32} */
|
|
{
|
|
M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* popm ${Regsetpop} */
|
|
{
|
|
M32C_INSN_POPM16, "popm16", "popm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pushm ${Regsetpush} */
|
|
{
|
|
M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* popm ${Regsetpop} */
|
|
{
|
|
M32C_INSN_POPM, "popm", "popm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* pushm ${Regsetpush} */
|
|
{
|
|
M32C_INSN_PUSHM, "pushm", "pushm", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.b$G #${Imm-16-QI} */
|
|
{
|
|
M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.w$G #${Imm-16-HI} */
|
|
{
|
|
M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.b #${Imm-8-QI} */
|
|
{
|
|
M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.w #${Imm-8-HI} */
|
|
{
|
|
M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* push.l #${Imm-16-SI} */
|
|
{
|
|
M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* reit */
|
|
{
|
|
M32C_INSN_REIT16, "reit16", "reit", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* reit */
|
|
{
|
|
M32C_INSN_REIT32, "reit32", "reit", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rmpa.b */
|
|
{
|
|
M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rmpa.w */
|
|
{
|
|
M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rmpa.b */
|
|
{
|
|
M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rmpa.w */
|
|
{
|
|
M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rts */
|
|
{
|
|
M32C_INSN_RTS16, "rts16", "rts", 8,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* rts */
|
|
{
|
|
M32C_INSN_RTS32, "rts32", "rts", 8,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* scmpu.b */
|
|
{
|
|
M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* scmpu.w */
|
|
{
|
|
M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l #${Imm-sh-12-s4},r2r0 */
|
|
{
|
|
M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l #${Imm-sh-12-s4},r3r1 */
|
|
{
|
|
M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,r2r0 */
|
|
{
|
|
M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sha.l r1h,r3r1 */
|
|
{
|
|
M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l #${Imm-sh-12-s4},r2r0 */
|
|
{
|
|
M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l #${Imm-sh-12-s4},r3r1 */
|
|
{
|
|
M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,r2r0 */
|
|
{
|
|
M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* shl.l r1h,r3r1 */
|
|
{
|
|
M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sin.b */
|
|
{
|
|
M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sin.w */
|
|
{
|
|
M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovb.b */
|
|
{
|
|
M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovb.w */
|
|
{
|
|
M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovb.b */
|
|
{
|
|
M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovb.w */
|
|
{
|
|
M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovf.b */
|
|
{
|
|
M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovf.w */
|
|
{
|
|
M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovf.b */
|
|
{
|
|
M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovf.w */
|
|
{
|
|
M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovu.b */
|
|
{
|
|
M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* smovu.w */
|
|
{
|
|
M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sout.b */
|
|
{
|
|
M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sout.w */
|
|
{
|
|
M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sstr.b */
|
|
{
|
|
M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sstr.w */
|
|
{
|
|
M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sstr.b */
|
|
{
|
|
M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* sstr.w */
|
|
{
|
|
M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
|
|
{
|
|
M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
|
|
{
|
|
M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
|
|
{
|
|
M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
|
|
{
|
|
M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
|
|
{
|
|
M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* und */
|
|
{
|
|
M32C_INSN_UND16, "und16", "und", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* und */
|
|
{
|
|
M32C_INSN_UND32, "und32", "und", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* wait */
|
|
{
|
|
M32C_INSN_WAIT16, "wait16", "wait", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* wait */
|
|
{
|
|
M32C_INSN_WAIT, "wait", "wait", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* exts.w r0 */
|
|
{
|
|
M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* src-indirect */
|
|
{
|
|
M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* dest-indirect */
|
|
{
|
|
M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
/* src-dest-indirect */
|
|
{
|
|
M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_NONE, 0 } } } }
|
|
},
|
|
};
|
|
|
|
#undef OP
|
|
#undef A
|
|
|
|
/* Initialize anything needed to be done once, before any cpu_open call. */
|
|
|
|
static void
|
|
init_tables (void)
|
|
{
|
|
}
|
|
|
|
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
|
|
static void build_hw_table (CGEN_CPU_TABLE *);
|
|
static void build_ifield_table (CGEN_CPU_TABLE *);
|
|
static void build_operand_table (CGEN_CPU_TABLE *);
|
|
static void build_insn_table (CGEN_CPU_TABLE *);
|
|
static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
|
|
|
|
static const CGEN_MACH *
|
|
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
|
|
{
|
|
while (table->name)
|
|
{
|
|
if (strcmp (name, table->bfd_name) == 0)
|
|
return table;
|
|
++table;
|
|
}
|
|
abort ();
|
|
}
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_hw_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
|
|
/* MAX_HW is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_HW_ENTRY **selected =
|
|
(const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
|
|
cd->hw_table.init_entries = init;
|
|
cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
|
|
memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
/* ??? For now we just use machs to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->hw_table.entries = selected;
|
|
cd->hw_table.num_entries = MAX_HW;
|
|
}
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_ifield_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
cd->ifld_table = & m32c_cgen_ifld_table[0];
|
|
}
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_operand_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
|
|
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
|
|
|
|
cd->operand_table.init_entries = init;
|
|
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
|
|
memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
|
|
/* ??? For now we just use mach to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->operand_table.entries = selected;
|
|
cd->operand_table.num_entries = MAX_OPERANDS;
|
|
}
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to build the hardware table.
|
|
??? This could leave out insns not supported by the specified mach/isa,
|
|
but that would cause errors like "foo only supported by bar" to become
|
|
"unknown insn", so for now we include all insns and require the app to
|
|
do the checking later.
|
|
??? On the other hand, parsing of such insns may require their hardware or
|
|
operand elements to be in the table [which they mightn't be]. */
|
|
|
|
static void
|
|
build_insn_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
|
|
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
|
|
|
|
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
|
|
for (i = 0; i < MAX_INSNS; ++i)
|
|
insns[i].base = &ib[i];
|
|
cd->insn_table.init_entries = insns;
|
|
cd->insn_table.entry_size = sizeof (CGEN_IBASE);
|
|
cd->insn_table.num_init_entries = MAX_INSNS;
|
|
}
|
|
|
|
/* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
|
|
|
|
static void
|
|
m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
CGEN_BITSET *isas = cd->isas;
|
|
unsigned int machs = cd->machs;
|
|
|
|
cd->int_insn_p = CGEN_INT_INSN_P;
|
|
|
|
/* Data derived from the isa spec. */
|
|
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
|
|
cd->default_insn_bitsize = UNSET;
|
|
cd->base_insn_bitsize = UNSET;
|
|
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
|
|
cd->max_insn_bitsize = 0;
|
|
for (i = 0; i < MAX_ISAS; ++i)
|
|
if (cgen_bitset_contains (isas, i))
|
|
{
|
|
const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
|
|
|
|
/* Default insn sizes of all selected isas must be
|
|
equal or we set the result to 0, meaning "unknown". */
|
|
if (cd->default_insn_bitsize == UNSET)
|
|
cd->default_insn_bitsize = isa->default_insn_bitsize;
|
|
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
|
|
; /* This is ok. */
|
|
else
|
|
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Base insn sizes of all selected isas must be equal
|
|
or we set the result to 0, meaning "unknown". */
|
|
if (cd->base_insn_bitsize == UNSET)
|
|
cd->base_insn_bitsize = isa->base_insn_bitsize;
|
|
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
|
|
; /* This is ok. */
|
|
else
|
|
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Set min,max insn sizes. */
|
|
if (isa->min_insn_bitsize < cd->min_insn_bitsize)
|
|
cd->min_insn_bitsize = isa->min_insn_bitsize;
|
|
if (isa->max_insn_bitsize > cd->max_insn_bitsize)
|
|
cd->max_insn_bitsize = isa->max_insn_bitsize;
|
|
}
|
|
|
|
/* Data derived from the mach spec. */
|
|
for (i = 0; i < MAX_MACHS; ++i)
|
|
if (((1 << i) & machs) != 0)
|
|
{
|
|
const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
|
|
|
|
if (mach->insn_chunk_bitsize != 0)
|
|
{
|
|
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
|
|
{
|
|
fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
|
|
cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
|
|
abort ();
|
|
}
|
|
|
|
cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
|
|
}
|
|
}
|
|
|
|
/* Determine which hw elements are used by MACH. */
|
|
build_hw_table (cd);
|
|
|
|
/* Build the ifield table. */
|
|
build_ifield_table (cd);
|
|
|
|
/* Determine which operands are used by MACH/ISA. */
|
|
build_operand_table (cd);
|
|
|
|
/* Build the instruction table. */
|
|
build_insn_table (cd);
|
|
}
|
|
|
|
/* Initialize a cpu table and return a descriptor.
|
|
It's much like opening a file, and must be the first function called.
|
|
The arguments are a set of (type/value) pairs, terminated with
|
|
CGEN_CPU_OPEN_END.
|
|
|
|
Currently supported values:
|
|
CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
|
|
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
|
|
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
|
|
CGEN_CPU_OPEN_ENDIAN: specify endian choice
|
|
CGEN_CPU_OPEN_END: terminates arguments
|
|
|
|
??? Simultaneous multiple isas might not make sense, but it's not (yet)
|
|
precluded. */
|
|
|
|
CGEN_CPU_DESC
|
|
m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
|
|
{
|
|
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
|
|
static int init_p;
|
|
CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
|
|
unsigned int machs = 0; /* 0 = "unspecified" */
|
|
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
|
|
va_list ap;
|
|
|
|
if (! init_p)
|
|
{
|
|
init_tables ();
|
|
init_p = 1;
|
|
}
|
|
|
|
memset (cd, 0, sizeof (*cd));
|
|
|
|
va_start (ap, arg_type);
|
|
while (arg_type != CGEN_CPU_OPEN_END)
|
|
{
|
|
switch (arg_type)
|
|
{
|
|
case CGEN_CPU_OPEN_ISAS :
|
|
isas = va_arg (ap, CGEN_BITSET *);
|
|
break;
|
|
case CGEN_CPU_OPEN_MACHS :
|
|
machs = va_arg (ap, unsigned int);
|
|
break;
|
|
case CGEN_CPU_OPEN_BFDMACH :
|
|
{
|
|
const char *name = va_arg (ap, const char *);
|
|
const CGEN_MACH *mach =
|
|
lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
|
|
|
|
machs |= 1 << mach->num;
|
|
break;
|
|
}
|
|
case CGEN_CPU_OPEN_ENDIAN :
|
|
endian = va_arg (ap, enum cgen_endian);
|
|
break;
|
|
default :
|
|
fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
|
|
arg_type);
|
|
abort (); /* ??? return NULL? */
|
|
}
|
|
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
|
|
}
|
|
va_end (ap);
|
|
|
|
/* Mach unspecified means "all". */
|
|
if (machs == 0)
|
|
machs = (1 << MAX_MACHS) - 1;
|
|
/* Base mach is always selected. */
|
|
machs |= 1;
|
|
if (endian == CGEN_ENDIAN_UNKNOWN)
|
|
{
|
|
/* ??? If target has only one, could have a default. */
|
|
fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
|
|
abort ();
|
|
}
|
|
|
|
cd->isas = cgen_bitset_copy (isas);
|
|
cd->machs = machs;
|
|
cd->endian = endian;
|
|
/* FIXME: for the sparc case we can determine insn-endianness statically.
|
|
The worry here is where both data and insn endian can be independently
|
|
chosen, in which case this function will need another argument.
|
|
Actually, will want to allow for more arguments in the future anyway. */
|
|
cd->insn_endian = endian;
|
|
|
|
/* Table (re)builder. */
|
|
cd->rebuild_tables = m32c_cgen_rebuild_tables;
|
|
m32c_cgen_rebuild_tables (cd);
|
|
|
|
/* Default to not allowing signed overflow. */
|
|
cd->signed_overflow_ok_p = 0;
|
|
|
|
return (CGEN_CPU_DESC) cd;
|
|
}
|
|
|
|
/* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
|
|
MACH_NAME is the bfd name of the mach. */
|
|
|
|
CGEN_CPU_DESC
|
|
m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
|
|
{
|
|
return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
|
|
CGEN_CPU_OPEN_ENDIAN, endian,
|
|
CGEN_CPU_OPEN_END);
|
|
}
|
|
|
|
/* Close a cpu table.
|
|
??? This can live in a machine independent file, but there's currently
|
|
no place to put this file (there's no libcgen). libopcodes is the wrong
|
|
place as some simulator ports use this but they don't use libopcodes. */
|
|
|
|
void
|
|
m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
|
|
{
|
|
unsigned int i;
|
|
const CGEN_INSN *insns;
|
|
|
|
if (cd->macro_insn_table.init_entries)
|
|
{
|
|
insns = cd->macro_insn_table.init_entries;
|
|
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
|
|
if (CGEN_INSN_RX ((insns)))
|
|
regfree (CGEN_INSN_RX (insns));
|
|
}
|
|
|
|
if (cd->insn_table.init_entries)
|
|
{
|
|
insns = cd->insn_table.init_entries;
|
|
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
|
|
if (CGEN_INSN_RX (insns))
|
|
regfree (CGEN_INSN_RX (insns));
|
|
}
|
|
|
|
if (cd->macro_insn_table.init_entries)
|
|
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
|
|
|
|
if (cd->insn_table.init_entries)
|
|
free ((CGEN_INSN *) cd->insn_table.init_entries);
|
|
|
|
if (cd->hw_table.entries)
|
|
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
|
|
|
|
if (cd->operand_table.entries)
|
|
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
|
|
|
|
free (cd);
|
|
}
|
|
|