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217 lines
7.7 KiB
Plaintext
217 lines
7.7 KiB
Plaintext
2017-03-02 Tristan Gingold <gingold@adacore.com>
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* configure: Regenerate.
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2017-02-28 Alan Modra <amodra@gmail.com>
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* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
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2017-02-28 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
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(md_apply_fix): Remove fx_subsy check. Move code converting to
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pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
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emiiting errors on seeing fx_pcrel set on unexpected relocs, as
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that is done now by the generic code via..
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* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
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(TC_VALIDATE_FIX_SUB): Define.
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2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
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* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
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to be used with SVE registers.
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(parse_operands): Handle new SVE operands.
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(aarch64_features): Make "sve" require F16 rather than FP. Also
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require COMPNUM.
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* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
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Include compnum tests.
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* testsuite/gas/aarch64/sve.d: Update accordingly.
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* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
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* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
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update expected output for new FMOV and MOV alternatives.
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2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Add a "compnum" entry.
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* config/tc-aarch64.c (aarch64_features): Likewise,
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* testsuite/gas/aarch64/advsimd-compnum.s: New test.
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* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
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2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
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* testsuite/gas/aarch64/sve-sysreg.s,
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testsuite/gas/aarch64/sve-sysreg.d,
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testsuite/gas/aarch64/sve-sysreg-invalid.d,
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testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
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2017-02-27 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Fix sve entry.
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2017-02-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add rcpc.
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* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.d: This.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.s: This.
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* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
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2017-02-14 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/cell.s: Correct invalid registers.
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* testsuite/gas/ppc/vle-simple-1.s: Likewise.
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* testsuite/gas/ppc/vle-simple-2.s: Likewise.
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2017-02-10 Nicholas Piggin <npiggin@gmail.com>
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* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
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2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
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* config/tc-mips.c (mips_ignore_branch_isa): New variable.
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(options): Add OPTION_IGNORE_BRANCH_ISA and
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OPTION_NO_IGNORE_BRANCH_ISA enum values.
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(md_longopts): Add "mignore-branch-isa" and
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"mno-ignore-branch-isa" options.
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(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
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OPTION_NO_IGNORE_BRANCH_ISA.
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(fix_bad_cross_mode_branch_p): Return FALSE if
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`mips_ignore_branch_isa' has been set.
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(md_show_usage): Add `-mignore-branch-isa' and
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`-mno-ignore-branch-isa'.
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* doc/as.texinfo (Target MIPS options): Add
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`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
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(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
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* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
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`-mno-ignore-branch-isa' options.
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* testsuite/gas/mips/branch-local-ignore-2.d: New test.
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* testsuite/gas/mips/branch-local-ignore-3.d: New test.
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* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
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* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
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* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
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* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
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* testsuite/gas/mips/mips.exp: Run the new tests.
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2017-01-30 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/branch-local-2.d: New test.
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* testsuite/gas/mips/branch-local-3.d: New test.
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* testsuite/gas/mips/branch-local-n32-2.d: New test.
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* testsuite/gas/mips/branch-local-n32-3.d: New test.
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* testsuite/gas/mips/branch-local-n64-2.d: New test.
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* testsuite/gas/mips/branch-local-n64-3.d: New test.
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* testsuite/gas/mips/mips.exp: Fold corresponding list tests
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into the new tests.
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2017-01-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* configure.tgt (riscv*-*-*): Remove em=linux.
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2017-01-18 Maciej W. Rozycki <macro@imgtec.com>
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PR gas/20649
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* config/tc-mips.c (pic_need_relax): Don't check for linkonce
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symbols, remove the `segtype' parameter.
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(mips_frob_file, md_estimate_size_before_relax): Adjust
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accordingly.
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(s_is_linkonce): Add an explanatory comment.
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* testsuite/gas/mips/comdat-reloc.d: New test.
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* testsuite/gas/mips/comdat-reloc.s: New test source.
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* testsuite/gas/mips/mips.exp: Run the new test.
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2017-01-18 Bernhard Rosenkranzer <bero@lindev.ch>
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PR 21059
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* config/bfin-lex.l: Support processing with flex 2.6.3.
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* itbl-lex.l: Likewise.
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2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
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(cpu_noarch): Add noavx512_vpopcntdq.
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* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
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* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
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* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
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* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
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* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
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* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
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* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
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* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
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2017-01-09 Andrew Waterman <andrew@sifive.com>
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* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
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against constants.
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(md_apply_fix): Mark relocations against constants as "done."
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2017-01-09 Andrew Waterman <andrew@sifive.com>
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* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
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against constants.
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(md_apply_fix): Mark relocations against constants as "done."
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2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
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Kito Cheng <kito.cheng@gmail.com>
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* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
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Removed.
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(SDATA_START_SYMBOLS): Likewise.
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2017-01-09 Andrew Waterman <andrew@sifive.com>
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* config/tc-riscv.c (relaxed_branch_length): Use the long
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sequence when the target is a weak symbol.
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add rcpc.
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* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.d: This.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.s: This.
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* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
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2017-01-04 Norm Jacobs <norm.jacobs@oracle.com>
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PR gas/20992
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* configure.tgt: Treat sparcv9 as sparc64.
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
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extension.
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(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
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enabled and no other ABI is specified.
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2017-01-03 Dimitar Dimitrov <dimitar@dinux.eu>
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* config/tc-pru.c (md_number_to_chars): Fix parameter to be
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valueT, as declared in tc.h.
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(md_apply_fix): Fix to work on 32-bit hosts.
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>>>>>>> 0115611... RISC-V/GAS: Correct branch relaxation for weak symbols.
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2017-01-02 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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For older changes see ChangeLog-2016
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Copyright (C) 2017 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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