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467 lines
12 KiB
C
467 lines
12 KiB
C
/* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_OPC_H
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#define OPCODES_AARCH64_OPC_H
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#include <string.h>
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#include "opcode/aarch64.h"
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/* Instruction fields.
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Keep synced with fields. */
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enum aarch64_field_kind
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{
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FLD_NIL,
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FLD_cond2,
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FLD_nzcv,
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FLD_defgh,
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FLD_abc,
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FLD_imm19,
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FLD_immhi,
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FLD_immlo,
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FLD_size,
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FLD_vldst_size,
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FLD_op,
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FLD_Q,
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FLD_Rt,
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FLD_Rd,
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FLD_Rn,
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FLD_Rt2,
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FLD_Ra,
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FLD_op2,
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FLD_CRm,
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FLD_CRn,
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FLD_op1,
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FLD_op0,
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FLD_imm3,
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FLD_cond,
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FLD_opcode,
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FLD_cmode,
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FLD_asisdlso_opcode,
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FLD_len,
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FLD_Rm,
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FLD_Rs,
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FLD_option,
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FLD_S,
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FLD_hw,
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FLD_opc,
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FLD_opc1,
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FLD_shift,
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FLD_type,
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FLD_ldst_size,
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FLD_imm6,
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FLD_imm4,
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FLD_imm5,
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FLD_imm7,
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FLD_imm8,
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FLD_imm9,
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FLD_imm12,
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FLD_imm14,
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FLD_imm16,
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FLD_imm26,
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FLD_imms,
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FLD_immr,
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FLD_immb,
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FLD_immh,
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FLD_S_imm10,
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FLD_N,
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FLD_index,
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FLD_index2,
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FLD_sf,
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FLD_lse_sz,
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FLD_H,
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FLD_L,
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FLD_M,
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FLD_b5,
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FLD_b40,
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FLD_scale,
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FLD_SVE_M_4,
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FLD_SVE_M_14,
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FLD_SVE_M_16,
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FLD_SVE_N,
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FLD_SVE_Pd,
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FLD_SVE_Pg3,
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FLD_SVE_Pg4_5,
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FLD_SVE_Pg4_10,
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FLD_SVE_Pg4_16,
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FLD_SVE_Pm,
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FLD_SVE_Pn,
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FLD_SVE_Pt,
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FLD_SVE_Rm,
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FLD_SVE_Rn,
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FLD_SVE_Vd,
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FLD_SVE_Vm,
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FLD_SVE_Vn,
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FLD_SVE_Za_5,
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FLD_SVE_Za_16,
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FLD_SVE_Zd,
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FLD_SVE_Zm_5,
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FLD_SVE_Zm_16,
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FLD_SVE_Zn,
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FLD_SVE_Zt,
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FLD_SVE_i1,
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FLD_SVE_i3h,
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FLD_SVE_imm3,
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FLD_SVE_imm4,
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FLD_SVE_imm5,
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FLD_SVE_imm5b,
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FLD_SVE_imm6,
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FLD_SVE_imm7,
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FLD_SVE_imm8,
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FLD_SVE_imm9,
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FLD_SVE_immr,
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FLD_SVE_imms,
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FLD_SVE_msz,
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FLD_SVE_pattern,
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FLD_SVE_prfop,
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FLD_SVE_rot1,
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FLD_SVE_rot2,
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FLD_SVE_sz,
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FLD_SVE_tsz,
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FLD_SVE_tszh,
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FLD_SVE_tszl_8,
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FLD_SVE_tszl_19,
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FLD_SVE_xs_14,
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FLD_SVE_xs_22,
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FLD_rotate1,
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FLD_rotate2,
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FLD_rotate3,
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};
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/* Field description. */
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struct aarch64_field
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{
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int lsb;
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int width;
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};
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typedef struct aarch64_field aarch64_field;
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extern const aarch64_field fields[];
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/* Operand description. */
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struct aarch64_operand
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{
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enum aarch64_operand_class op_class;
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/* Name of the operand code; used mainly for the purpose of internal
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debugging. */
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const char *name;
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unsigned int flags;
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/* The associated instruction bit-fields; no operand has more than 4
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bit-fields */
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enum aarch64_field_kind fields[4];
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/* Brief description */
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const char *desc;
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};
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typedef struct aarch64_operand aarch64_operand;
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extern const aarch64_operand aarch64_operands[];
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/* Operand flags. */
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#define OPD_F_HAS_INSERTER 0x00000001
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#define OPD_F_HAS_EXTRACTOR 0x00000002
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#define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
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#define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
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value by 2 to get the value
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of an immediate operand. */
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#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
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#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
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#define OPD_F_OD_LSB 5
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#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
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static inline bfd_boolean
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operand_has_inserter (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
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}
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static inline bfd_boolean
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operand_has_extractor (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
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}
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static inline bfd_boolean
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operand_need_sign_extension (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
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}
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static inline bfd_boolean
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operand_need_shift_by_two (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
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}
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static inline bfd_boolean
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operand_maybe_stack_pointer (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
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}
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/* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
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static inline unsigned int
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get_operand_specific_data (const aarch64_operand *operand)
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{
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return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
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}
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/* Return the width of field number N of operand *OPERAND. */
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static inline unsigned
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get_operand_field_width (const aarch64_operand *operand, unsigned n)
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{
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assert (operand->fields[n] != FLD_NIL);
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return fields[operand->fields[n]].width;
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}
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/* Return the total width of the operand *OPERAND. */
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static inline unsigned
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get_operand_fields_width (const aarch64_operand *operand)
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{
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int i = 0;
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unsigned width = 0;
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while (operand->fields[i] != FLD_NIL)
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width += fields[operand->fields[i++]].width;
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assert (width > 0 && width < 32);
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return width;
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}
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static inline const aarch64_operand *
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get_operand_from_code (enum aarch64_opnd code)
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{
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return aarch64_operands + code;
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}
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/* Operand qualifier and operand constraint checking. */
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int aarch64_match_operands_constraint (aarch64_inst *,
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aarch64_operand_error *);
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/* Operand qualifier related functions. */
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const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
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unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
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aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
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int aarch64_find_best_match (const aarch64_inst *,
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const aarch64_opnd_qualifier_seq_t *,
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int, aarch64_opnd_qualifier_t *);
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static inline void
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reset_operand_qualifier (aarch64_inst *inst, int idx)
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{
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assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
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inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
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}
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/* Inline functions operating on instruction bit-field(s). */
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/* Generate a mask that has WIDTH number of consecutive 1s. */
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static inline aarch64_insn
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gen_mask (int width)
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{
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return ((aarch64_insn) 1 << width) - 1;
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}
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/* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
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static inline int
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gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
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{
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const aarch64_field *field = &fields[kind];
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if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
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return 0;
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ret->lsb = field->lsb + lsb_rel;
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ret->width = width;
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return 1;
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}
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/* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
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of the opcode. */
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static inline void
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insert_field_2 (const aarch64_field *field, aarch64_insn *code,
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aarch64_insn value, aarch64_insn mask)
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{
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assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
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&& field->lsb + field->width <= 32);
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value &= gen_mask (field->width);
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value <<= field->lsb;
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/* In some opcodes, field can be part of the base opcode, e.g. the size
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field in FADD. The following helps avoid corrupt the base opcode. */
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value &= ~mask;
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*code |= value;
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}
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/* Extract FIELD of CODE and return the value. MASK can be zero or the base
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mask of the opcode. */
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static inline aarch64_insn
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extract_field_2 (const aarch64_field *field, aarch64_insn code,
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aarch64_insn mask)
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{
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aarch64_insn value;
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/* Clear any bit that is a part of the base opcode. */
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code &= ~mask;
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value = (code >> field->lsb) & gen_mask (field->width);
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return value;
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}
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/* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
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of the opcode. */
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static inline void
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insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
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aarch64_insn value, aarch64_insn mask)
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{
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insert_field_2 (&fields[kind], code, value, mask);
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}
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/* Extract field KIND of CODE and return the value. MASK can be zero or the
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base mask of the opcode. */
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static inline aarch64_insn
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extract_field (enum aarch64_field_kind kind, aarch64_insn code,
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aarch64_insn mask)
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{
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return extract_field_2 (&fields[kind], code, mask);
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}
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extern aarch64_insn
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extract_fields (aarch64_insn code, aarch64_insn mask, ...);
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/* Inline functions selecting operand to do the encoding/decoding for a
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certain instruction bit-field. */
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/* Select the operand to do the encoding/decoding of the 'sf' field.
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The heuristic-based rule is that the result operand is respected more. */
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static inline int
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select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
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{
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int idx = -1;
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if (aarch64_get_operand_class (opcode->operands[0])
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== AARCH64_OPND_CLASS_INT_REG)
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/* normal case. */
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idx = 0;
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else if (aarch64_get_operand_class (opcode->operands[1])
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== AARCH64_OPND_CLASS_INT_REG)
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/* e.g. float2fix. */
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idx = 1;
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else
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{ assert (0); abort (); }
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return idx;
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}
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/* Select the operand to do the encoding/decoding of the 'type' field in
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the floating-point instructions.
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The heuristic-based rule is that the source operand is respected more. */
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static inline int
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select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
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{
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int idx;
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if (aarch64_get_operand_class (opcode->operands[1])
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== AARCH64_OPND_CLASS_FP_REG)
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/* normal case. */
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idx = 1;
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else if (aarch64_get_operand_class (opcode->operands[0])
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== AARCH64_OPND_CLASS_FP_REG)
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/* e.g. float2fix. */
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idx = 0;
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else
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{ assert (0); abort (); }
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return idx;
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}
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/* Select the operand to do the encoding/decoding of the 'size' field in
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the AdvSIMD scalar instructions.
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The heuristic-based rule is that the destination operand is respected
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more. */
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static inline int
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select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
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{
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int src_size = 0, dst_size = 0;
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if (aarch64_get_operand_class (opcode->operands[0])
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== AARCH64_OPND_CLASS_SISD_REG)
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dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
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if (aarch64_get_operand_class (opcode->operands[1])
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== AARCH64_OPND_CLASS_SISD_REG)
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src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
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if (src_size == dst_size && src_size == 0)
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{ assert (0); abort (); }
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/* When the result is not a sisd register or it is a long operantion. */
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if (dst_size == 0 || dst_size == src_size << 1)
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return 1;
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else
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return 0;
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}
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/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
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the AdvSIMD instructions. */
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int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
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/* Miscellaneous. */
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aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
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enum aarch64_modifier_kind
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aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
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bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
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bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
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int aarch64_shrink_expanded_imm8 (uint64_t);
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/* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
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static inline void
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copy_operand_info (aarch64_inst *inst, int dst, int src)
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{
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assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
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&& src < AARCH64_MAX_OPND_NUM);
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memcpy (&inst->operands[dst], &inst->operands[src],
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sizeof (aarch64_opnd_info));
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inst->operands[dst].idx = dst;
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}
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/* A primitive log caculator. */
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static inline unsigned int
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get_logsz (unsigned int size)
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{
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const unsigned char ls[16] =
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{0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
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if (size > 16)
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{
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assert (0);
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return -1;
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}
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assert (ls[size - 1] != (unsigned char)-1);
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return ls[size - 1];
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}
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#endif /* OPCODES_AARCH64_OPC_H */
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