2021-10-26 17:00:04 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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2022-01-22 03:36:31 +00:00
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Copyright (C) 2018-22 divingkatae and maximum
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2021-10-26 17:00:04 +00:00
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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2022-01-22 03:36:31 +00:00
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/** @file NCR53C94/Am53CF94 SCSI controller definitions. */
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2021-10-26 17:00:04 +00:00
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/* NOTE: Power Macintosh computers don't have a real NCR 53C94 chip.
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2022-01-22 03:36:31 +00:00
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The corresponding functionality is provided by the 53CF94 compatible
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2021-10-26 17:00:04 +00:00
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cell in the custom Curio IC (Am79C950).
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*/
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2022-01-22 03:36:31 +00:00
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#ifndef SC_53C94_H
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#define SC_53C94_H
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2021-10-26 17:00:04 +00:00
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#include <cinttypes>
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2022-01-22 03:36:31 +00:00
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/** 53C94 read registers */
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2021-10-26 17:00:04 +00:00
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namespace Read {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Status = 4,
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Interrupt = 5,
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Seq_Step = 6,
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FIFO_Flags = 7,
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Config_1 = 8,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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2021-10-26 17:00:04 +00:00
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};
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};
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2022-01-22 03:36:31 +00:00
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/** 53C94 write registers */
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namespace Write {
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enum Reg53C94 : uint8_t {
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Xfer_Cnt_LSB = 0,
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Xfer_Cnt_MSB = 1,
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FIFO = 2,
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Command = 3,
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Dest_Bus_ID = 4,
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Sel_Timeout = 5,
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Synch_Period = 6,
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Synch_Offset = 7,
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Config_1 = 8,
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Clock_Factor = 9,
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Test_Mode = 0xA,
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Config_2 = 0xB,
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Config_3 = 0xC,
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Config_4 = 0xD, // Am53CF94 extension
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Xfer_Cnt_Hi = 0xE, // Am53CF94 extension
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Data_Align = 0xF
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};
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};
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2022-01-22 03:36:31 +00:00
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enum {
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CMD_NOP = 0,
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CMD_CLEAR_FIFO = 1,
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CMD_RESET_DEVICE = 2,
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CMD_RESET_BUS = 3,
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CMD_DMA_STOP = 4,
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};
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enum {
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CFG2_ENF = 0x40, // Am53CF94: enable features (ENF) bit
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};
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class Sc53C94 {
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public:
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Sc53C94(uint8_t chip_id=12) { this->chip_id = chip_id; };
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~Sc53C94() = default;
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2022-01-22 03:36:31 +00:00
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// 53C94 registers access
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uint8_t read(uint8_t reg_offset);
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void write(uint8_t reg_offset, uint8_t value);
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2022-01-22 03:36:31 +00:00
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protected:
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void reset_device();
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void add_command(uint8_t cmd);
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2021-10-26 17:00:04 +00:00
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private:
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uint8_t chip_id;
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bool on_reset = false;
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uint32_t xfer_count;
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uint32_t set_xfer_count;
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uint8_t sel_timeout;
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uint8_t clk_factor;
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uint8_t config1;
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uint8_t config2;
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uint8_t config3;
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};
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2022-01-22 03:36:31 +00:00
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#endif // SC_53C94_H
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