2020-01-05 17:38:32 +00:00
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//DingusPPC
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//Written by divingkatae and maximum
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//(c)2018-20 (theweirdo) spatium
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2019-07-02 02:15:33 +00:00
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//Please ask for permission
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//if you want to distribute this.
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2020-01-05 17:38:32 +00:00
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//(divingkatae#1017 or powermax#2286 on Discord)
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2019-07-02 02:15:33 +00:00
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2019-08-21 06:33:01 +00:00
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/** MPC106 (Grackle) emulation
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Author: Max Poliakovski
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*/
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2019-07-02 02:15:33 +00:00
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#include <iostream>
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#include <cstring>
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#include <cinttypes>
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2019-08-21 06:33:01 +00:00
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2020-01-03 15:08:00 +00:00
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#include "memreadwrite.h"
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2019-08-21 06:33:01 +00:00
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#include "memctrlbase.h"
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#include "mmiodevice.h"
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2019-07-02 02:15:33 +00:00
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#include "mpc106.h"
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2019-07-15 00:05:10 +00:00
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2019-08-23 19:30:30 +00:00
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MPC106::MPC106() : MemCtrlBase("Grackle"), PCIDevice("Grackle PCI host bridge")
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2019-07-15 00:05:10 +00:00
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{
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2019-08-21 06:33:01 +00:00
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/* add memory mapped I/O region for MPC106 registers */
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add_mmio_region(0xFEC00000, 0x300000, this);
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2019-08-23 19:30:30 +00:00
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this->pci_0_bus.clear();
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2019-07-02 02:15:33 +00:00
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}
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2019-08-21 06:33:01 +00:00
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MPC106::~MPC106()
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{
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2019-08-23 19:30:30 +00:00
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this->pci_0_bus.clear();
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2019-08-21 06:33:01 +00:00
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}
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2019-07-12 05:27:14 +00:00
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2019-08-21 06:33:01 +00:00
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uint32_t MPC106::read(uint32_t offset, int size)
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{
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if (offset >= 0x200000) {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_read(size);
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2019-07-07 06:10:32 +00:00
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}
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2019-08-21 06:33:01 +00:00
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/* FIXME: reading from CONFIG_ADDR is ignored for now */
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2019-07-07 06:10:32 +00:00
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return 0;
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2019-07-02 02:15:33 +00:00
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}
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2019-08-21 06:33:01 +00:00
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void MPC106::write(uint32_t offset, uint32_t value, int size)
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{
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if (offset < 0x200000) {
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this->config_addr = value;
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} else {
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if (this->config_addr & 0x80) // process only if bit E (enable) is set
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return pci_write(value, size);
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2019-07-07 06:10:32 +00:00
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}
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2019-07-15 00:05:10 +00:00
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}
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2019-08-21 06:33:01 +00:00
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uint32_t MPC106::pci_read(uint32_t size)
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{
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2019-08-23 19:30:30 +00:00
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int bus_num, dev_num, fun_num, reg_offs;
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2019-07-15 00:05:10 +00:00
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2019-08-21 06:33:01 +00:00
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bus_num = (this->config_addr >> 8) & 0xFF;
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if (bus_num) {
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std::cout << this->name << " err: read attempt from non-local PCI bus, "
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<< "config_addr = " << std::hex << this->config_addr << std::endl;
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return 0;
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}
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2019-07-15 00:05:10 +00:00
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2019-08-23 19:30:30 +00:00
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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2019-07-15 00:05:10 +00:00
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2019-08-21 06:33:01 +00:00
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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2019-08-23 19:30:30 +00:00
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return this->pci_cfg_read(reg_offs, size);
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2019-08-21 06:33:01 +00:00
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} else {
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2019-08-23 19:30:30 +00:00
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if (this->pci_0_bus.count(dev_num)) {
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return this->pci_0_bus[dev_num]->pci_cfg_read(reg_offs, size);
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} else {
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std::cout << this->name << " err: read attempt from non-existing PCI device "
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<< dev_num << std::endl;
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return 0;
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}
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2019-08-21 06:33:01 +00:00
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}
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2019-07-15 00:05:10 +00:00
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2019-08-21 06:33:01 +00:00
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return 0;
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2019-07-15 00:05:10 +00:00
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}
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2019-08-21 06:33:01 +00:00
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void MPC106::pci_write(uint32_t value, uint32_t size)
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{
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2019-08-23 19:30:30 +00:00
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int bus_num, dev_num, fun_num, reg_offs;
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2019-07-15 00:05:10 +00:00
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2019-08-21 06:33:01 +00:00
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bus_num = (this->config_addr >> 8) & 0xFF;
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if (bus_num) {
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std::cout << this->name << " err: write attempt to non-local PCI bus, "
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<< "config_addr = " << std::hex << this->config_addr << std::endl;
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return;
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2019-07-15 00:05:10 +00:00
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}
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2019-07-02 02:15:33 +00:00
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2019-08-23 19:30:30 +00:00
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dev_num = (this->config_addr >> 19) & 0x1F;
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fun_num = (this->config_addr >> 16) & 0x07;
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reg_offs = (this->config_addr >> 24) & 0xFC;
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2019-07-02 02:15:33 +00:00
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2019-08-21 06:33:01 +00:00
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if (dev_num == 0 && fun_num == 0) { // dev_num 0 is assigned to myself
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2019-08-23 19:30:30 +00:00
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this->pci_cfg_write(reg_offs, value, size);
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2019-08-21 06:33:01 +00:00
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} else {
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2019-08-23 19:30:30 +00:00
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if (this->pci_0_bus.count(dev_num)) {
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this->pci_0_bus[dev_num]->pci_cfg_write(reg_offs, value, size);
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} else {
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std::cout << this->name << " err: write attempt to non-existing PCI device "
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<< dev_num << std::endl;
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}
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2019-08-21 06:33:01 +00:00
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}
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2019-07-02 02:15:33 +00:00
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}
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2019-08-23 19:30:30 +00:00
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uint32_t MPC106::pci_cfg_read(uint32_t reg_offs, uint32_t size)
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2019-08-21 06:33:01 +00:00
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{
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#ifdef MPC106_DEBUG
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2019-08-23 19:30:30 +00:00
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printf("read from Grackle register %08X\n", reg_offs);
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2019-08-21 06:33:01 +00:00
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#endif
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2019-07-02 02:15:33 +00:00
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2019-08-21 06:33:01 +00:00
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switch(size) {
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case 1:
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2019-08-23 19:30:30 +00:00
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return this->my_pci_cfg_hdr[reg_offs];
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2019-08-21 06:33:01 +00:00
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break;
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case 2:
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2020-01-13 02:04:06 +00:00
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return READ_WORD_BE_A(&this->my_pci_cfg_hdr[reg_offs]);
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2019-08-21 06:33:01 +00:00
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break;
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case 4:
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2020-01-13 02:04:06 +00:00
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return READ_DWORD_BE_A(&this->my_pci_cfg_hdr[reg_offs]);
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2019-08-21 06:33:01 +00:00
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break;
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default:
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std::cout << "MPC106 read error: invalid size parameter " << size
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<< std::endl;
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2019-07-15 00:05:10 +00:00
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}
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2019-08-21 06:33:01 +00:00
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return 0;
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2019-07-15 00:05:10 +00:00
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}
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2019-08-23 19:30:30 +00:00
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void MPC106::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size)
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2019-08-21 06:33:01 +00:00
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{
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#ifdef MPC106_DEBUG
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2019-08-23 19:30:30 +00:00
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printf("write %08X to Grackle register %08X\n", value, reg_offs);
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2019-08-21 06:33:01 +00:00
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#endif
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// FIXME: implement write-protection for read-only registers
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switch(size) {
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case 1:
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2019-08-23 19:30:30 +00:00
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this->my_pci_cfg_hdr[reg_offs] = value & 0xFF;
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2019-08-21 06:33:01 +00:00
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break;
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case 2:
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2019-08-23 19:30:30 +00:00
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this->my_pci_cfg_hdr[reg_offs] = (value >> 8) & 0xFF;
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this->my_pci_cfg_hdr[reg_offs+1] = value & 0xFF;
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2019-08-21 06:33:01 +00:00
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break;
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case 4:
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2019-08-23 19:30:30 +00:00
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this->my_pci_cfg_hdr[reg_offs] = (value >> 24) & 0xFF;
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this->my_pci_cfg_hdr[reg_offs+1] = (value >> 16) & 0xFF;
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this->my_pci_cfg_hdr[reg_offs+2] = (value >> 8) & 0xFF;
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this->my_pci_cfg_hdr[reg_offs+3] = value & 0xFF;
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2019-08-21 06:33:01 +00:00
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break;
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default:
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std::cout << "MPC106 read error: invalid size parameter " << size
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<< std::endl;
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2019-07-02 02:15:33 +00:00
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}
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2019-10-07 01:21:01 +00:00
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if (this->my_pci_cfg_hdr[0xF2] & 8) {
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#ifdef MPC106_DEBUG
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std::cout << "MPC106: MCCR1[MEMGO] was set! " << std::endl;
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#endif
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setup_ram();
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}
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2019-07-02 02:15:33 +00:00
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}
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2019-08-23 19:30:30 +00:00
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bool MPC106::pci_register_device(int dev_num, PCIDevice *dev_instance)
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{
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if (this->pci_0_bus.count(dev_num)) // is dev_num already registered?
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return false;
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this->pci_0_bus[dev_num] = dev_instance;
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dev_instance->set_host(this);
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return true;
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}
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bool MPC106::pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIDevice *obj)
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{
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// FIXME: add sanity checks!
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return this->add_mmio_region(start_addr, size, obj);
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}
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2019-10-07 01:21:01 +00:00
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void MPC106::setup_ram()
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{
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uint32_t mem_start, mem_end, ext_mem_start, ext_mem_end, bank_start, bank_end;
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uint32_t ram_size = 0;
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uint8_t bank_en = this->my_pci_cfg_hdr[0xA0];
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for (int bank = 0; bank < 8; bank++) {
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if (bank_en & (1 << bank)) {
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if (bank < 4) {
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2020-01-13 02:04:06 +00:00
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x80]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x88]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x90]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x98]);
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2019-10-07 01:21:01 +00:00
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} else {
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2020-01-13 02:04:06 +00:00
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mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x84]);
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ext_mem_start = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x8C]);
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mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x94]);
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ext_mem_end = READ_DWORD_LE_A(&this->my_pci_cfg_hdr[0x9C]);
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2019-10-07 01:21:01 +00:00
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}
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bank_start = (((ext_mem_start >> bank * 8) & 3) << 30) |
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(((mem_start >> bank * 8) & 0xFF) << 20);
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bank_end = (((ext_mem_end >> bank * 8) & 3) << 30) |
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(((mem_end >> bank * 8) & 0xFF) << 20) | 0xFFFFFUL;
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if (bank && bank_start != ram_size)
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std::cout << "MPC106 error: RAM not contiguous!" << std::endl;
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ram_size += bank_end + 1;
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}
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}
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if (!this->add_ram_region(0, ram_size)) {
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std::cout << "MPC106 RAM allocation failed!" << std::endl;
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}
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}
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