2021-09-30 21:00:56 +00:00
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** @file Apple memory-mapped I/O controller emulation. */
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#ifndef AMIC_H
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#define AMIC_H
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2022-01-10 16:39:24 +00:00
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#include <devices/common/hwinterrupt.h>
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2021-10-23 18:17:47 +00:00
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#include <devices/common/mmiodevice.h>
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2022-01-22 03:36:31 +00:00
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#include <devices/common/scsi/sc53c94.h>
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2021-10-23 18:17:47 +00:00
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#include <devices/common/viacuda.h>
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2021-10-24 19:02:30 +00:00
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#include <devices/ethernet/mace.h>
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2021-12-12 20:40:04 +00:00
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#include <devices/floppy/swim3.h>
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2021-10-25 20:19:27 +00:00
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#include <devices/serial/escc.h>
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2021-10-23 18:17:47 +00:00
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#include <devices/sound/awacs.h>
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2021-11-30 00:26:32 +00:00
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#include <devices/video/displayid.h>
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2021-12-07 21:48:33 +00:00
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#include <devices/video/pdmonboard.h>
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2021-10-23 18:17:47 +00:00
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2021-09-30 21:00:56 +00:00
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#include <cinttypes>
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#include <memory>
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2022-01-10 16:39:24 +00:00
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/** Interrupt related constants. */
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#define AMIC_INT_CLR 0x80 // clears CPU interrupt
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#define AMIC_INT_MODE 0x40 // interrupt mode: 0 - native, 1 - 68k-style
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2021-10-04 21:46:19 +00:00
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/** AMIC sound buffers are located at fixed offsets from DMA base. */
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#define AMIC_SND_BUF0_OFFS 0x10000
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#define AMIC_SND_BUF1_OFFS 0x12000
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// PDM HWInit source defines two constants: kExpBit = 0x80 and kCmdBit = 0x40
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// I don't know what they mean but it seems that their combination will
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// cause sound control parameters to be transferred to the sound chip.
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#define PDM_SND_CTRL_VALID 0xC0
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#define PDM_DMA_IF1 0x80 // DMA interrupt flag => buffer 1 drained
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#define PDM_DMA_IF0 0x40 // DMA interrupt flag => buffer 0 drained
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#define PDM_DMA_INTS_MASK 0xF0 // mask for clearing all interrupt flags
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/** AMIC-specific sound output DMA implementation. */
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class AmicSndOutDma : public DmaOutChannel {
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public:
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AmicSndOutDma();
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~AmicSndOutDma() = default;
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bool is_active();
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void init(uint32_t buf_base, uint32_t buf_samples);
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void enable() { this->enabled = true; };
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void disable() { this->enabled = false; };
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uint8_t read_stat();
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void write_dma_out_ctrl(uint8_t value);
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uint32_t get_cur_buf_pos() { return this->cur_buf_pos; };
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DmaPullResult pull_data(uint32_t req_len, uint32_t *avail_len,
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uint8_t **p_data);
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private:
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bool enabled;
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uint8_t dma_out_ctrl;
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uint32_t out_buf0;
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uint32_t out_buf1;
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uint32_t out_buf_len;
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uint32_t snd_buf_num;
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uint32_t cur_buf_pos;
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};
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2022-02-13 22:47:45 +00:00
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// macro for byte wise updating of AMIC DMA address registers
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#define SET_ADDR_BYTE(reg, offset, value) \
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mask = 0xFF000000UL >> (8 * ((offset) & 3)); \
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(reg) = ((reg) & ~mask) | (((value) & 0xFF) << (8 * (3 - ((offset) & 3))));
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// macro for byte wise updating of AMIC DMA size registers
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#define SET_SIZE_BYTE(reg, offset, value) \
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mask = 0xFF00U >> (8 * ((offset) & 1)); \
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(reg) = ((reg) & ~mask) | (((value) & 0xFF) << (8 * (((offset) & 1) ^ 1)));
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2021-10-04 21:46:19 +00:00
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/* AMIC registers offsets from AMIC base (0x50F00000). */
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enum AMICReg : uint32_t {
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// Sound control registers
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Snd_Ctrl_0 = 0x14000, // audio codec control register 0
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Snd_Ctrl_1 = 0x14001, // audio codec control register 1
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Snd_Ctrl_2 = 0x14002, // audio codec control register 2
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Snd_Stat_0 = 0x14004, // audio codec status register 0
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Snd_Stat_1 = 0x14005, // audio codec status register 1
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Snd_Stat_2 = 0x14006, // audio codec status register 2
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Snd_Buf_Size_Hi = 0x14008, // sound buffer size, high-order byte
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Snd_Buf_Size_Lo = 0x14009, // sound buffer size, low-order byte
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Snd_Phase0 = 0x1400C, // high-order byte of the sound phase register
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Snd_Phase1 = 0x1400D, // middle byte of the sound phase register
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Snd_Phase2 = 0x1400E, // low-order byte of the sound phase register
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Snd_Out_Ctrl = 0x14010, // audio codec output control register
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Snd_In_Ctrl = 0x14011, // audio codec input control register
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Snd_In_DMA = 0x14014, // sound input DMA status/control register
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Snd_Out_DMA = 0x14018, // sound output DMA status/control register
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2021-12-07 21:48:33 +00:00
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// Video DAC (Ariel II) control registers
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Ariel_Clut_Index = 0x24000,
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Ariel_Clut_Color = 0x24001,
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Ariel_Config = 0x24002,
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2022-02-06 00:47:54 +00:00
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// VIA2 registers
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VIA2_IFR = 0x26003,
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VIA2_Slot_IER = 0x26012,
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VIA2_IER = 0x26013,
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VIA2_IFR_RBV = 0x27A03, // RBV-compatible mirror for the VIA2_IFR
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VIA2_IER_RBV = 0x27C13, // RBV-compatible mirror for the VIA2_IER
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2021-09-30 21:00:56 +00:00
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// Video control registers
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Video_Mode = 0x28000,
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Pixel_Depth = 0x28001,
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Monitor_Id = 0x28002,
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2022-01-10 16:39:24 +00:00
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// Interrupt registers
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Int_Ctrl = 0x2A000,
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2021-10-10 19:56:04 +00:00
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// Undocumented diagnostics register
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Diag_Reg = 0x2C000,
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2021-09-30 21:00:56 +00:00
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// DMA control registers
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DMA_Base_Addr_0 = 0x31000,
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DMA_Base_Addr_1 = 0x31001,
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DMA_Base_Addr_2 = 0x31002,
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DMA_Base_Addr_3 = 0x31003,
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Enet_DMA_Xmt_Ctrl = 0x31C20,
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SCSI_DMA_Ctrl = 0x32008,
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Enet_DMA_Rcv_Ctrl = 0x32028,
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2022-02-13 22:47:45 +00:00
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// Floppy (SWIM3) DMA registers
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Floppy_Addr_Ptr_0 = 0x32060,
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Floppy_Addr_Ptr_1 = 0x32061,
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Floppy_Addr_Ptr_2 = 0x32062,
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Floppy_Addr_Ptr_3 = 0x32063,
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Floppy_Byte_Cnt_Hi = 0x32064,
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Floppy_Byte_Cnt_Lo = 0x32065,
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Floppy_DMA_Ctrl = 0x32068,
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2021-10-04 21:46:19 +00:00
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SCC_DMA_Xmt_A_Ctrl = 0x32088,
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SCC_DMA_Rcv_A_Ctrl = 0x32098,
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SCC_DMA_Xmt_B_Ctrl = 0x320A8,
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SCC_DMA_Rcv_B_Ctrl = 0x320B8,
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2021-09-30 21:00:56 +00:00
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};
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2021-10-04 21:46:19 +00:00
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/** Apple Memory-mapped I/O controller device. */
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2022-01-10 16:39:24 +00:00
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class AMIC : public MMIODevice, public InterruptCtrl {
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public:
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AMIC();
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~AMIC() = default;
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2022-01-21 11:40:26 +00:00
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// HWComponent methods
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int device_postinit();
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2021-09-30 21:00:56 +00:00
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/* MMIODevice methods */
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uint32_t read(uint32_t reg_start, uint32_t offset, int size);
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void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
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2022-01-10 16:39:24 +00:00
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// InterruptCtrl methods
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uint32_t register_dev_int(IntSrc src_id);
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uint32_t register_dma_int(IntSrc src_id);
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void ack_int(uint32_t irq_id, uint8_t irq_line_state);
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void ack_dma_int(uint32_t irq_id, uint8_t irq_line_state);
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2022-02-06 00:47:54 +00:00
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protected:
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void ack_via2_int(uint32_t irq_id, uint8_t irq_line_state);
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void ack_cpu_int(uint32_t irq_id, uint8_t irq_line_state);
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2022-02-13 22:47:45 +00:00
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void reset_floppy_dma();
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2022-02-06 00:47:54 +00:00
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2021-09-30 21:00:56 +00:00
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private:
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2021-09-30 23:02:43 +00:00
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uint8_t imm_snd_regs[4]; // temporary storage for sound control registers
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2022-02-13 22:47:45 +00:00
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uint32_t dma_base = 0; // DMA physical base address
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uint16_t snd_buf_size = 0; // sound buffer size in bytes
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2021-10-04 21:46:19 +00:00
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uint8_t snd_out_ctrl = 0;
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2022-02-13 22:47:45 +00:00
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// floppy DMA state
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uint32_t floppy_addr_ptr;
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uint16_t floppy_byte_cnt;
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uint8_t floppy_dma_cs; // floppy DMA control/status value
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uint8_t scsi_dma_cs = 0; // SCSI DMA control/status register value
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2021-10-13 07:06:16 +00:00
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2022-01-10 16:39:24 +00:00
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uint8_t int_ctrl = 0;
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uint8_t dev_irq_lines = 0; // state of the IRQ lines
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2022-02-06 00:47:54 +00:00
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// pseudo VIA2 state
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uint8_t via2_ier = 0;
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uint8_t via2_ifr = 0;
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uint8_t via2_irq = 0;
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2022-01-21 11:40:26 +00:00
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uint32_t pseudo_vbl_tid; // ID for the pseudo-VBL timer
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2021-10-25 20:19:27 +00:00
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// AMIC subdevices instances
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2022-01-22 03:36:31 +00:00
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std::unique_ptr<Sc53C94> scsi;
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2021-10-25 20:19:27 +00:00
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std::unique_ptr<EsccController> escc;
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2021-10-24 19:02:30 +00:00
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std::unique_ptr<MaceController> mace;
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2021-09-30 23:02:43 +00:00
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std::unique_ptr<ViaCuda> viacuda;
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std::unique_ptr<AwacDevicePdm> awacs;
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2021-10-04 21:46:19 +00:00
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std::unique_ptr<AmicSndOutDma> snd_out_dma;
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2021-11-30 00:26:32 +00:00
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// on-board video
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std::unique_ptr<DisplayID> disp_id;
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2021-12-07 21:48:33 +00:00
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std::unique_ptr<PdmOnboardVideo> def_vid;
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2021-11-30 00:26:32 +00:00
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uint8_t mon_id;
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2021-12-12 20:40:04 +00:00
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std::unique_ptr<Swim3::Swim3Ctrl> swim3;
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2021-09-30 21:00:56 +00:00
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};
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#endif // AMIC_H
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