mirror of
https://github.com/dingusdev/dingusppc.git
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81 lines
3.0 KiB
C
81 lines
3.0 KiB
C
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_BRIDGE_BASE_H
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#define PCI_BRIDGE_BASE_H
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#include <devices/deviceregistry.h>
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#include <devices/common/pci/pcibase.h>
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#include <devices/common/pci/pcihost.h>
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#include <cinttypes>
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#include <string>
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#include <unordered_map>
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#include <vector>
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/** PCI configuration space registers offsets (type 1 and 2) */
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enum {
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PCI_CFG_PRIMARY_BUS = 0x18, // PRIMARY_BUS, SECONDARY_BUS, SUBORDINATE_BUS, SEC_LATENCY_TIMER
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};
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class PCIBridgeBase : public PCIHost, public PCIBase {
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friend class PCIHost;
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public:
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PCIBridgeBase(std::string name, PCIHeaderType hdr_type, int num_bars);
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~PCIBridgeBase() = default;
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// PCIHost methods
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virtual bool pci_register_mmio_region(uint32_t start_addr, uint32_t size, PCIBase* obj);
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virtual bool pci_unregister_mmio_region(uint32_t start_addr, uint32_t size, PCIBase* obj);
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// PCIBase methods
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virtual uint32_t pci_cfg_read(uint32_t reg_offs, AccessDetails &details);
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virtual void pci_cfg_write(uint32_t reg_offs, uint32_t value, AccessDetails &details);
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// plugin interface for using in the derived classes
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std::function<uint8_t()> pci_rd_primary_bus;
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std::function<void(uint8_t)> pci_wr_primary_bus;
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std::function<uint8_t()> pci_rd_secondary_bus;
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std::function<void(uint8_t)> pci_wr_secondary_bus;
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std::function<uint8_t()> pci_rd_subordinate_bus;
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std::function<void(uint8_t)> pci_wr_subordinate_bus;
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std::function<uint8_t()> pci_rd_sec_latency_timer;
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std::function<void(uint8_t)> pci_wr_sec_latency_timer;
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std::function<uint16_t()> pci_rd_sec_status;
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std::function<void(uint16_t)> pci_wr_sec_status;
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std::function<uint16_t()> pci_rd_bridge_control;
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std::function<void(uint16_t)> pci_wr_bridge_control;
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protected:
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// PCI configuration space state
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uint8_t primary_bus = 0;
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uint8_t secondary_bus = 0;
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uint8_t subordinate_bus = 0;
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uint8_t sec_latency_timer = 0; // if supportss r/w then must reset to 0
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uint16_t sec_status = 0;
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uint16_t bridge_control = 0;
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// 0 = not writable, 0xf8 = limits the granularity to eight PCI clocks
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uint8_t sec_latency_timer_cfg = 0xff;
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};
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#endif /* PCI_BRIDGE_BASE_H */
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