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https://github.com/dingusdev/dingusppc.git
synced 2024-06-25 23:29:33 +00:00
Implement virtual time based on instruction counting.
This commit is contained in:
Maxim Poliakovski
parent
9a0c340712
commit
087402290d
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@ -148,8 +148,12 @@ SUPERVISOR MODEL
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536 - 543 are the Data BAT registers
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**/
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extern uint32_t opcode_value; // used for interpreting opcodes
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extern uint64_t timebase_counter; // used for storing time base value
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extern uint32_t opcode_value; // used for interpreting opcodes
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extern uint64_t timebase_counter;
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extern uint64_t tbr_wr_timestamp;
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extern uint64_t tbr_wr_value;
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extern uint64_t tbr_freq_hz;
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// Additional steps to prevent overflow?
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extern int32_t add_result;
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@ -206,9 +210,9 @@ enum CR_select : int32_t {
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CR1_field = (0xF << 24),
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};
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enum CRx_bit : uint32_t {
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CR_SO = 28,
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CR_EQ = 29,
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enum CRx_bit : uint32_t {
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CR_SO = 28,
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CR_EQ = 29,
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CR_GT = 30,
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CR_LT = 31 };
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@ -615,6 +619,8 @@ extern void power_srq();
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// G5+ instructions
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extern uint64_t get_virt_time_ns(void);
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extern void ppc_main_opcode(void);
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extern void ppc_exec(void);
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extern void ppc_exec_single(void);
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@ -62,12 +62,19 @@ BB_end_kind bb_kind; /* basic block end */
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uint32_t glob_bb_start_la;
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/* variables related to virtual time */
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uint64_t cycles_count; /* contains number of cycles executed so far */
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uint64_t old_cycles_count; /* previous value for cycles_count */
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uint64_t timebase_counter; /* internal timebase counter */
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uint32_t decr; /* current value of PPC DEC register */
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uint8_t old_decr_msb; /* MSB value for previous DEC value */
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uint8_t tbr_factor; /* cycles_count to TBR freq ratio in 2^x units */
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uint64_t g_icycles;
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int icnt_factor;
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/* global variables related to the timebase facility */
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uint64_t tbr_wr_timestamp; // stores vCPU virtual time of the last TBR write
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uint64_t tbr_wr_value; // last value written to the TBR
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uint64_t tbr_freq_hz; // TBR driving frequency in Hz
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uint64_t cycles_count; // contains number of cycles executed so far */
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uint64_t old_cycles_count; // previous value for cycles_count */
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uint64_t timebase_counter; // internal timebase counter */
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uint32_t decr; // current value of PPC DEC register */
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uint8_t old_decr_msb; // MSB value for previous DEC value */
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uint8_t tbr_factor; // cycles_count to TBR freq ratio in 2^x units */
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#ifdef CPU_PROFILING
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@ -286,8 +293,20 @@ void ppc_main_opcode()
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OpcodeGrabber[(ppc_cur_instruction >> 26) & 0x3F]();
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}
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uint64_t get_virt_time_ns()
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{
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return g_icycles << icnt_factor;
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}
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int process_events()
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{
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// dummy implementation that schedules execution
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// of another 10.000 instructions
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return g_icycles + 10000;
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}
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/** Execute PPC code as long as power is on. */
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#if 0
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void ppc_exec()
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{
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uint32_t bb_start_la, page_start, delta;
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@ -348,8 +367,78 @@ again:
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}
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}
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}
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#else
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// inner interpreter loop
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static void ppc_exec_inner()
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{
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uint64_t max_cycles;
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uint32_t page_start, eb_start, eb_end;
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uint8_t* pc_real;
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max_cycles = 0;
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while (power_on) {
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// define boundaries of the next execution block
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// max execution block length = one memory page
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eb_start = ppc_state.pc;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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//eb_last = false;
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bb_kind = BB_end_kind::BB_NONE;
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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// interpret execution block
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while (ppc_state.pc < eb_end) {
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ppc_main_opcode();
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if (g_icycles++ >= max_cycles) {
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max_cycles = process_events();
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}
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//if (eb_last) {
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if (bb_kind != BB_end_kind::BB_NONE) { // execution block ended ?
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if (!power_on)
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break;
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// check the reason for the block end
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//eb_last = false;
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// define next execution block
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eb_start = ppc_next_instruction_address;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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if ((eb_start & PAGE_MASK) == page_start) {
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pc_real += (int)eb_start - (int)ppc_state.pc;
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ppc_set_cur_instruction(pc_real);
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} else {
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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}
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ppc_state.pc = eb_start;
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bb_kind = BB_end_kind::BB_NONE;
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} else {
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ppc_state.pc += 4;
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pc_real += 4;
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ppc_set_cur_instruction(pc_real);
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}
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}
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}
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}
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// outer interpreter loop
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void ppc_exec()
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{
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if (setjmp(exc_env)) {
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// process low-level exceptions
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//LOG_F(9, "PPC-EXEC: low_level exception raised!");
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ppc_state.pc = ppc_next_instruction_address;
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}
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while (power_on) {
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ppc_exec_inner();
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}
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}
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#endif
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/** Execute one PPC instruction. */
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#if 0
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void ppc_exec_single()
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{
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uint32_t delta;
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@ -383,8 +472,31 @@ void ppc_exec_single()
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timebase_counter++;
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#endif
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}
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#else
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void ppc_exec_single()
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{
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if (setjmp(exc_env)) {
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// process low-level exceptions
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//LOG_F(9, "PPC-EXEC: low_level exception raised!");
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ppc_state.pc = ppc_next_instruction_address;
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bb_kind = BB_end_kind::BB_NONE;
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return;
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}
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mmu_translate_imem(ppc_state.pc);
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ppc_main_opcode();
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if (bb_kind != BB_end_kind::BB_NONE) {
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ppc_state.pc = ppc_next_instruction_address;
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bb_kind = BB_end_kind::BB_NONE;
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} else {
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ppc_state.pc += 4;
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}
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g_icycles++;
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}
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#endif
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/** Execute PPC code until goal_addr is reached. */
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#if 0
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void ppc_exec_until(volatile uint32_t goal_addr)
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{
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uint32_t bb_start_la, page_start, delta;
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@ -411,7 +523,6 @@ void ppc_exec_until(volatile uint32_t goal_addr)
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}
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/* initial MMU translation for the current code page. */
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//pc_real = quickinstruction_translate(bb_start_la);
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pc_real = mmu_translate_imem(bb_start_la);
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/* set current code page limits */
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@ -444,8 +555,77 @@ again:
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}
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}
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}
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#else
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// inner interpreter loop
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static void ppc_exec_until_inner(const uint32_t goal_addr)
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{
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uint64_t max_cycles;
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uint32_t page_start, eb_start, eb_end;
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uint8_t* pc_real;
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max_cycles = 0;
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while (ppc_state.pc != goal_addr) {
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// define boundaries of the next execution block
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// max execution block length = one memory page
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eb_start = ppc_state.pc;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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//eb_last = false;
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bb_kind = BB_end_kind::BB_NONE;
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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// interpret execution block
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while ((ppc_state.pc != goal_addr) && (ppc_state.pc < eb_end)) {
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ppc_main_opcode();
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if (g_icycles++ >= max_cycles) {
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max_cycles = process_events();
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}
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//if (eb_last) {
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if (bb_kind != BB_end_kind::BB_NONE) { // execution block ended ?
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// check the reason for the block end
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//eb_last = false;
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// define next execution block
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eb_start = ppc_next_instruction_address;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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if ((eb_start & PAGE_MASK) == page_start) {
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pc_real += (int)eb_start - (int)ppc_state.pc;
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ppc_set_cur_instruction(pc_real);
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} else {
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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}
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ppc_state.pc = eb_start;
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bb_kind = BB_end_kind::BB_NONE;
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} else {
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ppc_state.pc += 4;
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pc_real += 4;
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ppc_set_cur_instruction(pc_real);
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}
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}
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}
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LOG_F(9, "PPC-EXEC: goal address reached, icycles=%llu", g_icycles);
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}
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// outer interpreter loop
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void ppc_exec_until(volatile uint32_t goal_addr)
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{
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if (setjmp(exc_env)) {
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// process low-level exceptions
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//LOG_F(9, "PPC-EXEC: low_level exception raised!");
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ppc_state.pc = ppc_next_instruction_address;
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}
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while (ppc_state.pc != goal_addr) {
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ppc_exec_until_inner(goal_addr);
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}
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}
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#endif
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/** Execute PPC code until control is reached the specified region. */
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#if 0
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void ppc_exec_dbg(volatile uint32_t start_addr, volatile uint32_t size)
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{
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uint32_t bb_start_la, page_start, delta;
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@ -508,6 +688,75 @@ again:
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}
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}
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}
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#else
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// inner interpreter loop
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static void ppc_exec_dbg_inner(const uint32_t start_addr, const uint32_t size)
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{
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uint64_t max_cycles;
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uint32_t page_start, eb_start, eb_end;
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uint8_t* pc_real;
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max_cycles = 0;
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while (ppc_state.pc < start_addr || ppc_state.pc >= start_addr + size) {
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// define boundaries of the next execution block
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// max execution block length = one memory page
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eb_start = ppc_state.pc;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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//eb_last = false;
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bb_kind = BB_end_kind::BB_NONE;
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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// interpret execution block
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while ((ppc_state.pc < start_addr || ppc_state.pc >= start_addr + size)
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&& (ppc_state.pc < eb_end)) {
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ppc_main_opcode();
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if (g_icycles++ >= max_cycles) {
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max_cycles = process_events();
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}
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//if (eb_last) {
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if (bb_kind != BB_end_kind::BB_NONE) { // execution block ended ?
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// check the reason for the block end
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//eb_last = false;
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// define next execution block
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eb_start = ppc_next_instruction_address;
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eb_end = (eb_start + PAGE_SIZE) & PAGE_MASK;
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if ((eb_start & PAGE_MASK) == page_start) {
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pc_real += (int)eb_start - (int)ppc_state.pc;
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ppc_set_cur_instruction(pc_real);
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} else {
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page_start = eb_start & PAGE_MASK;
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pc_real = mmu_translate_imem(eb_start);
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}
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ppc_state.pc = eb_start;
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bb_kind = BB_end_kind::BB_NONE;
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} else {
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ppc_state.pc += 4;
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pc_real += 4;
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ppc_set_cur_instruction(pc_real);
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}
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}
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}
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LOG_F(9, "PPC-EXEC: goal address reached, icycles=%llu", g_icycles);
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}
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// outer interpreter loop
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void ppc_exec_dbg(volatile uint32_t start_addr, volatile uint32_t size)
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{
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if (setjmp(exc_env)) {
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// process low-level exceptions
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//LOG_F(9, "PPC-EXEC: low_level exception raised!");
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ppc_state.pc = ppc_next_instruction_address;
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}
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while (ppc_state.pc < start_addr || ppc_state.pc >= start_addr + size) {
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ppc_exec_dbg_inner(start_addr, size);
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}
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}
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#endif
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uint64_t instr_count, old_instr_count;
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@ -767,6 +1016,13 @@ void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version) {
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tbr_factor = 4;
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#endif
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// initialize time base facility
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g_icycles = 0;
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icnt_factor = 4;
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tbr_wr_timestamp = 0;
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tbr_wr_value = 0;
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tbr_freq_hz = 16705000; // FIXME: this should be set properly during machine initialization
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timebase_counter = 0;
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decr = 0;
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old_decr_msb = decr >> 31;
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@ -71,6 +71,8 @@ typedef struct PATResult {
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} PATResult;
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#define PAGE_SIZE_BITS 12
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#define PAGE_SIZE (1 << PAGE_SIZE_BITS)
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#define PAGE_MASK ~(PAGE_SIZE - 1)
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#define TLB_SIZE 4096
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#define TLB2_WAYS 4
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#define TLB_INVALID_TAG 0xFFFFFFFF
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