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CPU and memory controller endian changes.
=============== Rairii changes: memctrlbase: The memory controller may have an endian swap mode. mpc106: Only mmio regions need endian swap and only if PCIR_LE_MODE is set. videoctrl: Add framebuffer_in_main_memory flag. Use needs_swap_endian. debugger: Fix disasm for little endian mode. ppcmmu: little endian mode requires munging of the data and instruction addresses, affecting the 3 least significant bits. ppcexec: pc_real is always recalculated during little endian mode because instructions are swapped every 8 bytes (due to the address munging). ============== joevt changes: Add SUPPORTS_MEMORY_CTRL_ENDIAN_MODE for memory controller. Use cmake -DDPPC_SUPPORT_PPC_LE=ON to enable. Add SUPPORTS_PPC_LITTLE_ENDIAN_MODE for CPU. Use cmake -DDPPC_SUPPORT_MEM_LE=ON to enable. Add ppc_change_endian to handle endian switch for MPC601 (uses HID0 instead of MSR) and later PPC CPUs. Add is_LE flag to ppc_state to indicate little endian mode for all processor versions. Create separate ppc_exec_inner template functions for little and big endian. Switch endian mode in the ppc_exec outer functions when power_off_reason is po_endian_switch. Since MPC601 doesn't have ILE and LE bits, remove that code for that CPU. videoctrl: Uses templated methods. See next commit for a fix that this change introduces.
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@@ -430,6 +430,21 @@ static uint32_t disasm(PPCDisasmContext &ctx) {
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cout << COUT08X << ctx.instr_addr;
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cout << ": " << COUT08X << ctx.instr_code;
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cout << " " << disassemble_single(&ctx) << setfill(' ') << right << dec;
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#if SUPPORTS_MEMORY_CTRL_ENDIAN_MODE
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bool needs_swap = false;
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if (mem_ctrl_instance != nullptr)
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needs_swap = mem_ctrl_instance->needs_swap_endian(false);
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#endif
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uint32_t phys_addr;
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uint8_t* real_addr = mmu_translate_imem(ctx.instr_addr, &phys_addr);
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ctx.instr_code =
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#if SUPPORTS_MEMORY_CTRL_ENDIAN_MODE
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needs_swap ? READ_DWORD_LE_A(real_addr) :
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#endif
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READ_DWORD_BE_A(real_addr);
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return ctx.instr_addr;
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}
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