diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..b9a280e
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,78 @@
+Language: Cpp
+
+AccessModifierOffset: -4
+AlignAfterOpenBracket: AlwaysBreak
+AlignConsecutiveAssignments: true
+AlignConsecutiveDeclarations: false
+#AlignConsecutiveMacros: false
+AlignEscapedNewlines: Right
+AlignOperands: false
+AlignTrailingComments: true
+AllowAllArgumentsOnNextLine: true
+AllowAllConstructorInitializersOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: true
+AllowShortBlocksOnASingleLine: false
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: Empty
+AllowShortIfStatementsOnASingleLine: Never
+#AllowShortLambdasOnASingleLine: All
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: true
+AlwaysBreakTemplateDeclarations: Yes
+BinPackArguments: false
+BinPackParameters: false
+BreakBeforeBinaryOperators: None
+BreakBeforeBraces: Attach
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: BeforeComma
+#BreakInheritanceList: BeforeComma
+BreakStringLiterals: true
+ColumnLimit: 100
+CompactNamespaces: true
+ConstructorInitializerAllOnOneLineOrOnePerLine: true
+ConstructorInitializerIndentWidth: 4
+ContinuationIndentWidth: 4
+Cpp11BracedListStyle: true
+DerivePointerAlignment: false
+FixNamespaceComments: true
+IncludeBlocks: Preserve
+IndentCaseLabels: false
+IndentPPDirectives: AfterHash
+IndentWidth: 4
+IndentWrappedFunctionNames: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+MaxEmptyLinesToKeep: 2
+NamespaceIndentation: None
+PenaltyBreakAssignment: 50
+PenaltyBreakBeforeFirstCallParameter: 0
+PenaltyBreakComment: 100
+PenaltyBreakFirstLessLess: 200
+PenaltyBreakString: 100
+#PenaltyBreakTemplateDeclaration: 0
+PenaltyExcessCharacter: 10
+PenaltyReturnTypeOnItsOwnLine: 1000
+PointerAlignment: Left
+ReflowComments: true
+SortIncludes: true
+SpaceAfterCStyleCast: false
+#SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+#SpaceBeforeCpp11BracedList: true
+#SpaceBeforeCtorInitializerColon: false
+#SpaceBeforeInheritanceColon: false
+SpaceBeforeParens: ControlStatements
+#SpaceBeforeRangeBasedForLoopColon: false
+#SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 4
+SpacesInAngles: false
+SpacesInCStyleCastParentheses: false
+SpacesInContainerLiterals: false
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+#Standard: c++17
+TabWidth: 4
+UseTab: Never
diff --git a/cpu/ppc/poweropcodes.cpp b/cpu/ppc/poweropcodes.cpp
index 06ae8b3..07c5024 100644
--- a/cpu/ppc/poweropcodes.cpp
+++ b/cpu/ppc/poweropcodes.cpp
@@ -22,23 +22,22 @@ along with this program. If not, see .
// The Power-specific opcodes for the processor - ppcopcodes.cpp
// Any shared opcodes are in ppcopcodes.cpp
-#include
-#include
-#include
-#include
-#include
#include "ppcemu.h"
#include "ppcmmu.h"
+#include
#include
+#include
#include
+#include
+#include
+#include
void power_abs() {
ppc_grab_regsda();
if (ppc_result_a == 0x80000000) {
ppc_result_d = ppc_result_a;
- }
- else {
+ } else {
ppc_result_d = ppc_result_a & 0x7FFFFFFF;
}
ppc_store_result_regd();
@@ -50,8 +49,7 @@ void power_absdot() {
if (ppc_result_a == 0x80000000) {
ppc_result_d = ppc_result_a;
- }
- else {
+ } else {
ppc_result_d = ppc_result_a & 0x7FFFFFFF;
}
ppc_changecrf0(ppc_result_d);
@@ -64,8 +62,7 @@ void power_abso() {
ppc_result_d = ppc_result_a;
ppc_state.spr[SPR::XER] |= 0x40000000;
- }
- else {
+ } else {
ppc_result_d = ppc_result_a & 0x7FFFFFFF;
}
ppc_store_result_regd();
@@ -77,8 +74,7 @@ void power_absodot() {
ppc_result_d = ppc_result_a;
ppc_state.spr[SPR::XER] |= 0x40000000;
- }
- else {
+ } else {
ppc_result_d = ppc_result_a & 0x7FFFFFFF;
}
ppc_changecrf0(ppc_result_d);
@@ -118,45 +114,45 @@ void power_clcsdot() {
void power_div() {
ppc_grab_regsdab();
- ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
+ ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a | ppc_state.spr[SPR::MQ]) % ppc_result_b;
ppc_store_result_regd();
}
void power_divdot() {
- ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
+ ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a | ppc_state.spr[SPR::MQ]) % ppc_result_b;
}
void power_divo() {
- ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
+ ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a | ppc_state.spr[SPR::MQ]) % ppc_result_b;
}
void power_divodot() {
- ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
+ ppc_result_d = (ppc_result_a | ppc_state.spr[SPR::MQ]) / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a | ppc_state.spr[SPR::MQ]) % ppc_result_b;
}
void power_divs() {
ppc_grab_regsdab();
- ppc_result_d = ppc_result_a / ppc_result_b;
+ ppc_result_d = ppc_result_a / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a % ppc_result_b);
ppc_store_result_regd();
}
void power_divsdot() {
- ppc_result_d = ppc_result_a / ppc_result_b;
+ ppc_result_d = ppc_result_a / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a % ppc_result_b);
}
void power_divso() {
- ppc_result_d = ppc_result_a / ppc_result_b;
+ ppc_result_d = ppc_result_a / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a % ppc_result_b);
}
void power_divsodot() {
- ppc_result_d = ppc_result_a / ppc_result_b;
+ ppc_result_d = ppc_result_a / ppc_result_b;
ppc_state.spr[SPR::MQ] = (ppc_result_a % ppc_result_b);
}
@@ -164,8 +160,7 @@ void power_doz() {
ppc_grab_regsdab();
if (((int32_t)ppc_result_a) > ((int32_t)ppc_result_b)) {
ppc_result_d = 0;
- }
- else {
+ } else {
ppc_result_d = ~ppc_result_a + ppc_result_b + 1;
}
ppc_store_result_rega();
@@ -175,8 +170,7 @@ void power_dozdot() {
ppc_grab_regsdab();
if (((int32_t)ppc_result_a) > ((int32_t)ppc_result_b)) {
ppc_result_d = 0;
- }
- else {
+ } else {
ppc_result_d = ~ppc_result_a + ppc_result_b + 1;
}
ppc_changecrf0(ppc_result_d);
@@ -186,8 +180,7 @@ void power_dozdot() {
void power_dozo() {
if (((int32_t)ppc_result_a) > ((int32_t)ppc_result_b)) {
ppc_result_d = 0;
- }
- else {
+ } else {
ppc_result_d = ~ppc_result_a + ppc_result_b + 1;
}
}
@@ -195,8 +188,7 @@ void power_dozo() {
void power_dozodot() {
if (((int32_t)ppc_result_a) > ((int32_t)ppc_result_b)) {
ppc_result_d = 0;
- }
- else {
+ } else {
ppc_result_d = ~ppc_result_a + ppc_result_b + 1;
}
}
@@ -205,8 +197,7 @@ void power_dozi() {
ppc_grab_regsdab();
if (((int32_t)ppc_result_a) > simm) {
ppc_result_d = 0;
- }
- else {
+ } else {
ppc_result_d = ~ppc_result_a + simm + 1;
}
ppc_store_result_rega();
@@ -215,7 +206,7 @@ void power_dozi() {
void power_lscbx() {
ppc_grab_regsdab();
uint32_t bytes_copied = 0;
- bool match_found = false;
+ bool match_found = false;
uint32_t shift_amount = 0;
uint8_t return_value;
uint8_t byte_compared = (uint8_t)((ppc_state.spr[SPR::XER] & 0xFF00) >> 8);
@@ -223,7 +214,7 @@ void power_lscbx() {
return;
}
uint32_t bytes_to_load = (ppc_state.spr[SPR::XER] & 0x7f) + 1;
- ppc_effective_address = (reg_a == 0) ? ppc_result_b : ppc_result_a + ppc_result_b;
+ ppc_effective_address = (reg_a == 0) ? ppc_result_b : ppc_result_a + ppc_result_b;
do {
ppc_effective_address++;
bytes_to_load--;
@@ -259,9 +250,8 @@ void power_lscbx() {
if (shift_amount == 3) {
shift_amount = 0;
- reg_d = (reg_d + 1) & 0x1F;
- }
- else {
+ reg_d = (reg_d + 1) & 0x1F;
+ } else {
shift_amount++;
}
} while (bytes_to_load > 0);
@@ -275,19 +265,17 @@ void power_lscbxdot() {
void power_maskg() {
ppc_grab_regssab();
- uint32_t mask_start = ppc_result_d & 31;
- uint32_t mask_end = ppc_result_b & 31;
+ uint32_t mask_start = ppc_result_d & 31;
+ uint32_t mask_end = ppc_result_b & 31;
uint32_t insert_mask = 0;
if (mask_start < (mask_end + 1)) {
for (uint32_t i = mask_start; i < mask_end; i++) {
insert_mask |= (0x80000000 >> i);
}
- }
- else if (mask_start == (mask_end + 1)) {
+ } else if (mask_start == (mask_end + 1)) {
insert_mask = 0xFFFFFFFF;
- }
- else {
+ } else {
insert_mask = 0xFFFFFFFF;
for (uint32_t i = (mask_end + 1); i < (mask_start - 1); i++) {
insert_mask &= (~(0x80000000 >> i));
@@ -300,19 +288,17 @@ void power_maskg() {
void power_maskgdot() {
ppc_grab_regssab();
- uint32_t mask_start = ppc_result_d & 31;
- uint32_t mask_end = ppc_result_b & 31;
+ uint32_t mask_start = ppc_result_d & 31;
+ uint32_t mask_end = ppc_result_b & 31;
uint32_t insert_mask = 0;
if (mask_start < (mask_end + 1)) {
for (uint32_t i = mask_start; i < mask_end; i++) {
insert_mask |= (0x80000000 >> i);
}
- }
- else if (mask_start == (mask_end + 1)) {
+ } else if (mask_start == (mask_end + 1)) {
insert_mask = 0xFFFFFFFF;
- }
- else {
+ } else {
insert_mask = 0xFFFFFFFF;
for (uint32_t i = (mask_end + 1); i < (mask_start - 1); i++) {
insert_mask &= (~(0x80000000 >> i));
@@ -326,7 +312,7 @@ void power_maskgdot() {
void power_maskir() {
ppc_grab_regssab();
uint32_t mask_insert = ppc_result_a;
- uint32_t insert_rot = 0x80000000;
+ uint32_t insert_rot = 0x80000000;
do {
if (ppc_result_b & insert_rot) {
mask_insert &= ~insert_rot;
@@ -342,7 +328,7 @@ void power_maskir() {
void power_maskirdot() {
ppc_grab_regssab();
uint32_t mask_insert = ppc_result_a;
- uint32_t insert_rot = 0x80000000;
+ uint32_t insert_rot = 0x80000000;
do {
if (ppc_result_b & insert_rot) {
mask_insert &= ~insert_rot;
@@ -360,41 +346,37 @@ void power_mul() {
ppc_grab_regsdab();
uint64_t product;
- product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
- ppc_result_d = ((uint32_t)(product >> 32));
+ product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
+ ppc_result_d = ((uint32_t)(product >> 32));
ppc_state.spr[SPR::MQ] = ((uint32_t)(product));
ppc_store_result_regd();
-
}
void power_muldot() {
ppc_grab_regsdab();
uint64_t product;
- product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
- ppc_result_d = ((uint32_t)(product >> 32));
+ product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
+ ppc_result_d = ((uint32_t)(product >> 32));
ppc_state.spr[SPR::MQ] = ((uint32_t)(product));
ppc_changecrf0(ppc_result_d);
ppc_store_result_regd();
-
}
void power_mulo() {
uint64_t product;
- product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
- ppc_result_d = ((uint32_t)(product >> 32));
+ product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
+ ppc_result_d = ((uint32_t)(product >> 32));
ppc_state.spr[SPR::MQ] = ((uint32_t)(product));
-
}
void power_mulodot() {
uint64_t product;
- product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
- ppc_result_d = ((uint32_t)(product >> 32));
+ product = ((uint64_t)ppc_result_a) * ((uint64_t)ppc_result_b);
+ ppc_result_d = ((uint32_t)(product >> 32));
ppc_state.spr[SPR::MQ] = ((uint32_t)(product));
-
}
void power_nabs() {
@@ -417,20 +399,18 @@ void power_nabsodot() {
void power_rlmi() {
ppc_grab_regssab();
- unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
- unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
- uint32_t rot_amt = ppc_result_b & 31;
+ unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
+ unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
uint32_t insert_mask = 0;
if (rot_mb < (rot_me + 1)) {
for (uint32_t i = rot_mb; i < rot_me; i++) {
insert_mask |= (0x80000000 >> i);
}
- }
- else if (rot_mb == (rot_me + 1)) {
+ } else if (rot_mb == (rot_me + 1)) {
insert_mask = 0xFFFFFFFF;
- }
- else {
+ } else {
insert_mask = 0xFFFFFFFF;
for (uint32_t i = (rot_me + 1); i < (rot_mb - 1); i++) {
insert_mask &= (~(0x80000000 >> i));
@@ -438,7 +418,7 @@ void power_rlmi() {
}
uint32_t step2 = (ppc_result_d << rot_amt) | (ppc_result_d >> rot_amt);
- ppc_result_a = step2 & insert_mask;
+ ppc_result_a = step2 & insert_mask;
ppc_store_result_rega();
}
@@ -446,8 +426,7 @@ void power_rrib() {
ppc_grab_regssab();
if (ppc_result_d & 0x80000000) {
ppc_result_a |= (0x80000000 >> ppc_result_b);
- }
- else {
+ } else {
ppc_result_a &= ~(0x80000000 >> ppc_result_b);
}
ppc_store_result_rega();
@@ -457,8 +436,7 @@ void power_rribdot() {
ppc_grab_regssab();
if (ppc_result_d & 0x80000000) {
ppc_result_a |= (0x80000000 >> ppc_result_b);
- }
- else {
+ } else {
ppc_result_a &= ~(0x80000000 >> ppc_result_b);
}
ppc_changecrf0(ppc_result_a);
@@ -468,26 +446,26 @@ void power_rribdot() {
void power_sle() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
- uint32_t insert_final = ((ppc_result_d << rot_amt) | (ppc_result_d >> (32 - rot_amt)));
+ uint32_t insert_final = ((ppc_result_d << rot_amt) | (ppc_result_d >> (32 - rot_amt)));
ppc_state.spr[SPR::MQ] = insert_final & insert_mask;
- ppc_result_a = insert_final & insert_mask;
+ ppc_result_a = insert_final & insert_mask;
ppc_store_result_rega();
}
void power_sledot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
- uint32_t insert_final = ((ppc_result_d << rot_amt) | (ppc_result_d >> (32 - rot_amt)));
+ uint32_t insert_final = ((ppc_result_d << rot_amt) | (ppc_result_d >> (32 - rot_amt)));
ppc_state.spr[SPR::MQ] = insert_final & insert_mask;
- ppc_result_a = insert_final & insert_mask;
+ ppc_result_a = insert_final & insert_mask;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
}
@@ -495,12 +473,12 @@ void power_sledot() {
void power_sleq() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_amt) | (ppc_result_d >> (rot_amt - 31)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -509,7 +487,7 @@ void power_sleq() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_store_result_rega();
}
@@ -517,12 +495,12 @@ void power_sleq() {
void power_sleqdot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_amt) | (ppc_result_d >> (rot_amt - 31)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -531,7 +509,7 @@ void power_sleqdot() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
@@ -540,12 +518,12 @@ void power_sleqdot() {
void power_sliq() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_sh) | (ppc_result_d >> (rot_sh - 31)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -554,7 +532,7 @@ void power_sliq() {
}
}
- ppc_result_a = insert_end & insert_mask;
+ ppc_result_a = insert_end & insert_mask;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_store_result_rega();
}
@@ -562,12 +540,12 @@ void power_sliq() {
void power_sliqdot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_sh) | (ppc_result_d >> (rot_sh - 31)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -576,7 +554,7 @@ void power_sliqdot() {
}
}
- ppc_result_a = insert_end & insert_mask;
+ ppc_result_a = insert_end & insert_mask;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
@@ -585,12 +563,12 @@ void power_sliqdot() {
void power_slliq() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -599,7 +577,7 @@ void power_slliq() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_store_result_rega();
}
@@ -607,12 +585,12 @@ void power_slliq() {
void power_slliqdot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -621,7 +599,7 @@ void power_slliqdot() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
@@ -662,26 +640,26 @@ void power_sraqdot() {
void power_sre() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
- uint32_t insert_final = ((ppc_result_d >> rot_amt) | (ppc_result_d << (32 - rot_amt)));
+ uint32_t insert_final = ((ppc_result_d >> rot_amt) | (ppc_result_d << (32 - rot_amt)));
ppc_state.spr[SPR::MQ] = insert_final & insert_mask;
- ppc_result_a = insert_final;
+ ppc_result_a = insert_final;
ppc_store_result_rega();
}
void power_sredot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- uint32_t rot_amt = ppc_result_b & 31;
+ uint32_t rot_amt = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_amt; i--) {
insert_mask |= (1 << i);
}
- uint32_t insert_final = ((ppc_result_d >> rot_amt) | (ppc_result_d << (32 - rot_amt)));
+ uint32_t insert_final = ((ppc_result_d >> rot_amt) | (ppc_result_d << (32 - rot_amt)));
ppc_state.spr[SPR::MQ] = insert_final & insert_mask;
- ppc_result_a = insert_final;
+ ppc_result_a = insert_final;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
}
@@ -697,12 +675,12 @@ void power_sreadot() {
void power_sreq() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = ppc_result_b & 31;
+ unsigned rot_sh = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -711,7 +689,7 @@ void power_sreq() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_store_result_rega();
}
@@ -719,12 +697,12 @@ void power_sreq() {
void power_sreqdot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = ppc_result_b & 31;
+ unsigned rot_sh = ppc_result_b & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -733,7 +711,7 @@ void power_sreqdot() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
@@ -742,12 +720,12 @@ void power_sreqdot() {
void power_sriq() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -756,7 +734,7 @@ void power_sriq() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_store_result_rega();
}
@@ -764,12 +742,12 @@ void power_sriq() {
void power_sriqdot() {
ppc_grab_regssa();
uint32_t insert_mask = 0;
- unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
+ unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
for (uint32_t i = 31; i > rot_sh; i--) {
insert_mask |= (1 << i);
}
uint32_t insert_start = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
- uint32_t insert_end = ppc_state.spr[SPR::MQ];
+ uint32_t insert_end = ppc_state.spr[SPR::MQ];
for (int i = 0; i < 32; i++) {
if (insert_mask & (1 << i)) {
@@ -778,7 +756,7 @@ void power_sriqdot() {
}
}
- ppc_result_a = insert_end;
+ ppc_result_a = insert_end;
ppc_state.spr[SPR::MQ] = insert_start;
ppc_changecrf0(ppc_result_a);
ppc_store_result_rega();
diff --git a/cpu/ppc/ppcdisasm.cpp b/cpu/ppc/ppcdisasm.cpp
index f9563f3..21ecd1b 100644
--- a/cpu/ppc/ppcdisasm.cpp
+++ b/cpu/ppc/ppcdisasm.cpp
@@ -25,18 +25,17 @@ along with this program. If not, see .
#define _CRT_SECURE_NO_WARNINGS /* shut up MSVC regarding the unsafe strcpy/strcat */
-#include
-#include
-#include
-#include
-#include /* without this, MSVC doesn't understand std::function */
#include "ppcdisasm.h"
+#include
+#include /* without this, MSVC doesn't understand std::function */
+#include
+#include
+#include
using namespace std;
-template< typename... Args >
-std::string my_sprintf(const char* format, Args... args)
-{
+template
+std::string my_sprintf(const char* format, Args... args) {
int length = std::snprintf(nullptr, 0, format, args...);
if (length <= 0)
return {}; /* empty string in C++11 */
@@ -49,216 +48,264 @@ std::string my_sprintf(const char* format, Args... args)
return str;
}
-const char* arith_im_mnem[9] = {
- "mulli", "subfic", "", "", "", "addic", "addic.", "addi", "addis"
-};
+const char* arith_im_mnem[9] = {"mulli", "subfic", "", "", "", "addic", "addic.", "addi", "addis"};
-const char* bx_mnem[4] = {
- "b", "bl", "ba", "bla"
-};
+const char* bx_mnem[4] = {"b", "bl", "ba", "bla"};
-const char* bclrx_mnem[2] = {
- "blr", "blrl"
-};
+const char* bclrx_mnem[2] = {"blr", "blrl"};
-const char* bcctrx_mnem[2] = {
- "bctr", "bctrl"
-};
+const char* bcctrx_mnem[2] = {"bctr", "bctrl"};
-const char* br_cond[8] = { /* simplified branch conditions */
- "ge", "le", "ne", "ns", "lt", "gt", "eq", "so"
-};
+const char* br_cond[8] = {/* simplified branch conditions */
+ "ge",
+ "le",
+ "ne",
+ "ns",
+ "lt",
+ "gt",
+ "eq",
+ "so"};
-const char* bclrx_cond[8] = { /* simplified branch conditions */
- "gelr", "lelr", "nelr", "nslr", "ltlr", "gtlr", "eqlr", "solr"
-};
+const char* bclrx_cond[8] = {/* simplified branch conditions */
+ "gelr",
+ "lelr",
+ "nelr",
+ "nslr",
+ "ltlr",
+ "gtlr",
+ "eqlr",
+ "solr"};
-const char* bcctrx_cond[8] = { /* simplified branch conditions */
- "gectr", "lectr", "nectr", "nsctr", "ltctr", "gtctr", "eqctr", "soctr"
-};
+const char* bcctrx_cond[8] = {/* simplified branch conditions */
+ "gectr",
+ "lectr",
+ "nectr",
+ "nsctr",
+ "ltctr",
+ "gtctr",
+ "eqctr",
+ "soctr"};
-const char* opc_idx_ldst[32] = { /* indexed load/store opcodes */
- "lwzx", "lwzux", "lbzx", "lbzux", "stwx", "stwux", "stbx", "stbux",
- "lhzx", "lhzux", "lhax", "lhaux", "sthx", "sthux", "", "",
- "lfsx", "lfsux", "lfdx", "lfdux", "stfsx", "stfsux", "stfdx", "stfdux",
- "", "", "", "", "", "", "stfiwx", ""
-};
+const char* opc_idx_ldst[32] = {/* indexed load/store opcodes */
+ "lwzx", "lwzux", "lbzx", "lbzux", "stwx", "stwux", "stbx",
+ "stbux", "lhzx", "lhzux", "lhax", "lhaux", "sthx", "sthux",
+ "", "", "lfsx", "lfsux", "lfdx", "lfdux", "stfsx",
+ "stfsux", "stfdx", "stfdux", "", "", "", "",
+ "", "", "stfiwx", ""};
-const char* opc_bim_str[6] = { /* boolean immediate instructions */
- "ori", "oris", "xori", "xoris", "andi.", "andis."
-};
+const char* opc_bim_str[6] = {/* boolean immediate instructions */
+ "ori",
+ "oris",
+ "xori",
+ "xoris",
+ "andi.",
+ "andis."};
-const char* opc_logic[16] = { /* indexed load/store opcodes */
- "and", "andc", "", "nor", "", "", "", "", "eqv", "xor", "", "", "orc", "or",
- "nand", ""
-};
+const char* opc_logic[16] = {/* indexed load/store opcodes */
+ "and",
+ "andc",
+ "",
+ "nor",
+ "",
+ "",
+ "",
+ "",
+ "eqv",
+ "xor",
+ "",
+ "",
+ "orc",
+ "or",
+ "nand",
+ ""};
-const char* opc_subs[16] = { /* subtracts & friends */
- "subfc", "subf", "", "neg", "subfe", "", "subfze", "subfme", "doz", "", "",
- "abs", "", "", "", "nabs"
-};
+const char* opc_subs[16] = {/* subtracts & friends */
+ "subfc",
+ "subf",
+ "",
+ "neg",
+ "subfe",
+ "",
+ "subfze",
+ "subfme",
+ "doz",
+ "",
+ "",
+ "abs",
+ "",
+ "",
+ "",
+ "nabs"};
-const char* opc_adds[9] = { /* additions */
- "addc", "", "", "", "adde", "", "addze", "addme", "add"
-};
+const char* opc_adds[9] = {/* additions */
+ "addc",
+ "",
+ "",
+ "",
+ "adde",
+ "",
+ "addze",
+ "addme",
+ "add"};
-const char* opc_muldivs[16] = { /* multiply and division instructions */
- "mulhwu", "", "mulhw", "mul", "", "", "", "mullw", "", "", "div", "divs",
- "", "", "divwu", "divw"
-};
+const char* opc_muldivs[16] = {/* multiply and division instructions */
+ "mulhwu",
+ "",
+ "mulhw",
+ "mul",
+ "",
+ "",
+ "",
+ "mullw",
+ "",
+ "",
+ "div",
+ "divs",
+ "",
+ "",
+ "divwu",
+ "divw"};
-const char* opc_shft_reg[32]{ /* Regular shift instructions */
- "slw", "", "", "", "slq", "sliq", "sllq", "slliq",
- "", "", "", "", "", "", "", "",
- "srw", "", "", "", "srq", "sriq", "srlq", "srliq",
- "sraw", "srawi", "", "", "sraq", "sraiq", "", ""
-};
+const char* opc_shft_reg[32]{
+ /* Regular shift instructions */
+ "slw", "", "", "", "slq", "sliq", "sllq", "slliq", "", "", "",
+ "", "", "", "", "", "srw", "", "", "", "srq", "sriq",
+ "srlq", "srliq", "sraw", "srawi", "", "", "sraq", "sraiq", "", ""};
-const char* opc_shft_ext[32]{ /* Extended shift instructions (601 only) */
- "", "", "", "", "sle", "", "sleq", "",
- "", "", "", "", "", "", "", "",
- "rrib", "", "", "", "sre", "", "sreq", "",
- "", "", "", "", "srea", "", "", ""
-};
+const char* opc_shft_ext[32]{
+ /* Extended shift instructions (601 only) */
+ "", "", "", "", "sle", "", "sleq", "", "", "", "", "", "", "", "", "",
+ "rrib", "", "", "", "sre", "", "sreq", "", "", "", "", "", "srea", "", "", ""};
-const char* opc_int_ldst[16] = { /* integer load and store instructions */
- "lwz", "lwzu", "lbz", "lbzu", "stw", "stwu", "stb", "stbu", "lhz", "lhzu",
- "lha", "lhau", "sth", "sthu", "lmw", "stmw"
-};
+const char* opc_int_ldst[16] = {/* integer load and store instructions */
+ "lwz",
+ "lwzu",
+ "lbz",
+ "lbzu",
+ "stw",
+ "stwu",
+ "stb",
+ "stbu",
+ "lhz",
+ "lhzu",
+ "lha",
+ "lhau",
+ "sth",
+ "sthu",
+ "lmw",
+ "stmw"};
/* processor management + byte reversed load and store */
const char* proc_mgmt_str[32] = {
- "", "dcbst", "dcbf", "", "stwcx.", "", "", "dcbtst",
- "dcbt", "eciwx", "", "", "", "ecowx", "dcbi", "",
- "lwbrx", "tlbsync", "sync", "", "stwbrx", "", "", "dcba",
- "lhbrx", "", "eieio", "", "sthbrx", "", "icbi", "dcbz"
+ "", "dcbst", "dcbf", "", "stwcx.", "", "", "dcbtst", "dcbt", "eciwx", "",
+ "", "", "ecowx", "dcbi", "", "lwbrx", "tlbsync", "sync", "", "stwbrx", "",
+ "", "dcba", "lhbrx", "", "eieio", "", "sthbrx", "", "icbi", "dcbz"};
+
+const char* opc_flt_ldst[8] = {/* integer load and store instructions */
+ "lfs",
+ "lfsu",
+ "lfd",
+ "lfdu",
+ "stfs",
+ "stfsu",
+ "sftd",
+ "sftdu"};
+
+const char* opc_flt_ext_arith[32] = {
+ /* integer load and store instructions */
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "fsel", "", "fmul", "", "", "fmsub", "fmadd", "fnmsub", "fnmadd",
};
-const char* opc_flt_ldst[8] = { /* integer load and store instructions */
- "lfs", "lfsu", "lfd", "lfdu", "stfs", "stfsu", "sftd", "sftdu"
-};
+const char* trap_cond[32] = {/*Trap conditions*/
+ "", "twlgt", "twllt", "", "tweq", "twlge", "twlle", "",
+ "twgt", "", "", "", "twge", "", "", "",
+ "twlt", "", "", "", "twle", "", "", "",
+ "twne", "", "", "", "", "", "", ""};
-const char* opc_flt_ext_arith[32] = { /* integer load and store instructions */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "fsel",
- "", "fmul", "", "", "fmsub", "fmadd", "fnmsub", "fnmadd",
-};
-
-const char* trap_cond[32] = { /*Trap conditions*/
- "", "twlgt", "twllt", "", "tweq", "twlge", "twlle", "",
- "twgt", "", "", "", "twge", "", "", "",
- "twlt", "", "", "", "twle", "", "", "",
- "twne", "", "", "", "", "", "", ""
-};
-
-const char* spr_index0[32] = {
- "mq", "xer", "", "", "rtcu", "rtcl", "", "",
- "lr", "ctr", "", "", "", "", "", "",
- "", "", "dsisr", "dar", "", "", "dec", "",
- "", "sdr1", "srr0", "srr1", "", "", "", ""
-};
+const char* spr_index0[32] = {"mq", "xer", "", "", "rtcu", "rtcl", "", "",
+ "lr", "ctr", "", "", "", "", "", "",
+ "", "", "dsisr", "dar", "", "", "dec", "",
+ "", "sdr1", "srr0", "srr1", "", "", "", ""};
const char* spr_index8[32] = {
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "sprg0", "sprg1", "sprg2", "sprg3", "sprg4", "sprg5", "sprg6", "sprg7",
- "", "", "ear", "", "tbl", "tbu", "", "pvr"
-};
+ "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "sprg0", "sprg1", "sprg2", "sprg3", "sprg4", "sprg5",
+ "sprg6", "sprg7", "", "", "ear", "", "tbl", "tbu", "", "pvr"};
const char* spr_index16[32] = {
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
"ibat0u", "ibat0l", "ibat1u", "ibat1l", "ibat2u", "ibat2l", "ibat3u", "ibat3l",
"dbat0u", "dbat0l", "dbat1u", "dbat1l", "dbat2u", "dbat2l", "dbat3u", "dbat3l",
};
const char* spr_index29[32] = {
- "", "", "", "", "", "", "", "",
- "ummcr0", "upmc1", "upmc2", "usia", "ummcr1", "upmc3", "upmc4", "",
- "", "", "", "", "", "", "", "",
- "mmcr0", "pmc1", "pmc2", "sia", "mmcr1", "pmc3", "pmc4", "sda"
-};
+ "", "", "", "", "", "", "", "", "ummcr0", "upmc1", "upmc2",
+ "usia", "ummcr1", "upmc3", "upmc4", "", "", "", "", "", "", "",
+ "", "", "mmcr0", "pmc1", "pmc2", "sia", "mmcr1", "pmc3", "pmc4", "sda"};
const char* spr_index30[32] = {
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "dmiss", "dcmp", "hash1", "hash2", "imiss", "icmp", "rpa", "",
- "", "", "", "", "", "", "", ""
-};
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "dmiss", "dcmp", "hash1", "hash2", "imiss", "icmp", "rpa", "", "", "", "", "", "", "", "", ""};
const char* spr_index31[32] = {
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "hid0", "hid1", "iabr", "", "", "dabr", "", "",
- "", "l2cr", "", "ictc", "thrm1", "thrm2", "thrm3", "pir",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "hid0", "hid1", "iabr", "", "", "dabr",
+ "", "", "", "l2cr", "", "ictc", "thrm1", "thrm2", "thrm3", "pir",
};
/** various formatting helpers. */
-void fmt_oneop(string& buf, const char* opc, int src)
-{
+void fmt_oneop(string& buf, const char* opc, int src) {
buf = my_sprintf("%-8sr%d", opc, src);
}
-void fmt_twoop(string& buf, const char* opc, int dst, int src)
-{
+void fmt_twoop(string& buf, const char* opc, int dst, int src) {
buf = my_sprintf("%-8sr%d, r%d", opc, dst, src);
}
-void fmt_twoop_simm(string& buf, const char* opc, int dst, int imm)
-{
+void fmt_twoop_simm(string& buf, const char* opc, int dst, int imm) {
buf = my_sprintf("%-8sr%d, %s0x%X", opc, dst, (imm < 0) ? "-" : "", abs(imm));
}
-void fmt_twoop_fromspr(string& buf, const char* opc, int dst, int src)
-{
+void fmt_twoop_fromspr(string& buf, const char* opc, int dst, int src) {
buf = my_sprintf("%-8sr%d, spr%d", opc, dst, src);
}
-void fmt_twoop_tospr(string& buf, const char* opc, int dst, int src)
-{
+void fmt_twoop_tospr(string& buf, const char* opc, int dst, int src) {
buf = my_sprintf("%-8sspr%d, r%d", opc, dst, src);
}
-void fmt_twoop_flt(string& buf, const char* opc, int dst, int src1)
-{
+void fmt_twoop_flt(string& buf, const char* opc, int dst, int src1) {
buf = my_sprintf("%-8sf%d, f%d", opc, dst, src1);
}
-void fmt_threeop(string& buf, const char* opc, int dst, int src1, int src2)
-{
+void fmt_threeop(string& buf, const char* opc, int dst, int src1, int src2) {
buf = my_sprintf("%-8sr%d, r%d, r%d", opc, dst, src1, src2);
}
-void fmt_threeop_crb(string& buf, const char* opc, int dst, int src1, int src2)
-{
+void fmt_threeop_crb(string& buf, const char* opc, int dst, int src1, int src2) {
buf = my_sprintf("%-8scrb%d, crb%d, crb%d", opc, dst, src1, src2);
}
-void fmt_threeop_uimm(string& buf, const char* opc, int dst, int src1, int imm)
-{
+void fmt_threeop_uimm(string& buf, const char* opc, int dst, int src1, int imm) {
buf = my_sprintf("%-8sr%d, r%d, 0x%X", opc, dst, src1, imm);
}
-void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm)
-{
- buf = my_sprintf("%-8sr%d, r%d, %s0x%X", opc, dst, src1,
- (imm < 0) ? "-" : "", abs(imm));
+void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm) {
+ buf = my_sprintf("%-8sr%d, r%d, %s0x%X", opc, dst, src1, (imm < 0) ? "-" : "", abs(imm));
}
-void fmt_threeop_flt(string& buf, const char* opc, int dst, int src1, int src2)
-{
+void fmt_threeop_flt(string& buf, const char* opc, int dst, int src1, int src2) {
buf = my_sprintf("%-8sf%d, f%d, f%d", opc, dst, src1, src2);
}
-void fmt_fourop_flt(string& buf, const char* opc, int dst, int src1, int src2, int src3)
-{
+void fmt_fourop_flt(string& buf, const char* opc, int dst, int src1, int src2, int src3) {
buf = my_sprintf("%-8sf%d, f%d, f%d, f%d", opc, dst, src1, src2, src3);
}
-void fmt_rotateop(string& buf, const char* opc, int dst, int src, int sh, int mb, int me, bool imm)
-{
+void fmt_rotateop(string& buf, const char* opc, int dst, int src, int sh, int mb, int me, bool imm) {
if (imm)
buf = my_sprintf("%-8sr%d, r%d, %d, %d, %d", opc, dst, src, sh, mb, me);
else
@@ -267,18 +314,15 @@ void fmt_rotateop(string& buf, const char* opc, int dst, int src, int sh, int mb
/* Opcodes */
-void opc_illegal(PPCDisasmContext* ctx)
-{
+void opc_illegal(PPCDisasmContext* ctx) {
ctx->instr_str = my_sprintf("%-8s0x%08X", "dc.l", ctx->instr_code);
}
-void opc_twi(PPCDisasmContext* ctx)
-{
-
+void opc_twi(PPCDisasmContext* ctx) {
char opcode[10] = "";
- auto to = (ctx->instr_code >> 21) & 0x1F;
- auto ra = (ctx->instr_code >> 16) & 0x1F;
+ auto to = (ctx->instr_code >> 21) & 0x1F;
+ auto ra = (ctx->instr_code >> 16) & 0x1F;
int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
if (ctx->simplified) {
@@ -289,28 +333,24 @@ void opc_twi(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8sr%d, 0x%X", opcode, ra, imm);
return;
}
-
}
ctx->instr_str = my_sprintf("%-8s%d, r%d, 0x%X", "twi", to, ra, imm);
}
-void opc_group4(PPCDisasmContext* ctx)
-{
+void opc_group4(PPCDisasmContext* ctx) {
printf("Altivec group 4 not supported yet\n");
}
-void opc_ar_im(PPCDisasmContext* ctx)
-{
- auto ra = (ctx->instr_code >> 16) & 0x1F;
- auto rd = (ctx->instr_code >> 21) & 0x1F;
+void opc_ar_im(PPCDisasmContext* ctx) {
+ auto ra = (ctx->instr_code >> 16) & 0x1F;
+ auto rd = (ctx->instr_code >> 21) & 0x1F;
int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
if (ctx->simplified) {
if (((ctx->instr_code >> 26) == 0xE) & !ra) {
fmt_twoop_simm(ctx->instr_str, "li", rd, imm);
return;
- }
- else if (((ctx->instr_code >> 26) == 0xF) & !ra) {
+ } else if (((ctx->instr_code >> 26) == 0xF) & !ra) {
fmt_twoop_simm(ctx->instr_str, "lis", rd, imm);
return;
}
@@ -333,21 +373,18 @@ void opc_ar_im(PPCDisasmContext* ctx)
}
}
- fmt_threeop_simm(ctx->instr_str, arith_im_mnem[(ctx->instr_code >> 26) - 7],
- rd, ra, imm);
+ fmt_threeop_simm(ctx->instr_str, arith_im_mnem[(ctx->instr_code >> 26) - 7], rd, ra, imm);
}
-void power_dozi(PPCDisasmContext* ctx)
-{
- auto ra = (ctx->instr_code >> 16) & 0x1F;
- auto rd = (ctx->instr_code >> 21) & 0x1F;
+void power_dozi(PPCDisasmContext* ctx) {
+ auto ra = (ctx->instr_code >> 16) & 0x1F;
+ auto rd = (ctx->instr_code >> 21) & 0x1F;
auto imm = ctx->instr_code & 0xFFFF;
fmt_threeop_simm(ctx->instr_str, "dozi", rd, ra, imm);
}
-void fmt_rot_imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n)
-{
+void fmt_rot_imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n) {
char opcode[10];
strcpy(opcode, opc);
@@ -357,9 +394,7 @@ void fmt_rot_imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n)
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d", opcode, ra, rs, n);
}
-void fmt_rot_2imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n,
- int b)
-{
+void fmt_rot_2imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n, int b) {
char opcode[10];
strcpy(opcode, opc);
@@ -369,8 +404,7 @@ void fmt_rot_2imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n,
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", opcode, ra, rs, n, b);
}
-void opc_rlwimi(PPCDisasmContext* ctx)
-{
+void opc_rlwimi(PPCDisasmContext* ctx) {
char opcode[10];
auto rs = (ctx->instr_code >> 21) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
@@ -382,8 +416,7 @@ void opc_rlwimi(PPCDisasmContext* ctx)
if ((32 - sh) == mb) {
fmt_rot_2imm(ctx, "inslwi", ra, rs, me + 1 - mb, mb);
return;
- }
- else if (sh == 32 - (me + 1)) {
+ } else if (sh == 32 - (me + 1)) {
fmt_rot_2imm(ctx, "insrwi", ra, rs, (me - mb + 1), mb);
return;
}
@@ -396,8 +429,7 @@ void opc_rlwimi(PPCDisasmContext* ctx)
fmt_rotateop(ctx->instr_str, opcode, ra, rs, sh, mb, me, true);
}
-void opc_rlwinm(PPCDisasmContext* ctx)
-{
+void opc_rlwinm(PPCDisasmContext* ctx) {
char opcode[10];
auto rs = (ctx->instr_code >> 21) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
@@ -413,8 +445,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
fmt_rot_imm(ctx, "rotrwi", ra, rs, 32 - sh);
}
return;
- }
- else if (me == 31) {
+ } else if (me == 31) {
if ((32 - sh) == mb) {
fmt_rot_imm(ctx, "srwi", ra, rs, mb);
} else if (sh == 0) {
@@ -423,8 +454,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
fmt_rot_2imm(ctx, "extrwi", ra, rs, (32 - mb), (sh - (32 - mb)));
}
return;
- }
- else if (mb == 0) {
+ } else if (mb == 0) {
if ((31 - me) == sh) {
fmt_rot_imm(ctx, "slwi", ra, rs, sh);
} else if (sh == 0) {
@@ -433,8 +463,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
fmt_rot_2imm(ctx, "extlwi", ra, rs, (me + 1), sh);
}
return;
- }
- else if (mb) {
+ } else if (mb) {
if ((31 - me) == sh) {
fmt_rot_2imm(ctx, "clrlslwi", ra, rs, (mb + sh), sh);
return;
@@ -449,8 +478,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
fmt_rotateop(ctx->instr_str, opcode, ra, rs, sh, mb, me, true);
}
-void opc_rlmi(PPCDisasmContext* ctx)
-{
+void opc_rlmi(PPCDisasmContext* ctx) {
auto rs = (ctx->instr_code >> 21) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto rb = (ctx->instr_code >> 11) & 0x1F;
@@ -463,8 +491,7 @@ void opc_rlmi(PPCDisasmContext* ctx)
fmt_rotateop(ctx->instr_str, "rlmi", ra, rs, rb, mb, me, false);
}
-void opc_rlwnm(PPCDisasmContext* ctx)
-{
+void opc_rlwnm(PPCDisasmContext* ctx) {
char opcode[10];
auto rs = (ctx->instr_code >> 21) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
@@ -479,8 +506,8 @@ void opc_rlwnm(PPCDisasmContext* ctx)
if (ctx->instr_code & 1)
strcat(opcode, ".");
- fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
- return;
+ fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
+ return;
}
}
strcpy(opcode, "rlwnm");
@@ -490,12 +517,11 @@ void opc_rlwnm(PPCDisasmContext* ctx)
fmt_rotateop(ctx->instr_str, "rlwnm", ra, rs, rb, mb, me, false);
}
-void opc_cmp_i_li(PPCDisasmContext* ctx)
-{
- auto ls = (ctx->instr_code >> 21) & 0x1;
- auto ra = (ctx->instr_code >> 16) & 0x1F;
+void opc_cmp_i_li(PPCDisasmContext* ctx) {
+ auto ls = (ctx->instr_code >> 21) & 0x1;
+ auto ra = (ctx->instr_code >> 16) & 0x1F;
auto crfd = (ctx->instr_code >> 23) & 0x07;
- int imm = ctx->instr_code & 0xFFFF;
+ int imm = ctx->instr_code & 0xFFFF;
if (ctx->simplified) {
@@ -503,7 +529,8 @@ void opc_cmp_i_li(PPCDisasmContext* ctx)
if ((ctx->instr_code >> 26) & 0x1)
ctx->instr_str = my_sprintf("%-8scr%d, r%d, 0x%X", "cmpwi", crfd, ra, imm);
else
- ctx->instr_str = my_sprintf("%-8scr%d, r%d, %s0x%X", "cmplwi", crfd, ra, (imm < 0) ? "-" : "", abs(imm));
+ ctx->instr_str = my_sprintf(
+ "%-8scr%d, r%d, %s0x%X", "cmplwi", crfd, ra, (imm < 0) ? "-" : "", abs(imm));
return;
}
@@ -512,21 +539,21 @@ void opc_cmp_i_li(PPCDisasmContext* ctx)
if ((ctx->instr_code >> 26) & 0x1)
ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, 0x%X", "cmpi", crfd, ls, ra, imm);
else
- ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, %s0x%X", "cmpli", crfd, ls, ra, (imm < 0) ? "-" : "", abs(imm));
+ ctx->instr_str = my_sprintf(
+ "%-8scr%d, %d, r%d, %s0x%X", "cmpli", crfd, ls, ra, (imm < 0) ? "-" : "", abs(imm));
}
-void opc_bool_im(PPCDisasmContext* ctx)
-{
+void opc_bool_im(PPCDisasmContext* ctx) {
char opcode[10];
- auto ra = (ctx->instr_code >> 16) & 0x1F;
- auto rs = (ctx->instr_code >> 21) & 0x1F;
+ auto ra = (ctx->instr_code >> 16) & 0x1F;
+ auto rs = (ctx->instr_code >> 21) & 0x1F;
auto index = ((ctx->instr_code >> 26) & 0x1F) - 24;
- auto imm = ctx->instr_code & 0xFFFF;
+ auto imm = ctx->instr_code & 0xFFFF;
if (ctx->simplified) {
if (index == 0) {
- if (imm == 0 && !ra && !rs && !imm) { /* unofficial, produced by IDA */
+ if (imm == 0 && !ra && !rs && !imm) { /* unofficial, produced by IDA */
ctx->instr_str = my_sprintf("%-8s", "nop");
return;
}
@@ -537,8 +564,7 @@ void opc_bool_im(PPCDisasmContext* ctx)
fmt_threeop_uimm(ctx->instr_str, opcode, ra, rs, imm);
}
-void generic_bcx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi, uint32_t dst)
-{
+void generic_bcx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi, uint32_t dst) {
char opcode[10] = "bc";
if (ctx->instr_code & 1) {
@@ -550,8 +576,7 @@ void generic_bcx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi, uint32_t dst)
ctx->instr_str = my_sprintf("%-8s%d, %d, 0x%08X", opcode, bo, bi, dst);
}
-void generic_bcctrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi)
-{
+void generic_bcctrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi) {
char opcode[10] = "bcctr";
if (ctx->instr_code & 1) {
@@ -561,8 +586,7 @@ void generic_bcctrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi)
ctx->instr_str = my_sprintf("%-8s%d, %d, 0x%08X", opcode, bo, bi);
}
-void generic_bclrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi)
-{
+void generic_bclrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi) {
char opcode[10] = "bclr";
if (ctx->instr_code & 1) {
@@ -572,20 +596,17 @@ void generic_bclrx(PPCDisasmContext* ctx, uint32_t bo, uint32_t bi)
ctx->instr_str = my_sprintf("%-8s%d, %d, 0x%08X", opcode, bo, bi);
}
-void opc_bcx(PPCDisasmContext* ctx)
-{
+void opc_bcx(PPCDisasmContext* ctx) {
uint32_t bo, bi, dst, cr;
- char opcode[10] = "b";
+ char opcode[10] = "b";
char operands[12] = "";
- bo = (ctx->instr_code >> 21) & 0x1F;
- bi = (ctx->instr_code >> 16) & 0x1F;
- cr = bi >> 2;
- dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr) +
- SIGNEXT(ctx->instr_code & 0xFFFC, 15);
+ bo = (ctx->instr_code >> 21) & 0x1F;
+ bi = (ctx->instr_code >> 16) & 0x1F;
+ cr = bi >> 2;
+ dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr) + SIGNEXT(ctx->instr_code & 0xFFFC, 15);
- if (!ctx->simplified || ((bo & 0x10) && bi) ||
- (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
+ if (!ctx->simplified || ((bo & 0x10) && bi) || (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
generic_bcx(ctx, bo, bi, dst);
return;
}
@@ -607,8 +628,7 @@ void opc_bcx(PPCDisasmContext* ctx)
strcat(operands, br_cond[4 + (bi & 3)]);
strcat(operands, ", ");
}
- }
- else { /* CTR ignored */
+ } else { /* CTR ignored */
strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
if (cr) {
strcat(operands, "cr0, ");
@@ -629,10 +649,9 @@ void opc_bcx(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8s%s0x%08X", opcode, operands, dst);
}
-void opc_bcctrx(PPCDisasmContext* ctx)
-{
+void opc_bcctrx(PPCDisasmContext* ctx) {
uint32_t bo, bi, cr;
- char opcode[10] = "b";
+ char opcode[10] = "b";
char operands[4] = "";
bo = (ctx->instr_code >> 21) & 0x1F;
@@ -643,8 +662,7 @@ void opc_bcctrx(PPCDisasmContext* ctx)
opc_illegal(ctx);
}
- if (!ctx->simplified || ((bo & 0x10) && bi) ||
- (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
+ if (!ctx->simplified || ((bo & 0x10) && bi) || (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
generic_bcctrx(ctx, bo, bi);
return;
}
@@ -671,18 +689,16 @@ void opc_bcctrx(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8s%s", opcode, operands);
}
-void opc_bclrx(PPCDisasmContext* ctx)
-{
+void opc_bclrx(PPCDisasmContext* ctx) {
uint32_t bo, bi, cr;
- char opcode[10] = "b";
+ char opcode[10] = "b";
char operands[12] = "";
bo = (ctx->instr_code >> 21) & 0x1F;
bi = (ctx->instr_code >> 16) & 0x1F;
cr = bi >> 2;
- if (!ctx->simplified || ((bo & 0x10) && bi) ||
- (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
+ if (!ctx->simplified || ((bo & 0x10) && bi) || (((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
generic_bclrx(ctx, bo, bi);
return;
}
@@ -703,8 +719,7 @@ void opc_bclrx(PPCDisasmContext* ctx)
}
strcat(operands, br_cond[4 + (bi & 3)]);
}
- }
- else { /* CTR ignored */
+ } else { /* CTR ignored */
strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
if (cr) {
strcat(operands, "cr0");
@@ -724,26 +739,23 @@ void opc_bclrx(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8s%s", opcode, operands);
}
-void opc_bx(PPCDisasmContext* ctx)
-{
- uint32_t dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr)
- + SIGNEXT(ctx->instr_code & 0x3FFFFFC, 25);
+void opc_bx(PPCDisasmContext* ctx) {
+ uint32_t dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr) +
+ SIGNEXT(ctx->instr_code & 0x3FFFFFC, 25);
ctx->instr_str = my_sprintf("%-8s0x%08X", bx_mnem[ctx->instr_code & 3], dst);
}
-void opc_sc(PPCDisasmContext* ctx)
-{
+void opc_sc(PPCDisasmContext* ctx) {
ctx->instr_str = my_sprintf("%-8s", "sc");
}
-void opc_group19(PPCDisasmContext* ctx)
-{
+void opc_group19(PPCDisasmContext* ctx) {
auto rb = (ctx->instr_code >> 11) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto rs = (ctx->instr_code >> 21) & 0x1F;
- int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
+ int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
char operand1[12] = "";
char operand2[12] = "";
char operand3[12] = "";
@@ -778,8 +790,7 @@ void opc_group19(PPCDisasmContext* ctx)
case 33:
if (ctx->simplified && (ra == rb)) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crnor", operand1, operand2, operand3);
- }
- else {
+ } else {
fmt_threeop_crb(ctx->instr_str, "crnor", rs, ra, rb);
}
return;
@@ -789,8 +800,7 @@ void opc_group19(PPCDisasmContext* ctx)
case 129:
if (ctx->simplified) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crandc", operand1, operand2, operand3);
- }
- else {
+ } else {
fmt_threeop_crb(ctx->instr_str, "crandc", rs, ra, rb);
}
return;
@@ -801,8 +811,7 @@ void opc_group19(PPCDisasmContext* ctx)
if (ctx->simplified && (rs == ra) && (rs == rb)) {
ctx->instr_str = my_sprintf("%-8scrb%d", "crclr", rs);
return;
- }
- else if (ctx->simplified && ((rs != ra) || (rs != rb))) {
+ } else if (ctx->simplified && ((rs != ra) || (rs != rb))) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crxor", operand1, operand2, operand3);
return;
}
@@ -811,16 +820,14 @@ void opc_group19(PPCDisasmContext* ctx)
case 225:
if (ctx->simplified) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crnand", operand1, operand2, operand3);
- }
- else {
+ } else {
fmt_threeop_crb(ctx->instr_str, "crnand", rs, ra, rb);
}
return;
case 257:
if (ctx->simplified) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crand", operand1, operand2, operand3);
- }
- else {
+ } else {
fmt_threeop_crb(ctx->instr_str, "crand", rs, ra, rb);
}
return;
@@ -828,8 +835,7 @@ void opc_group19(PPCDisasmContext* ctx)
if (ctx->simplified && (rs == ra) && (rs == rb)) {
ctx->instr_str = my_sprintf("%-8scrb%d", "crset", rs);
return;
- }
- else if (ctx->simplified && ((rs != ra) || (rs != rb))) {
+ } else if (ctx->simplified && ((rs != ra) || (rs != rb))) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "creqv", operand1, operand2, operand3);
return;
}
@@ -838,8 +844,7 @@ void opc_group19(PPCDisasmContext* ctx)
case 417:
if (ctx->simplified) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "crorc", operand1, operand2, operand3);
- }
- else {
+ } else {
fmt_threeop_crb(ctx->instr_str, "crorc", rs, ra, rb);
}
return;
@@ -847,8 +852,7 @@ void opc_group19(PPCDisasmContext* ctx)
if (ctx->simplified && (ra == rb)) {
ctx->instr_str = my_sprintf("%-8scrb%d, crb%d", "crmove", rs, ra);
return;
- }
- else if (ctx->simplified && (ra!= rb)) {
+ } else if (ctx->simplified && (ra != rb)) {
ctx->instr_str = my_sprintf("%-8s%s, %s, %s", "cror", operand1, operand2, operand3);
return;
}
@@ -861,25 +865,23 @@ void opc_group19(PPCDisasmContext* ctx)
}
-void opc_group31(PPCDisasmContext* ctx)
-{
+void opc_group31(PPCDisasmContext* ctx) {
char opcode[10] = "";
auto rb = (ctx->instr_code >> 11) & 0x1F;
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto rs = (ctx->instr_code >> 21) & 0x1F;
- int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
- int index = ext_opc >> 5;
+ int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
+ int index = ext_opc >> 5;
bool rc_set = ctx->instr_code & 1;
switch (ext_opc & 0x1F) {
- case 8: /* subtracts & friends */
+ case 8: /* subtracts & friends */
index &= 0xF; /* strip OE bit */
if (!strlen(opc_subs[index])) {
opc_illegal(ctx);
- }
- else {
+ } else {
strcpy(opcode, opc_subs[index]);
if (ext_opc & 0x200) /* check OE bit */
strcat(opcode, "o");
@@ -891,18 +893,16 @@ void opc_group31(PPCDisasmContext* ctx)
opc_illegal(ctx);
else
fmt_twoop(ctx->instr_str, opcode, rs, ra);
- }
- else
+ } else
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
}
return;
- case 10: /* additions */
+ case 10: /* additions */
index &= 0xF; /* strip OE bit */
if (index > 8 || !strlen(opc_adds[index])) {
opc_illegal(ctx);
- }
- else {
+ } else {
strcpy(opcode, opc_adds[index]);
if (ext_opc & 0x200) /* check OE bit */
strcat(opcode, "o");
@@ -913,18 +913,16 @@ void opc_group31(PPCDisasmContext* ctx)
opc_illegal(ctx);
else
fmt_twoop(ctx->instr_str, opcode, rs, ra);
- }
- else
+ } else
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
}
return;
- case 11: /* integer multiplications and divisions */
+ case 11: /* integer multiplications and divisions */
index &= 0xF; /* strip OE bit */
if (!strlen(opc_muldivs[index])) {
opc_illegal(ctx);
- }
- else {
+ } else {
strcpy(opcode, opc_muldivs[index]);
if (ext_opc & 0x200) /* check OE bit */
strcat(opcode, "o");
@@ -944,29 +942,23 @@ void opc_group31(PPCDisasmContext* ctx)
opc_illegal(ctx);
else
ctx->instr_str = my_sprintf("%-8sr%d", "mtmsr", rs);
- }
- else if (index == 6) { /* mtsr */
+ } else if (index == 6) { /* mtsr */
if (ra & 16)
opc_illegal(ctx);
else
ctx->instr_str = my_sprintf("%-8s%d, r%d", "mtsr", ra, rs);
- }
- else if (index == 7) { /* mtsrin */
+ } else if (index == 7) { /* mtsrin */
ctx->instr_str = my_sprintf("%-8sr%d, r%d", "mtsrin", rs, rb);
- }
- else if (index == 9) { /* tlbie */
+ } else if (index == 9) { /* tlbie */
ctx->instr_str = my_sprintf("%-8sr%d", "tlbie", rb);
- }
- else if (index == 11) { /* tlbia */
+ } else if (index == 11) { /* tlbia */
ctx->instr_str = my_sprintf("%-8s", "tlbia");
- }
- else if (index == 30) { /* tlbld - 603 only */
+ } else if (index == 30) { /* tlbld - 603 only */
if (!rs & !ra)
opc_illegal(ctx);
else
ctx->instr_str = my_sprintf("%-8sr%s", "tlbld", rb);
- }
- else if (index == 30) { /* tlbli - 603 only */
+ } else if (index == 30) { /* tlbli - 603 only */
if (!rs & !ra)
opc_illegal(ctx);
else
@@ -981,15 +973,12 @@ void opc_group31(PPCDisasmContext* ctx)
strcat(opcode, ".");
- if ((index == 0) | (index == 4) | (index == 6) | (index == 16) \
- | (index == 20) | (index == 22) | (index == 24) | (index == 28)) {
+ if ((index == 0) | (index == 4) | (index == 6) | (index == 16) | (index == 20) |
+ (index == 22) | (index == 24) | (index == 28)) {
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
- }
- else if ((index == 5) | (index == 7) | (index == 21) \
- | (index == 23) | (index == 25) | (index == 29)) {
+ } else if ((index == 5) | (index == 7) | (index == 21) | (index == 23) | (index == 25) | (index == 29)) {
fmt_threeop_simm(ctx->instr_str, opcode, ra, rs, rb);
- }
- else {
+ } else {
opc_illegal(ctx);
}
@@ -1001,11 +990,10 @@ void opc_group31(PPCDisasmContext* ctx)
if (rc_set)
strcat(opcode, ".");
- if ((index == 4) | (index == 6) | (index == 16) \
- | (index == 20) | (index == 22) | (index == 28)){
+ if ((index == 4) | (index == 6) | (index == 16) | (index == 20) | (index == 22) |
+ (index == 28)) {
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
- }
- else{
+ } else {
opc_illegal(ctx);
}
@@ -1030,13 +1018,11 @@ void opc_group31(PPCDisasmContext* ctx)
case 0x1C: /* logical instructions */
if (index == 13 && rs == rb && ctx->simplified) {
fmt_twoop(ctx->instr_str, rc_set ? "mr." : "mr", ra, rs);
- }
- else {
+ } else {
strcpy(opcode, opc_logic[index]);
if (!strlen(opcode)) {
opc_illegal(ctx);
- }
- else {
+ } else {
if (rc_set)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
@@ -1045,13 +1031,12 @@ void opc_group31(PPCDisasmContext* ctx)
return;
- case 0x17: /* indexed load/store instructions */
+ case 0x17: /* indexed load/store instructions */
if (index == 30) { /* stfiwx sneaks in here */
if (rc_set) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sf%d, 0, r%d", opc_idx_ldst[index], rs, rb);
else {
@@ -1071,10 +1056,8 @@ void opc_group31(PPCDisasmContext* ctx)
fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
return;
- }
- else {
- ctx->instr_str = my_sprintf("%-8sf%d, r%d, r%d", \
- opc_idx_ldst[index], rs, ra, rb);
+ } else {
+ ctx->instr_str = my_sprintf("%-8sf%d, r%d, r%d", opc_idx_ldst[index], rs, ra, rb);
}
return;
@@ -1085,8 +1068,7 @@ void opc_group31(PPCDisasmContext* ctx)
if (!rc_set) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", opcode, rs, rb);
else
@@ -1095,56 +1077,49 @@ void opc_group31(PPCDisasmContext* ctx)
}
}
/* eciwx, ecowx, lhbrx, lwbrx, stwbrx, sthbrx */
- else if ((index == 9) | (index == 13) | (index == 16) \
- | (index == 20) | (index == 24) | (index == 28)) {
+ else if ((index == 9) | (index == 13) | (index == 16) | (index == 20) | (index == 24) | (index == 28)) {
if (rc_set) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", opcode, rs, rb);
else
fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
return;
}
- }
- else if ((index == 18) | (index == 26)) { /* sync, eieio */
+ } else if ((index == 18) | (index == 26)) { /* sync, eieio */
ctx->instr_str = my_sprintf("%-8s", opcode);
return;
}
/* dcba, dcbf, dcbi, dcbst, dcbt, dcbz, icbi */
- else if ((index == 1) | (index == 2) | (index == 7) \
- | (index == 8) | (index == 14) | (index == 23) \
- | (index == 30) | (index == 31)) {
+ else if (
+ (index == 1) | (index == 2) | (index == 7) | (index == 8) | (index == 14) |
+ (index == 23) | (index == 30) | (index == 31)) {
if (rc_set | (rs != 0)) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8s0, r%d", opcode, rb);
else
fmt_twoop(ctx->instr_str, opcode, ra, rb);
return;
}
- }
- else if (index == 17) { /* tlbsync */
+ } else if (index == 17) { /* tlbsync */
ctx->instr_str = my_sprintf("%-8s", opcode);
return;
- }
- else {
+ } else {
opc_illegal(ctx);
}
return;
break;
-
}
- auto ref_spr = (((ctx->instr_code >> 11) & 31) << 5) | ((ctx->instr_code >> 16) & 31);
+ auto ref_spr = (((ctx->instr_code >> 11) & 31) << 5) | ((ctx->instr_code >> 16) & 31);
auto spr_high = (ctx->instr_code >> 11) & 31;
- auto spr_low = (ctx->instr_code >> 16) & 31;
+ auto spr_low = (ctx->instr_code >> 16) & 31;
switch (ext_opc) {
case 0: /* cmp */
@@ -1159,8 +1134,7 @@ void opc_group31(PPCDisasmContext* ctx)
if ((rs >> 2) == 0) {
ctx->instr_str = my_sprintf("%-8sr%d, r%d", "cmpw", ra, rb);
return;
- }
- else {
+ } else {
ctx->instr_str = my_sprintf("%-8scr%d, r%d, r%d", "cmpw", (rs >> 2), ra, rb);
return;
}
@@ -1172,8 +1146,7 @@ void opc_group31(PPCDisasmContext* ctx)
case 4: /* tw */
if (rc_set) {
opc_illegal(ctx);
- }
- else {
+ } else {
if (ctx->simplified) {
strcpy(opcode, trap_cond[rs]);
@@ -1181,7 +1154,6 @@ void opc_group31(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8sr%d, r%d", opcode, ra, rb);
break;
}
-
}
ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "tw", rs, ra, rb);
@@ -1193,8 +1165,7 @@ void opc_group31(PPCDisasmContext* ctx)
case 20: /* lwarx */
if (rc_set) {
opc_illegal(ctx);
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", "lwarx", rs, rb);
else
@@ -1227,12 +1198,12 @@ void opc_group31(PPCDisasmContext* ctx)
}
else {
- ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, r%d", "cmpl", (rs >> 2), (rs & 1), ra, rb);
+ ctx->instr_str = my_sprintf(
+ "%-8scr%d, %d, r%d, r%d", "cmpl", (rs >> 2), (rs & 1), ra, rb);
}
break;
case 83: /* mfmsr */
- ctx->instr_str = my_sprintf("%-8sr%d", "mfmsr",
- (ctx->instr_code >> 21) & 0x1F);
+ ctx->instr_str = my_sprintf("%-8sr%d", "mfmsr", (ctx->instr_code >> 21) & 0x1F);
break;
case 144: /* mtcrf */
if (ctx->instr_code & 0x100801)
@@ -1241,8 +1212,8 @@ void opc_group31(PPCDisasmContext* ctx)
if (((ctx->instr_code >> 12) & 0xFF) == 0xFF)
ctx->instr_str = my_sprintf("%-8sr%d", "mtcr", rs);
else
- ctx->instr_str = my_sprintf("%-8s0x%02X, r%d", "mtcrf",
- (ctx->instr_code >> 12) & 0xFF, rs);
+ ctx->instr_str = my_sprintf(
+ "%-8s0x%02X, r%d", "mtcrf", (ctx->instr_code >> 12) & 0xFF, rs);
}
break;
case 277: /* lscbx */
@@ -1294,8 +1265,7 @@ void opc_group31(PPCDisasmContext* ctx)
if (ctx->simplified) {
if (ref_spr == 268) {
fmt_oneop(ctx->instr_str, "mftbl", rs);
- }
- else if (ref_spr == 269) {
+ } else if (ref_spr == 269) {
fmt_oneop(ctx->instr_str, "mftbu", rs);
}
return;
@@ -1353,8 +1323,7 @@ void opc_group31(PPCDisasmContext* ctx)
case 533: /* lswx */
if (rc_set) {
opc_illegal(ctx);
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", "lswx", rs, rb);
else
@@ -1378,8 +1347,7 @@ void opc_group31(PPCDisasmContext* ctx)
case 597: /* lswi */
if (rc_set) {
opc_illegal(ctx);
- }
- else {
+ } else {
if (rb == 0)
rb = 32;
@@ -1396,8 +1364,7 @@ void opc_group31(PPCDisasmContext* ctx)
if (rc_set) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (ra == 0)
ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", "stswx", rs, rb);
else
@@ -1409,8 +1376,7 @@ void opc_group31(PPCDisasmContext* ctx)
if (rc_set) {
opc_illegal(ctx);
return;
- }
- else {
+ } else {
if (rb == 0)
rb = 32;
@@ -1426,8 +1392,7 @@ void opc_group31(PPCDisasmContext* ctx)
}
}
-void opc_group59(PPCDisasmContext* ctx)
-{
+void opc_group59(PPCDisasmContext* ctx) {
char opcode[10] = "";
auto rc = (ctx->instr_code >> 6) & 0x1F;
@@ -1435,7 +1400,7 @@ void opc_group59(PPCDisasmContext* ctx)
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto rs = (ctx->instr_code >> 21) & 0x1F;
- int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
+ int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
bool rc_set = ctx->instr_code & 1;
switch (ext_opc & 0x1F) {
@@ -1569,8 +1534,7 @@ void opc_group59(PPCDisasmContext* ctx)
}
}
-void opc_group63(PPCDisasmContext* ctx)
-{
+void opc_group63(PPCDisasmContext* ctx) {
char opcode[10] = "";
auto rc = (ctx->instr_code >> 6) & 0x1F;
@@ -1578,7 +1542,7 @@ void opc_group63(PPCDisasmContext* ctx)
auto ra = (ctx->instr_code >> 16) & 0x1F;
auto rs = (ctx->instr_code >> 21) & 0x1F;
- int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
+ int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
bool rc_set = ctx->instr_code & 1;
switch (ext_opc & 0x1F) {
@@ -1819,78 +1783,64 @@ void opc_group63(PPCDisasmContext* ctx)
}
}
-void opc_intldst(PPCDisasmContext* ctx)
-{
+void opc_intldst(PPCDisasmContext* ctx) {
int32_t opcode = (ctx->instr_code >> 26) - 32;
- int32_t ra = (ctx->instr_code >> 16) & 0x1F;
- int32_t rd = (ctx->instr_code >> 21) & 0x1F;
- int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
+ int32_t ra = (ctx->instr_code >> 16) & 0x1F;
+ int32_t rd = (ctx->instr_code >> 21) & 0x1F;
+ int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
/* ra = 0 is forbidden for loads and stores with update */
/* ra = rd is forbidden for loads with update */
- if (((opcode < 14) && (opcode & 5) == 1 && ra == rd) || ((opcode & 1) && !ra))
- {
+ if (((opcode < 14) && (opcode & 5) == 1 && ra == rd) || ((opcode & 1) && !ra)) {
opc_illegal(ctx);
return;
}
if (ra) {
- ctx->instr_str = my_sprintf("%-8sr%d, %s0x%X(r%d)", opc_int_ldst[opcode],
- rd, ((imm < 0) ? "-" : ""), abs(imm), ra);
- }
- else {
- ctx->instr_str = my_sprintf("%-8sr%d, %s0x%X", opc_int_ldst[opcode],
- rd, ((imm < 0) ? "-" : ""), abs(imm));
+ ctx->instr_str = my_sprintf(
+ "%-8sr%d, %s0x%X(r%d)", opc_int_ldst[opcode], rd, ((imm < 0) ? "-" : ""), abs(imm), ra);
+ } else {
+ ctx->instr_str = my_sprintf(
+ "%-8sr%d, %s0x%X", opc_int_ldst[opcode], rd, ((imm < 0) ? "-" : ""), abs(imm));
}
}
-void opc_fltldst(PPCDisasmContext* ctx)
-{
+void opc_fltldst(PPCDisasmContext* ctx) {
int32_t opcode = (ctx->instr_code >> 26) - 48;
- int32_t ra = (ctx->instr_code >> 16) & 0x1F;
- int32_t rd = (ctx->instr_code >> 21) & 0x1F;
- int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
+ int32_t ra = (ctx->instr_code >> 16) & 0x1F;
+ int32_t rd = (ctx->instr_code >> 21) & 0x1F;
+ int32_t imm = SIGNEXT(ctx->instr_code & 0xFFFF, 15);
/* ra = 0 is forbidden for loads and stores with update */
/* ra = rd is forbidden for loads with update */
- if ((((opcode == 1) || (opcode == 3)) && ra == rd) || ((opcode & 1) && !ra))
- {
+ if ((((opcode == 1) || (opcode == 3)) && ra == rd) || ((opcode & 1) && !ra)) {
opc_illegal(ctx);
return;
}
if (ra) {
- ctx->instr_str = my_sprintf("%-8sf%d, %s0x%X(r%d)", opc_flt_ldst[opcode],
- rd, ((imm < 0) ? "-" : ""), abs(imm), ra);
- }
- else {
- ctx->instr_str = my_sprintf("%-8sf%d, %s0x%X", opc_flt_ldst[opcode],
- rd, ((imm < 0) ? "-" : ""), abs(imm));
+ ctx->instr_str = my_sprintf(
+ "%-8sf%d, %s0x%X(r%d)", opc_flt_ldst[opcode], rd, ((imm < 0) ? "-" : ""), abs(imm), ra);
+ } else {
+ ctx->instr_str = my_sprintf(
+ "%-8sf%d, %s0x%X", opc_flt_ldst[opcode], rd, ((imm < 0) ? "-" : ""), abs(imm));
}
}
/** main dispatch table. */
static std::function OpcodeDispatchTable[64] = {
- opc_illegal, opc_illegal, opc_illegal, opc_twi,
- opc_group4, opc_illegal, opc_illegal, opc_ar_im,
- opc_ar_im, power_dozi, opc_cmp_i_li, opc_cmp_i_li,
- opc_ar_im, opc_ar_im, opc_ar_im, opc_ar_im,
- opc_bcx, opc_sc, opc_bx, opc_group19,
- opc_rlwimi, opc_rlwinm, opc_rlmi, opc_rlwnm,
- opc_bool_im, opc_bool_im, opc_bool_im, opc_bool_im,
- opc_bool_im, opc_bool_im, opc_illegal, opc_group31,
- opc_intldst, opc_intldst, opc_intldst, opc_intldst,
- opc_intldst, opc_intldst, opc_intldst, opc_intldst,
- opc_intldst, opc_intldst, opc_intldst, opc_intldst,
- opc_intldst, opc_intldst, opc_intldst, opc_intldst,
- opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst,
- opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst,
- opc_illegal, opc_illegal, opc_illegal, opc_group59,
- opc_illegal, opc_illegal, opc_illegal, opc_group63
-};
+ opc_illegal, opc_illegal, opc_illegal, opc_twi, opc_group4, opc_illegal, opc_illegal,
+ opc_ar_im, opc_ar_im, power_dozi, opc_cmp_i_li, opc_cmp_i_li, opc_ar_im, opc_ar_im,
+ opc_ar_im, opc_ar_im, opc_bcx, opc_sc, opc_bx, opc_group19, opc_rlwimi,
+ opc_rlwinm, opc_rlmi, opc_rlwnm, opc_bool_im, opc_bool_im, opc_bool_im, opc_bool_im,
+ opc_bool_im, opc_bool_im, opc_illegal, opc_group31, opc_intldst, opc_intldst, opc_intldst,
+ opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_intldst,
+ opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_intldst, opc_fltldst,
+ opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst, opc_fltldst,
+ opc_illegal, opc_illegal, opc_illegal, opc_group59, opc_illegal, opc_illegal, opc_illegal,
+ opc_group63};
-string disassemble_single(PPCDisasmContext* ctx)
-{
+string disassemble_single(PPCDisasmContext* ctx) {
if (ctx->instr_addr & 3) {
throw std::invalid_argument(string("PPC instruction address must be a multiply of 4!"));
}
diff --git a/cpu/ppc/ppcdisasm.h b/cpu/ppc/ppcdisasm.h
index 58b5dda..bfc200c 100644
--- a/cpu/ppc/ppcdisasm.h
+++ b/cpu/ppc/ppcdisasm.h
@@ -26,17 +26,17 @@ along with this program. If not, see .
#include
typedef struct PPCDisasmContext {
- uint32_t instr_addr;
- uint32_t instr_code;
+ uint32_t instr_addr;
+ uint32_t instr_code;
std::string instr_str;
- bool simplified; /* true if we should output simplified mnemonics */
+ bool simplified; /* true if we should output simplified mnemonics */
} PPCDisasmContext;
-std::string disassemble_single(PPCDisasmContext *ctx);
+std::string disassemble_single(PPCDisasmContext* ctx);
int test_ppc_disasm(void);
/** sign-extend an integer. */
-#define SIGNEXT(x, sb) ((x) | (((x) & (1 << (sb))) ? ~((1 << (sb))-1) : 0))
+#define SIGNEXT(x, sb) ((x) | (((x) & (1 << (sb))) ? ~((1 << (sb)) - 1) : 0))
#endif /* PPCDISASM_H */
diff --git a/cpu/ppc/ppcemu.h b/cpu/ppc/ppcemu.h
index 163491b..29d464b 100644
--- a/cpu/ppc/ppcemu.h
+++ b/cpu/ppc/ppcemu.h
@@ -22,22 +22,22 @@ along with this program. If not, see .
#ifndef PPCEMU_H
#define PPCEMU_H
-#include
-#include
-#include
-#include "endianswap.h"
#include "devices/memctrlbase.h"
+#include "endianswap.h"
+#include
+#include
+#include
-//Uncomment this to help debug the emulator further
+// Uncomment this to help debug the emulator further
//#define EXHAUSTIVE_DEBUG 1
-//Uncomment this to have a more graceful approach to illegal opcodes
+// Uncomment this to have a more graceful approach to illegal opcodes
//#define ILLEGAL_OP_SAFE 1
-//Uncomment this to use GCC built-in functions.
+// Uncomment this to use GCC built-in functions.
//#define USE_GCC_BUILTINS 1
-//Uncomment this to use Visual Studio built-in functions.
+// Uncomment this to use Visual Studio built-in functions.
//#define USE_VS_BUILTINS 1
enum endian_switch { big_end = 0, little_end = 1 };
@@ -45,8 +45,8 @@ enum endian_switch { big_end = 0, little_end = 1 };
typedef void (*PPCOpcode)(void);
union FPR_storage {
- double dbl64_r; // double floating-point representation
- uint64_t int64_r; // double integer representation
+ double dbl64_r; // double floating-point representation
+ uint64_t int64_r; // double integer representation
};
/**
@@ -65,7 +65,7 @@ fpscr = FP Status and Condition Register
typedef struct struct_ppc_state {
FPR_storage fpr[32];
- uint32_t pc; //Referred as the CIA in the PPC manual
+ uint32_t pc; // Referred as the CIA in the PPC manual
uint32_t gpr[32];
uint32_t cr;
uint32_t fpscr;
@@ -73,7 +73,7 @@ typedef struct struct_ppc_state {
uint32_t spr[1024];
uint32_t msr;
uint32_t sr[16];
- bool reserve; //reserve bit used for lwarx and stcwx
+ bool reserve; // reserve bit used for lwarx and stcwx
} SetPRS;
extern SetPRS ppc_state;
@@ -94,10 +94,7 @@ enum SPR : int {
};
/** symbolic names for frequently used SPRs */
-enum TBR : int {
- TBL = 0,
- TBU = 1
-};
+enum TBR : int { TBL = 0, TBU = 1 };
/** symbolic names for common PPC processors */
enum PPC_VER : uint32_t {
@@ -147,10 +144,10 @@ SUPERVISOR MODEL
536 - 543 are the Data BAT registers
**/
-extern uint32_t opcode_value; //used for interpreting opcodes
-extern uint64_t timebase_counter; //used for storing time base value
+extern uint32_t opcode_value; // used for interpreting opcodes
+extern uint64_t timebase_counter; // used for storing time base value
-//Additional steps to prevent overflow?
+// Additional steps to prevent overflow?
extern int32_t add_result;
extern int32_t simult_result;
extern uint32_t uiadd_result;
@@ -176,19 +173,19 @@ extern uint32_t rot_mb;
extern uint32_t rot_me;
extern uint32_t uimm;
extern uint32_t grab_sr;
-extern uint32_t grab_inb; //This is for grabbing the number of immediate bytes for loading and storing
+extern uint32_t grab_inb; // This is for grabbing the number of immediate bytes for loading and storing
extern uint32_t ppc_to;
extern int32_t simm;
extern int32_t adr_li;
extern int32_t br_bd;
-//Used for GP calcs
+// Used for GP calcs
extern uint32_t ppc_result_a;
extern uint32_t ppc_result_b;
extern uint32_t ppc_result_c;
extern uint32_t ppc_result_d;
-//Used for FP calcs
+// Used for FP calcs
extern uint64_t ppc_result64_a;
extern uint64_t ppc_result64_b;
extern uint64_t ppc_result64_c;
@@ -197,7 +194,7 @@ extern uint64_t ppc_result64_d;
/* The precise end of a basic block. */
enum class BB_end_kind {
- BB_NONE = 0, /* no basic block end is reached */
+ BB_NONE = 0, /* no basic block end is reached */
BB_BRANCH = 1, /* a branch instruction is encountered */
BB_EXCEPTION, /* an exception is occured */
BB_RFI /* the rfi instruction is encountered */
@@ -215,10 +212,10 @@ enum class Except_Type {
EXC_NO_FPU,
EXC_DECR,
EXC_SYSCALL = 12,
- EXC_TRACE = 13
+ EXC_TRACE = 13
};
-//extern bool bb_end;
+// extern bool bb_end;
extern BB_end_kind bb_kind;
extern jmp_buf exc_env;
@@ -229,23 +226,23 @@ extern bool grab_return;
extern bool power_on;
-extern bool is_601; //For PowerPC 601 Emulation
-extern bool is_gekko; //For GameCube Emulation
-extern bool is_altivec; //For Altivec Emulation
-extern bool is_64bit; //For PowerPC G5 Emulation
+extern bool is_601; // For PowerPC 601 Emulation
+extern bool is_gekko; // For GameCube Emulation
+extern bool is_altivec; // For Altivec Emulation
+extern bool is_64bit; // For PowerPC G5 Emulation
-//Important Addressing Integers
+// Important Addressing Integers
extern uint32_t ppc_cur_instruction;
extern uint32_t ppc_effective_address;
extern uint32_t ppc_next_instruction_address;
-//Profiling Stats
+// Profiling Stats
extern uint32_t mmu_translations_num;
extern uint32_t exceptions_performed;
extern uint32_t supervisor_inst_num;
-//Function prototypes
-extern void ppc_cpu_init(MemCtrlBase *mem_ctrl, uint32_t proc_version);
+// Function prototypes
+extern void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t proc_version);
extern void ppc_mmu_init();
void ppc_illegalop();
@@ -293,15 +290,13 @@ void ppc_fp_changecrf1();
void ppc_tbr_update();
/* Exception handlers. */
-[[noreturn]] void ppc_exception_handler(Except_Type exception_type,
- uint32_t srr1_bits);
-[[noreturn]] void dbg_exception_handler(Except_Type exception_type,
- uint32_t srr1_bits);
+[[noreturn]] void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
+[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits);
-//MEMORY DECLARATIONS
+// MEMORY DECLARATIONS
extern MemCtrlBase* mem_ctrl_instance;
-//The functions used by the PowerPC processor
+// The functions used by the PowerPC processor
extern void ppc_bcctr();
extern void ppc_bcctrl();
extern void ppc_bclr();
@@ -599,7 +594,7 @@ extern void ppc_fsqrtsdot();
extern void ppc_fcmpo();
extern void ppc_fcmpu();
-//Power-specific instructions
+// Power-specific instructions
extern void power_abs();
extern void power_absdot();
extern void power_abso();
@@ -667,17 +662,17 @@ extern void power_srlqdot();
extern void power_srq();
extern void power_srqdot();
-//Gekko instructions
+// Gekko instructions
extern void ppc_psq_l();
extern void ppc_psq_lu();
extern void ppc_psq_st();
extern void ppc_psq_stu();
-//AltiVec instructions
+// AltiVec instructions
-//64-bit instructions
+// 64-bit instructions
-//G5+ instructions
+// G5+ instructions
extern void ppc_main_opcode(void);
extern void ppc_exec(void);
@@ -685,9 +680,9 @@ extern void ppc_exec_single(void);
extern void ppc_exec_until(uint32_t goal_addr);
/* debugging support API */
-void print_gprs(void); /* print content of the general purpose registers */
-void print_fprs(void); /* print content of the floating-point registers */
-uint64_t get_reg(std::string ®_name); /* get content of the register reg_name */
-void set_reg(std::string ®_name, uint64_t val); /* set reg_name to val */
+void print_gprs(void); /* print content of the general purpose registers */
+void print_fprs(void); /* print content of the floating-point registers */
+uint64_t get_reg(std::string& reg_name); /* get content of the register reg_name */
+void set_reg(std::string& reg_name, uint64_t val); /* set reg_name to val */
#endif /* PPCEMU_H */
diff --git a/cpu/ppc/ppcexceptions.cpp b/cpu/ppc/ppcexceptions.cpp
index 6216ea7..715c743 100644
--- a/cpu/ppc/ppcexceptions.cpp
+++ b/cpu/ppc/ppcexceptions.cpp
@@ -21,92 +21,89 @@ along with this program. If not, see .
/** @file Handling of low-level PPC exceptions. */
-#include
-#include
-#include
#include "ppcemu.h"
+#include
+#include
+#include
jmp_buf exc_env; /* Global exception environment. */
-[[noreturn]] void ppc_exception_handler(Except_Type exception_type,
- uint32_t srr1_bits)
-{
+[[noreturn]] void ppc_exception_handler(Except_Type exception_type, uint32_t srr1_bits) {
grab_exception = true;
- #ifdef PROFILER
+#ifdef PROFILER
exceptions_performed++;
- #endif
+#endif
bb_kind = BB_end_kind::BB_EXCEPTION;
- switch(exception_type) {
- case Except_Type::EXC_SYSTEM_RESET:
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0100;
- break;
+ switch (exception_type) {
+ case Except_Type::EXC_SYSTEM_RESET:
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0100;
+ break;
- case Except_Type::EXC_MACHINE_CHECK:
- if (!(ppc_state.msr & 0x1000)) {
- /* TODO: handle internal checkstop */
- }
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0200;
- break;
+ case Except_Type::EXC_MACHINE_CHECK:
+ if (!(ppc_state.msr & 0x1000)) {
+ /* TODO: handle internal checkstop */
+ }
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0200;
+ break;
- case Except_Type::EXC_DSI:
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0300;
- break;
+ case Except_Type::EXC_DSI:
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0300;
+ break;
- case Except_Type::EXC_ISI:
- ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
- ppc_next_instruction_address = 0x0400;
- break;
+ case Except_Type::EXC_ISI:
+ ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
+ ppc_next_instruction_address = 0x0400;
+ break;
- case Except_Type::EXC_EXT_INT:
- ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
- ppc_next_instruction_address = 0x0500;
- break;
+ case Except_Type::EXC_EXT_INT:
+ ppc_state.spr[SPR::SRR0] = ppc_next_instruction_address;
+ ppc_next_instruction_address = 0x0500;
+ break;
- case Except_Type::EXC_ALIGNMENT:
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0600;
- break;
+ case Except_Type::EXC_ALIGNMENT:
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0600;
+ break;
- case Except_Type::EXC_PROGRAM:
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0700;
- break;
+ case Except_Type::EXC_PROGRAM:
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0700;
+ break;
- case Except_Type::EXC_NO_FPU:
- ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
- ppc_next_instruction_address = 0x0800;
- break;
+ case Except_Type::EXC_NO_FPU:
+ ppc_state.spr[SPR::SRR0] = ppc_state.pc & 0xFFFFFFFC;
+ ppc_next_instruction_address = 0x0800;
+ break;
- case Except_Type::EXC_DECR:
- ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
- ppc_next_instruction_address = 0x0900;
- break;
+ case Except_Type::EXC_DECR:
+ ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
+ ppc_next_instruction_address = 0x0900;
+ break;
- case Except_Type::EXC_SYSCALL:
- ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
- ppc_next_instruction_address = 0x0C00;
- break;
+ case Except_Type::EXC_SYSCALL:
+ ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
+ ppc_next_instruction_address = 0x0C00;
+ break;
- case Except_Type::EXC_TRACE:
- ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
- ppc_next_instruction_address = 0x0D00;
- break;
+ case Except_Type::EXC_TRACE:
+ ppc_state.spr[SPR::SRR0] = (ppc_state.pc & 0xFFFFFFFC) + 4;
+ ppc_next_instruction_address = 0x0D00;
+ break;
- default:
- //printf("Unknown exception occured: %X\n", exception_type);
- //exit(-1);
- break;
+ default:
+ // printf("Unknown exception occured: %X\n", exception_type);
+ // exit(-1);
+ break;
}
ppc_state.spr[SPR::SRR1] = (ppc_state.msr & 0x0000FF73) | srr1_bits;
ppc_state.msr &= 0xFFFB1041;
/* copy MSR[ILE] to MSR[LE] */
- ppc_state.msr = (ppc_state.msr & 0xFFFFFFFE) |
- ((ppc_state.msr >> 16) & 1);
+ ppc_state.msr = (ppc_state.msr & 0xFFFFFFFE) | ((ppc_state.msr >> 16) & 1);
if (ppc_state.msr & 0x40) {
ppc_next_instruction_address |= 0xFFF00000;
@@ -116,61 +113,59 @@ jmp_buf exc_env; /* Global exception environment. */
}
-[[noreturn]] void dbg_exception_handler(Except_Type exception_type,
- uint32_t srr1_bits)
-{
+[[noreturn]] void dbg_exception_handler(Except_Type exception_type, uint32_t srr1_bits) {
std::string exc_descriptor;
- switch(exception_type) {
- case Except_Type::EXC_SYSTEM_RESET:
- exc_descriptor = "System reset exception occured";
- break;
+ switch (exception_type) {
+ case Except_Type::EXC_SYSTEM_RESET:
+ exc_descriptor = "System reset exception occured";
+ break;
- case Except_Type::EXC_MACHINE_CHECK:
- exc_descriptor = "Machine check exception occured";
- break;
+ case Except_Type::EXC_MACHINE_CHECK:
+ exc_descriptor = "Machine check exception occured";
+ break;
- case Except_Type::EXC_DSI:
- case Except_Type::EXC_ISI:
- if (ppc_state.spr[SPR::DSISR] & 0x40000000)
- exc_descriptor = "DSI/ISI exception: unmapped memory access";
- else if (ppc_state.spr[SPR::DSISR] & 0x08000000)
- exc_descriptor = "DSI/ISI exception: access protection violation";
- else {
- if (exception_type == Except_Type::EXC_DSI)
- exc_descriptor = "DSI exception";
- else
- exc_descriptor = "ISI exception";
- }
- break;
+ case Except_Type::EXC_DSI:
+ case Except_Type::EXC_ISI:
+ if (ppc_state.spr[SPR::DSISR] & 0x40000000)
+ exc_descriptor = "DSI/ISI exception: unmapped memory access";
+ else if (ppc_state.spr[SPR::DSISR] & 0x08000000)
+ exc_descriptor = "DSI/ISI exception: access protection violation";
+ else {
+ if (exception_type == Except_Type::EXC_DSI)
+ exc_descriptor = "DSI exception";
+ else
+ exc_descriptor = "ISI exception";
+ }
+ break;
- case Except_Type::EXC_EXT_INT:
- exc_descriptor = "External interrupt exception occured";
- break;
+ case Except_Type::EXC_EXT_INT:
+ exc_descriptor = "External interrupt exception occured";
+ break;
- case Except_Type::EXC_ALIGNMENT:
- exc_descriptor = "Alignment exception occured";
- break;
+ case Except_Type::EXC_ALIGNMENT:
+ exc_descriptor = "Alignment exception occured";
+ break;
- case Except_Type::EXC_PROGRAM:
- exc_descriptor = "Program exception occured";
- break;
+ case Except_Type::EXC_PROGRAM:
+ exc_descriptor = "Program exception occured";
+ break;
- case Except_Type::EXC_NO_FPU:
- exc_descriptor = "Floating-Point unavailable exception occured";
- break;
+ case Except_Type::EXC_NO_FPU:
+ exc_descriptor = "Floating-Point unavailable exception occured";
+ break;
- case Except_Type::EXC_DECR:
- exc_descriptor = "Decrementer exception occured";
- break;
+ case Except_Type::EXC_DECR:
+ exc_descriptor = "Decrementer exception occured";
+ break;
- case Except_Type::EXC_SYSCALL:
- exc_descriptor = "Syscall exception occured";
- break;
+ case Except_Type::EXC_SYSCALL:
+ exc_descriptor = "Syscall exception occured";
+ break;
- case Except_Type::EXC_TRACE:
- exc_descriptor = "Trace exception occured";
- break;
+ case Except_Type::EXC_TRACE:
+ exc_descriptor = "Trace exception occured";
+ break;
}
throw std::invalid_argument(exc_descriptor);
diff --git a/cpu/ppc/ppcexec.cpp b/cpu/ppc/ppcexec.cpp
index 2278f08..98bb803 100644
--- a/cpu/ppc/ppcexec.cpp
+++ b/cpu/ppc/ppcexec.cpp
@@ -19,23 +19,23 @@ You should have received a copy of the GNU General Public License
along with this program. If not, see .
*/
-#include
+#include
+#include
+#include
+#include