Refactor the interpreter, part 1: loads and stores.
This commit is contained in:
Maxim Poliakovski
parent
7bdad7703c
commit
0d5817042e
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@ -0,0 +1,61 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_DEFS_H
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#define PPC_DEFS_H
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#include <cinttypes>
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#define GET_rD_rA_OFFS(opcode) \
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uint32_t reg_d = ((opcode) >> 21) & 31; \
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uint32_t reg_a = ((opcode) >> 16) & 31; \
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int32_t offs = (int32_t)((int16_t)((opcode) & 0xFFFF));
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#define GET_GPR(reg) ppc_state.gpr[(reg)]
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#define SET_GPR(reg, val) ppc_state.gpr[(reg)] = (val)
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#define GET_rD_iA_iB(opcode) \
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uint32_t reg_d = ((opcode) >> 21) & 31; \
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uint32_t imm_a = ppc_state.gpr[((opcode) >> 16) & 31]; \
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uint32_t imm_b = ppc_state.gpr[((opcode) >> 11) & 31];
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#define GET_rD_rA_iA_iB(opcode) \
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uint32_t reg_d = ((opcode) >> 21) & 31; \
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uint32_t reg_a = ((opcode) >> 16) & 31; \
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uint32_t imm_a = ppc_state.gpr[reg_a]; \
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uint32_t imm_b = ppc_state.gpr[((opcode) >> 11) & 31];
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#define GET_rA_iS(opcode) \
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uint32_t reg_a = ((opcode) >> 16) & 31; \
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uint32_t imm_d = ppc_state.gpr[((opcode) >> 21) & 31];
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#define GET_rS_rA_OFFS(opcode) \
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uint32_t reg_s = ((opcode) >> 21) & 31; \
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uint32_t reg_a = ((opcode) >> 16) & 31; \
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int32_t offs = (int32_t)((int16_t)((opcode) & 0xFFFF));
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#define GET_rS_rA_iA_iB(opcode) \
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uint32_t reg_s = ((opcode) >> 21) & 31; \
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uint32_t reg_a = ((opcode) >> 16) & 31; \
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uint32_t imm_a = ppc_state.gpr[reg_a]; \
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uint32_t imm_b = ppc_state.gpr[((opcode) >> 11) & 31];
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#endif // PPC_DEFS_H
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@ -505,14 +505,16 @@ extern void ppc_bcl();
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extern void ppc_bcla();
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extern void ppc_cmpi();
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extern void ppc_cmpli();
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extern void ppc_lbz();
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extern void ppc_lbzu();
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extern void ppc_lha();
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extern void ppc_lhau();
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extern void ppc_lhz();
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extern void ppc_lhzu();
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extern void ppc_lwz();
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extern void ppc_lwzu();
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template <class T> void ppc_lz(void);
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template <class T> void ppc_lzu(void);
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template <class T> void ppc_lzux(void);
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template <class T> void ppc_lzx(void);
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template <class T> void ppc_st(void);
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template <class T> void ppc_stu(void);
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template <class T> void ppc_stux(void);
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template <class T> void ppc_stx(void);
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extern void ppc_lmw();
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extern void ppc_mulli();
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extern void ppc_ori();
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@ -522,12 +524,6 @@ extern void ppc_rlwimi();
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extern void ppc_rlwinm();
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extern void ppc_rlwnm();
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extern void ppc_sc();
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extern void ppc_stb();
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extern void ppc_stbu();
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extern void ppc_sth();
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extern void ppc_sthu();
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extern void ppc_stw();
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extern void ppc_stwu();
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extern void ppc_stmw();
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extern void ppc_subfic();
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extern void ppc_twi();
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@ -136,9 +136,9 @@ static PPCOpcode OpcodeGrabber[] = {
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ppc_addic, ppc_addicdot, ppc_addi, ppc_addis, ppc_opcode16, ppc_sc,
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ppc_opcode18, ppc_opcode19, ppc_rlwimi, ppc_rlwinm, power_rlmi, ppc_rlwnm,
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ppc_ori, ppc_oris, ppc_xori, ppc_xoris, ppc_andidot, ppc_andisdot,
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ppc_illegalop, ppc_opcode31, ppc_lwz, ppc_lwzu, ppc_lbz, ppc_lbzu,
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ppc_stw, ppc_stwu, ppc_stb, ppc_stbu, ppc_lhz, ppc_lhzu,
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ppc_lha, ppc_lhau, ppc_sth, ppc_sthu, ppc_lmw, ppc_stmw,
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ppc_illegalop, ppc_opcode31, ppc_lz<uint32_t>, ppc_lzu<uint32_t>, ppc_lz<uint8_t>, ppc_lzu<uint8_t>,
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ppc_st<uint32_t>, ppc_stu<uint32_t>, ppc_st<uint8_t>, ppc_stu<uint8_t>, ppc_lz<uint16_t>, ppc_lzu<uint16_t>,
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ppc_lha, ppc_lhau, ppc_st<uint16_t>, ppc_stu<uint16_t>, ppc_lmw, ppc_stmw,
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ppc_lfs, ppc_lfsu, ppc_lfd, ppc_lfdu, ppc_stfs, ppc_stfsu,
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ppc_stfd, ppc_stfdu, ppc_illegalop, ppc_illegalop, ppc_illegalop, ppc_opcode59,
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ppc_illegalop, ppc_illegalop, ppc_illegalop, ppc_opcode63};
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@ -818,12 +818,12 @@ void initialize_ppc_opcode_tables() {
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SubOpcode31Grabber[491] = SubOpcode31Grabber[1003] = ppc_divw;
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SubOpcode31Grabber[20] = ppc_lwarx;
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SubOpcode31Grabber[23] = ppc_lwzx;
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SubOpcode31Grabber[55] = ppc_lwzux;
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SubOpcode31Grabber[87] = ppc_lbzx;
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SubOpcode31Grabber[119] = ppc_lbzux;
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SubOpcode31Grabber[279] = ppc_lhzx;
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SubOpcode31Grabber[311] = ppc_lhzux;
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SubOpcode31Grabber[23] = ppc_lzx<uint32_t>;
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SubOpcode31Grabber[55] = ppc_lzux<uint32_t>;
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SubOpcode31Grabber[87] = ppc_lzx<uint8_t>;
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SubOpcode31Grabber[119] = ppc_lzux<uint8_t>;
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SubOpcode31Grabber[279] = ppc_lzx<uint16_t>;
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SubOpcode31Grabber[311] = ppc_lzux<uint16_t>;
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SubOpcode31Grabber[343] = ppc_lhax;
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SubOpcode31Grabber[375] = ppc_lhaux;
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SubOpcode31Grabber[533] = ppc_lswx;
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@ -836,12 +836,12 @@ void initialize_ppc_opcode_tables() {
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SubOpcode31Grabber[790] = ppc_lhbrx;
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SubOpcode31Grabber[150] = ppc_stwcx;
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SubOpcode31Grabber[151] = ppc_stwx;
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SubOpcode31Grabber[183] = ppc_stwux;
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SubOpcode31Grabber[215] = ppc_stbx;
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SubOpcode31Grabber[247] = ppc_stbux;
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SubOpcode31Grabber[407] = ppc_sthx;
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SubOpcode31Grabber[439] = ppc_sthux;
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SubOpcode31Grabber[151] = ppc_stx<uint32_t>;
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SubOpcode31Grabber[183] = ppc_stux<uint32_t>;
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SubOpcode31Grabber[215] = ppc_stx<uint8_t>;
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SubOpcode31Grabber[247] = ppc_stux<uint8_t>;
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SubOpcode31Grabber[407] = ppc_stx<uint16_t>;
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SubOpcode31Grabber[439] = ppc_stux<uint16_t>;
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SubOpcode31Grabber[661] = ppc_stswx;
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SubOpcode31Grabber[662] = ppc_stwbrx;
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SubOpcode31Grabber[663] = ppc_stfsx;
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@ -21,6 +21,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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// General opcodes for the processor - ppcopcodes.cpp
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#include "ppcdefs.h"
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#include "ppcemu.h"
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#include "ppcmmu.h"
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#include <array>
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@ -1415,203 +1416,112 @@ void dppc_interpreter::ppc_dcbz() {
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// Integer Load and Store Functions
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void dppc_interpreter::ppc_stb() {
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template <class T>
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void dppc_interpreter::ppc_st() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssa();
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ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
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ppc_effective_address += reg_a ? ppc_result_a : 0;
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mmu_write_vmem<uint8_t>(ppc_effective_address, ppc_result_d);
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//mem_write_byte(ppc_effective_address, ppc_result_d);
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GET_rS_rA_OFFS(ppc_cur_instruction);
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uint32_t ea = offs + (reg_a ? GET_GPR(reg_a) : 0);
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mmu_write_vmem<T>(ea, GET_GPR(reg_s));
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}
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void dppc_interpreter::ppc_stbx() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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mmu_write_vmem<uint8_t>(ppc_effective_address, ppc_result_d);
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//mem_write_byte(ppc_effective_address, ppc_result_d);
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}
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// explicitely instantiate all required ppc_st variants
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template void dppc_interpreter::ppc_st<uint8_t>(void); // stb
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template void dppc_interpreter::ppc_st<uint16_t>(void); // sth
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template void dppc_interpreter::ppc_st<uint32_t>(void); // stw
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void dppc_interpreter::ppc_stbu() {
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template <class T>
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void dppc_interpreter::ppc_stu() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssa();
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if (reg_a != 0) {
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ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
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ppc_effective_address += ppc_result_a;
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mmu_write_vmem<uint8_t>(ppc_effective_address, ppc_result_d);
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//mem_write_byte(ppc_effective_address, ppc_result_d);
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ppc_state.gpr[reg_a] = ppc_effective_address;
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} else {
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GET_rS_rA_OFFS(ppc_cur_instruction);
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if (!reg_a) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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uint32_t ea = offs + GET_GPR(reg_a);
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mmu_write_vmem<T>(ea, GET_GPR(reg_s));
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SET_GPR(reg_a, ea);
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}
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void dppc_interpreter::ppc_stbux() {
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// explicitely instantiate all required ppc_stu variants
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template void dppc_interpreter::ppc_stu<uint8_t>(void); // stbu
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template void dppc_interpreter::ppc_stu<uint16_t>(void); // sthu
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template void dppc_interpreter::ppc_stu<uint32_t>(void); // stwu
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template <class T>
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void dppc_interpreter::ppc_stx() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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if (reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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mmu_write_vmem<uint8_t>(ppc_effective_address, ppc_result_d);
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//mem_write_byte(ppc_effective_address, ppc_result_d);
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ppc_state.gpr[reg_a] = ppc_effective_address;
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} else {
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GET_rS_rA_iA_iB(ppc_cur_instruction);
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uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
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mmu_write_vmem<T>(ea, GET_GPR(reg_s));
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}
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// explicitely instantiate all required ppc_stx variants
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template void dppc_interpreter::ppc_stx<uint8_t>(void); // stbx
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template void dppc_interpreter::ppc_stx<uint16_t>(void); // sthx
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template void dppc_interpreter::ppc_stx<uint32_t>(void); // stwx
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template <class T>
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void dppc_interpreter::ppc_stux() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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GET_rS_rA_iA_iB(ppc_cur_instruction);
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if (!reg_a) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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uint32_t ea = imm_a + imm_b;
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mmu_write_vmem<T>(ea, GET_GPR(reg_s));
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SET_GPR(reg_a, ea);
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}
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void dppc_interpreter::ppc_sth() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssa();
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ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
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ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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}
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// explicitely instantiate all required ppc_stux variants
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template void dppc_interpreter::ppc_stux<uint8_t>(void); // stbux
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template void dppc_interpreter::ppc_stux<uint16_t>(void); // sthux
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template void dppc_interpreter::ppc_stux<uint32_t>(void); // stwux
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void dppc_interpreter::ppc_sthu() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssa();
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if (reg_a != 0) {
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ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
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ppc_effective_address += ppc_result_a;
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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ppc_state.gpr[reg_a] = ppc_effective_address;
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} else {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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}
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void dppc_interpreter::ppc_sthux() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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if (reg_a != 0) {
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ppc_effective_address = ppc_result_a + ppc_result_b;
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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ppc_state.gpr[reg_a] = ppc_effective_address;
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} else {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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}
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void dppc_interpreter::ppc_sthx() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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}
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void dppc_interpreter::ppc_sthbrx() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
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ppc_result_d = (uint32_t)(BYTESWAP_16((uint16_t)ppc_result_d));
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mmu_write_vmem<uint16_t>(ppc_effective_address, ppc_result_d);
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//mem_write_word(ppc_effective_address, ppc_result_d);
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}
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void dppc_interpreter::ppc_stw() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssa();
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ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
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ppc_effective_address += reg_a ? ppc_result_a : 0;
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
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//mem_write_dword(ppc_effective_address, ppc_result_d);
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}
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void dppc_interpreter::ppc_stwx() {
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#ifdef CPU_PROFILING
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num_int_stores++;
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#endif
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ppc_grab_regssab();
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ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
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mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
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//mem_write_dword(ppc_effective_address, ppc_result_d);
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}
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void dppc_interpreter::ppc_stwcx() {
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#ifdef CPU_PROFILING
|
||||
num_int_stores++;
|
||||
#endif
|
||||
// PLACEHOLDER CODE FOR STWCX - We need to check for reserve memory
|
||||
if (rc_flag == 0) {
|
||||
ppc_illegalop();
|
||||
} else {
|
||||
ppc_grab_regssab();
|
||||
ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
|
||||
if (ppc_state.reserve) {
|
||||
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
|
||||
//mem_write_dword(ppc_effective_address, ppc_result_d);
|
||||
ppc_state.cr |= (ppc_state.spr[SPR::XER] & 0x80000000) ? 0x30000000 : 0x20000000;
|
||||
ppc_state.reserve = false;
|
||||
} else {
|
||||
ppc_state.cr |= (ppc_state.spr[SPR::XER] & 0x80000000) ? 0x10000000 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_stwu() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_stores++;
|
||||
#endif
|
||||
ppc_grab_regssa();
|
||||
if (reg_a != 0) {
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += ppc_result_a;
|
||||
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
|
||||
//mem_write_dword(ppc_effective_address, ppc_result_d);
|
||||
ppc_state.gpr[reg_a] = ppc_effective_address;
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_stwux() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_stores++;
|
||||
#endif
|
||||
ppc_grab_regssab();
|
||||
if (reg_a != 0) {
|
||||
ppc_effective_address = ppc_result_a + ppc_result_b;
|
||||
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
|
||||
//mem_write_dword(ppc_effective_address, ppc_result_d);
|
||||
ppc_state.gpr[reg_a] = ppc_effective_address;
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
GET_rS_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
mmu_write_vmem<uint16_t>(ea, BYTESWAP_16((uint16_t)(GET_GPR(reg_s))));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_stwbrx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_stores++;
|
||||
#endif
|
||||
ppc_grab_regssab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
ppc_result_d = BYTESWAP_32(ppc_result_d);
|
||||
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
|
||||
//mem_write_dword(ppc_effective_address, ppc_result_d);
|
||||
GET_rS_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
mmu_write_vmem<uint32_t>(ea, BYTESWAP_32(GET_GPR(reg_s)));
|
||||
}
|
||||
|
||||
|
||||
void dppc_interpreter::ppc_stwcx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_stores++;
|
||||
#endif
|
||||
if (rc_flag == 0) {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
} else {
|
||||
// TODO: We need to check for memory reservation
|
||||
ppc_grab_regssab();
|
||||
ppc_effective_address = (reg_a == 0) ? ppc_result_b : (ppc_result_a + ppc_result_b);
|
||||
if (ppc_state.reserve) {
|
||||
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_result_d);
|
||||
ppc_state.cr |= (ppc_state.spr[SPR::XER] & 0x80000000) ? 0x30000000 : 0x20000000;
|
||||
ppc_state.reserve = false;
|
||||
} else {
|
||||
ppc_state.cr |= (ppc_state.spr[SPR::XER] & 0x80000000) ? 0x10000000 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_stmw() {
|
||||
|
|
@ -1634,277 +1544,136 @@ void dppc_interpreter::ppc_stmw() {
|
|||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lbz() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
|
||||
//ppc_result_d = mem_grab_byte(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lbzu() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address += ppc_result_a;
|
||||
//ppc_result_d = mem_grab_byte(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_regd();
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lbzx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//ppc_result_d = mem_grab_byte(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lbzux() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address = ppc_result_a + ppc_result_b;
|
||||
//ppc_result_d = mem_grab_byte(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint8_t>(ppc_effective_address);
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_regd();
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dppc_interpreter::ppc_lhz() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += reg_a ? ppc_result_a : 0;
|
||||
//ppc_result_d = mem_grab_word(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhzu() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += ppc_result_a;
|
||||
//ppc_result_d = mem_grab_word(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_regd();
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhzx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//ppc_result_d = mem_grab_word(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhzux() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address = ppc_result_a + ppc_result_b;
|
||||
//ppc_result_d = mem_grab_word(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_regd();
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lha() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
|
||||
//uint16_t val = mem_grab_word(ppc_effective_address);
|
||||
uint16_t val = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
if (val & 0x8000) {
|
||||
ppc_result_d = 0xFFFF0000UL | (uint32_t)val;
|
||||
} else {
|
||||
ppc_result_d = (uint32_t)val;
|
||||
}
|
||||
ppc_store_result_regd();
|
||||
GET_rD_rA_OFFS(ppc_cur_instruction);
|
||||
uint32_t ea = offs + ((reg_a) ? ppc_state.gpr[reg_a] : 0);
|
||||
SET_GPR(reg_d, (int32_t)((int16_t)mmu_read_vmem<uint16_t>(ea)));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhau() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += ppc_result_a;
|
||||
//uint16_t val = mem_grab_word(ppc_effective_address);
|
||||
uint16_t val = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
if (val & 0x8000) {
|
||||
ppc_result_d = 0xFFFF0000UL | (uint32_t)val;
|
||||
} else {
|
||||
ppc_result_d = (uint32_t)val;
|
||||
}
|
||||
ppc_store_result_regd();
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
GET_rD_rA_OFFS(ppc_cur_instruction);
|
||||
if ((reg_a == reg_d) || reg_a == 0) {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
uint32_t ea = offs + ppc_state.gpr[reg_a];
|
||||
SET_GPR(reg_d, (int32_t)((int16_t)mmu_read_vmem<uint16_t>(ea)));
|
||||
SET_GPR(reg_a, ea);
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhaux() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//uint16_t val = mem_grab_word(ppc_effective_address);
|
||||
uint16_t val = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
if (val & 0x8000) {
|
||||
ppc_result_d = 0xFFFF0000UL | (uint32_t)val;
|
||||
} else {
|
||||
ppc_result_d = (uint32_t)val;
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
if ((reg_a == reg_d) || reg_a == 0) {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
ppc_store_result_regd();
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_rega();
|
||||
uint32_t ea = imm_a + imm_b;
|
||||
SET_GPR(reg_d, (int32_t)((int16_t)mmu_read_vmem<uint16_t>(ea)));
|
||||
SET_GPR(reg_a, ea);
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhax() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//uint16_t val = mem_grab_word(ppc_effective_address);
|
||||
uint16_t val = mmu_read_vmem<uint16_t>(ppc_effective_address);
|
||||
if (val & 0x8000) {
|
||||
ppc_result_d = 0xFFFF0000UL | (uint32_t)val;
|
||||
} else {
|
||||
ppc_result_d = (uint32_t)val;
|
||||
}
|
||||
ppc_store_result_regd();
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
SET_GPR(reg_d, (int32_t)((int16_t)mmu_read_vmem<uint16_t>(ea)));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lhbrx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//ppc_result_d = (uint32_t)(BYTESWAP_16(mem_grab_word(ppc_effective_address)));
|
||||
ppc_result_d = (uint32_t)(BYTESWAP_16(mmu_read_vmem<uint16_t>(ppc_effective_address)));
|
||||
ppc_store_result_regd();
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lwz() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
ppc_effective_address += (reg_a > 0) ? ppc_result_a : 0;
|
||||
//ppc_result_d = mem_grab_dword(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
SET_GPR(reg_d, BYTESWAP_16(mmu_read_vmem<uint16_t>(ea)));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lwbrx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//ppc_result_d = BYTESWAP_32(mem_grab_dword(ppc_effective_address));
|
||||
ppc_result_d = BYTESWAP_32(mmu_read_vmem<uint32_t>(ppc_effective_address));
|
||||
ppc_store_result_regd();
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
SET_GPR(reg_d, BYTESWAP_32(mmu_read_vmem<uint32_t>(ea)));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lwzu() {
|
||||
template <class T>
|
||||
void dppc_interpreter::ppc_lz() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsda();
|
||||
ppc_effective_address = (int32_t)((int16_t)(ppc_cur_instruction & 0xFFFF));
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address += ppc_result_a;
|
||||
//ppc_result_d = mem_grab_dword(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_rega();
|
||||
} else {
|
||||
GET_rD_rA_OFFS(ppc_cur_instruction);
|
||||
uint32_t ea = offs + ((reg_a) ? ppc_state.gpr[reg_a] : 0);
|
||||
SET_GPR(reg_d, mmu_read_vmem<T>(ea));
|
||||
}
|
||||
|
||||
// explicitely instantiate all required ppc_lz variants
|
||||
template void dppc_interpreter::ppc_lz<uint8_t>(void); // lbz
|
||||
template void dppc_interpreter::ppc_lz<uint16_t>(void); // lhz
|
||||
template void dppc_interpreter::ppc_lz<uint32_t>(void); // lwz
|
||||
|
||||
template <class T>
|
||||
void dppc_interpreter::ppc_lzu() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
GET_rD_rA_OFFS(ppc_cur_instruction);
|
||||
if ((reg_a == reg_d) || reg_a == 0) {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
uint32_t ea = offs + ppc_state.gpr[reg_a];
|
||||
SET_GPR(reg_d, mmu_read_vmem<T>(ea));
|
||||
SET_GPR(reg_a, ea);
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lwzx() {
|
||||
// explicitely instantiate all required ppc_lzu variants
|
||||
template void dppc_interpreter::ppc_lzu<uint8_t>(void); // lbzu
|
||||
template void dppc_interpreter::ppc_lzu<uint16_t>(void); // lhzu
|
||||
template void dppc_interpreter::ppc_lzu<uint32_t>(void); // lwzu
|
||||
|
||||
template <class T>
|
||||
void dppc_interpreter::ppc_lzx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
ppc_effective_address = reg_a ? (ppc_result_a + ppc_result_b) : ppc_result_b;
|
||||
//ppc_result_d = mem_grab_dword(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
|
||||
ppc_store_result_regd();
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
uint32_t ea = imm_b + ((reg_a) ? imm_a : 0);
|
||||
SET_GPR(reg_d, mmu_read_vmem<T>(ea));
|
||||
}
|
||||
|
||||
void dppc_interpreter::ppc_lwzux() {
|
||||
// explicitely instantiate all required ppc_lzx variants
|
||||
template void dppc_interpreter::ppc_lzx<uint8_t>(void); // lbzx
|
||||
template void dppc_interpreter::ppc_lzx<uint16_t>(void); // lhzx
|
||||
template void dppc_interpreter::ppc_lzx<uint32_t>(void); // lwzx
|
||||
|
||||
template <class T>
|
||||
void dppc_interpreter::ppc_lzux() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
#endif
|
||||
ppc_grab_regsdab();
|
||||
if ((reg_a != reg_d) || reg_a != 0) {
|
||||
ppc_effective_address = ppc_result_a + ppc_result_b;
|
||||
} else {
|
||||
GET_rD_rA_iA_iB(ppc_cur_instruction);
|
||||
if ((reg_a == reg_d) || reg_a == 0) {
|
||||
ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
|
||||
}
|
||||
//ppc_result_d = mem_grab_dword(ppc_effective_address);
|
||||
ppc_result_d = mmu_read_vmem<uint32_t>(ppc_effective_address);
|
||||
ppc_result_a = ppc_effective_address;
|
||||
ppc_store_result_regd();
|
||||
ppc_store_result_rega();
|
||||
uint32_t ea = imm_a + imm_b;
|
||||
SET_GPR(reg_d, mmu_read_vmem<T>(ea));
|
||||
SET_GPR(reg_a, ea);
|
||||
}
|
||||
|
||||
// explicitely instantiate all required ppc_lzux variants
|
||||
template void dppc_interpreter::ppc_lzux<uint8_t>(void); // lbzux
|
||||
template void dppc_interpreter::ppc_lzux<uint16_t>(void); // lhzux
|
||||
template void dppc_interpreter::ppc_lzux<uint32_t>(void); // lwzux
|
||||
|
||||
void dppc_interpreter::ppc_lwarx() {
|
||||
#ifdef CPU_PROFILING
|
||||
num_int_loads++;
|
||||
|
|
|
|||
Loading…
Reference in New Issue