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Define and connect basic PowerMac 6100 hardware.
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parent
6ad38c9142
commit
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6
main.cpp
6
main.cpp
@ -26,6 +26,7 @@
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#include "mpc106.h"
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#include "openpic.h"
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#include "debugger.h"
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#include "pmac6100hw.h"
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//#include <vector>
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#define max_16b_int 65535
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@ -596,6 +597,8 @@ int main(int argc, char **argv)
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//Copy the contents of the IO data and the ROM to memory appropriate locations.
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romFile.read ((char *)machine_sysrom_mem,grab_sysrom_size);
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if (is_nubus)
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pmac6100_init();
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/*
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//Open the Disk File.
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@ -867,6 +870,9 @@ int main(int argc, char **argv)
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romFile.close();
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//Free memory after the emulation is completed.
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if (machine_phys_map)
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delete(machine_phys_map);
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free(machine_sysram_mem);
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free(machine_upperiocontrol_mem);
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free(machine_iocontrolcdma_mem);
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9
makefile
9
makefile
@ -1,11 +1,11 @@
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OBJS = main.o macioserial.o macscsi.o macswim3.o mpc106.o openpic.o poweropcodes.o \
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ppcfpopcodes.o ppcgekkoopcodes.o ppcmemory.o ppcopcodes.o viacuda.o davbus.o \
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debugger.o addressmap.o
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debugger.o addressmap.o pmac6100hw.o
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SOURCE = main.cpp macioserial.cpp macscsi.cpp macswim3.cpp mpc106.cpp openpic.cpp \
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poweropcodes.cpp ppcfpopcodes.cpp ppcgekkoopcodes.cpp ppcmemory.cpp \
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ppcopcodes.cpp viacuda.cpp davbus.cpp debugger.cpp addressmap.cpp
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ppcopcodes.cpp viacuda.cpp davbus.cpp debugger.cpp addressmap.cpp pmac6100hw.cpp
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HEADER = macioserial.h macscsi.h macswim3.h mpc106.h openpic.h ppcemumain.h ppcmemory.h \
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viacuda.h debugger.h addressmap.h
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viacuda.h debugger.h addressmap.h pmac6100hw.h
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OUT = dingusppc
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CC = g++
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FLAGS = -g -c -Wall -std=c++11
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@ -59,5 +59,8 @@ debugger.o: debugger.cpp
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addressmap.o: addressmap.cpp
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$(CC) $(FLAGS) addressmap.cpp
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pmac6100hw.o: pmac6100hw.cpp
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$(CC) $(FLAGS) pmac6100hw.cpp
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clean:
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rm -f $(OBJS) $(OUT)
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71
pmac6100hw.cpp
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71
pmac6100hw.cpp
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@ -0,0 +1,71 @@
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#include <iostream>
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#include "ppcemumain.h"
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#include "pmac6100hw.h"
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#include "addressmap.h"
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/** ======== High-speed memory controller (HMC) implementation ======== */
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HMC::HMC()
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{
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this->config_reg = 0ULL;
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this->bit_pos = 0;
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}
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uint32_t HMC::read(uint32_t offset, int size)
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{
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if (!offset)
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return !!(this->config_reg & (1ULL << this->bit_pos++));
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else
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return 0; /* FIXME: what should be returned for invalid offsets? */
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}
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void HMC::write(uint32_t offset, uint32_t value, int size)
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{
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uint64_t bit;
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switch(offset) {
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case 0:
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bit = 1ULL << this->bit_pos++;
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this->config_reg = (value & 1) ? this->config_reg | bit :
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this->config_reg & ~bit;
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break;
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case 8: /* writing to HMCBase + 8 resets internal bit position */
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this->bit_pos = 0;
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break;
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}
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}
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/** Initialize Power Macintosh 6100 hardware. */
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void pmac6100_init()
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{
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AddressMapEntry entry;
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machine_phys_map = new AddressMap();
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/* add ROM and its mirror */
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entry = {0xFFC00000, 0xFFFFFFFF, 0, RT_ROM, 0, machine_sysrom_mem};
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machine_phys_map->add(entry);
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entry = {0x40000000, 0x403FFFFF, 0, RT_MIRROR | RT_ROM, 0, machine_sysrom_mem};
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machine_phys_map->add(entry);
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/* add soldered on-board RAM. FIXME: do it properly using memory objects */
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entry = {0x00000000, 0x007FFFFF, 0, RT_RAM, 0, machine_sysram_mem};
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machine_phys_map->add(entry);
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/* this machine has two SIMM slots, each of them can hold max. 128 MB RAM */
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/* SIMM slot 2 physical range: 0x08000000 - 0x0FFFFFFF */
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/* SIMM slot 1 physical range: 0x10000000 - 0x17FFFFFF */
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/* TODO: make those SIMM slots end-user configurable */
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/* add high-speed memory controller I/O space */
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entry = {0x50F40000, 0x50F4FFFF, 0, RT_MMIO, new HMC()};
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machine_phys_map->add(entry);
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/* add read-only machine identification register */
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entry = {0x5FFFFFFC, 0x5FFFFFFF, 0, RT_MMIO, new CPUID(PM6100)};
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machine_phys_map->add(entry);
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printf("Machine initialization completed.\n");
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}
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45
pmac6100hw.h
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45
pmac6100hw.h
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#ifndef PMAC_6100_HW_H
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#define PMAC_6100_HW_H
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#include <cinttypes>
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#include "mmiodevice.h"
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/** Some Power macintosh IDs stored in the CPUID register */
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enum PMACID {
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PM6100 = 0x3010, /* PowerMac 6100 */
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PM7100 = 0x3012, /* PowerMac 7100 */
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PM8100 = 0x3013, /* PowerMac 8100 */
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};
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/** ======== High-speed memory controller (HMC) ======== */
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class HMC : public MMIODevice {
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public:
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HMC();
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~HMC() = default;
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uint32_t read(uint32_t offset, int size);
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void write(uint32_t offset, uint32_t value, int size);
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private:
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int bit_pos;
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uint64_t config_reg;
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};
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/** CPUID is a read-only register containing machine identification (see PMACID) */
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class CPUID : public MMIODevice {
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public:
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CPUID(const uint32_t id) {
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this->cpuid = (0xA55A << 16) | (id & 0xFFFF); };
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~CPUID() = default;
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uint32_t read(uint32_t offset, int size) {
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return (cpuid >> (3 - (offset & 3)) * 8) & 0xFF; };
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void write(uint32_t offset, uint32_t value, int size) {}; /* not writable */
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private:
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uint32_t cpuid;
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};
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void pmac6100_init(void);
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#endif /* PMAC_6100_HW_H */
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