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poweropcodes: Fix srea.

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Fix carry flag calculation. Anding with the rotation count (n = rB) is nonsensical.
(r & ~mask) is the rotated word ANDed with the complement of the generated mask of n zeros followed by 32 - n ones.
The manual says this 32-bit result is ORed together. This means all the bits are ORed together which is equivalent to saying 0 if all zeros and 1 if any ones. In other words: (r & ~mask) != 0.
This boolean is ANDed with bit 0 of rS to produce the carry. int32_t(rS) < 0 will test bit 0. The && operator will treat each side as a boolean so you can exclude "!= 0" tests.
This commit is contained in:
joevt 2024-04-09 02:41:33 -07:00 committed by dingusdev
parent a928c67913
commit 24bce16c4d
1 changed files with 4 additions and 2 deletions
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6
cpu/ppc/poweropcodes.cpp
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@ -565,9 +565,10 @@ void dppc_interpreter::power_srea() {
ppc_grab_regssab(ppc_cur_instruction);
unsigned rot_sh = ppc_result_b & 0x1F;
ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
uint32_t r = ((ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh)));
uint32_t mask = -1U >> rot_sh;
if ((int32_t(ppc_result_d) < 0) && (ppc_result_d & rot_sh)) {
if ((int32_t(ppc_result_d) < 0) && (r & ~mask)) {
ppc_state.spr[SPR::XER] |= XER::CA;
} else {
ppc_state.spr[SPR::XER] &= ~XER::CA;
@ -577,6 +578,7 @@ void dppc_interpreter::power_srea() {
ppc_changecrf0(ppc_result_a);
ppc_store_iresult_reg(reg_a, ppc_result_a);
ppc_state.spr[SPR::MQ] = r;
}
template void dppc_interpreter::power_srea<RC0>();