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GrandCentral: access to ESCC and board reg 1.

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This commit is contained in:
Maxim Poliakovski 2022-03-21 15:06:40 +01:00
parent ac5078f133
commit 29ce960dbf
2 changed files with 22 additions and 0 deletions
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21
devices/ioctrl/grandcentral.cpp
View File

@ -21,6 +21,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
#include <devices/ethernet/mace.h> #include <devices/ethernet/mace.h>
#include <devices/ioctrl/macio.h> #include <devices/ioctrl/macio.h>
#include <devices/serial/escc.h>
#include <endianswap.h> #include <endianswap.h>
#include <loguru.hpp> #include <loguru.hpp>
#include <machines/machinebase.h> #include <machines/machinebase.h>
@ -57,6 +58,8 @@ GrandCentral::GrandCentral() : PCIDevice("mac-io/grandcentral"), InterruptCtrl()
std::bind(&AwacsScreamer::dma_start, this->awacs.get()), std::bind(&AwacsScreamer::dma_start, this->awacs.get()),
std::bind(&AwacsScreamer::dma_end, this->awacs.get()) std::bind(&AwacsScreamer::dma_end, this->awacs.get())
); );
this->escc = std::unique_ptr<EsccController> (new EsccController());
} }
void GrandCentral::notify_bar_change(int bar_num) void GrandCentral::notify_bar_change(int bar_num)
@ -82,11 +85,20 @@ uint32_t GrandCentral::read(uint32_t reg_start, uint32_t offset, int size)
switch (subdev_num) { switch (subdev_num) {
case 1: // MACE case 1: // MACE
return this->mace->read((offset >> 4) & 0x1F); return this->mace->read((offset >> 4) & 0x1F);
case 2: // ESCC compatible addressing
if ((offset & 0xFF) < 16) {
return this->escc->read((offset >> 1) & 0xF);
}
// fallthrough
case 3: // ESCC MacRISC addressing
return this->escc->read((offset >> 4) & 0xF);
case 4: // AWACS case 4: // AWACS
return this->awacs->snd_ctrl_read(offset & 0xFF, size); return this->awacs->snd_ctrl_read(offset & 0xFF, size);
case 6: case 6:
case 7: // VIA-CUDA case 7: // VIA-CUDA
return this->viacuda->read((offset >> 9) & 0xF); return this->viacuda->read((offset >> 9) & 0xF);
case 0xA: // Board register 1 (IOBus dev #1)
return BYTESWAP_32(0x100);
case 0xF: // NVRAM Data (IOBus dev #6) case 0xF: // NVRAM Data (IOBus dev #6)
return this->nvram->read_byte( return this->nvram->read_byte(
(this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F)); (this->nvram_addr_hi << 5) + ((offset >> 4) & 0x1F));
@ -119,6 +131,15 @@ void GrandCentral::write(uint32_t reg_start, uint32_t offset, uint32_t value, in
case 1: // MACE registers case 1: // MACE registers
this->mace->write((offset >> 4) & 0x1F, value); this->mace->write((offset >> 4) & 0x1F, value);
break; break;
case 2: // ESCC compatible addressing
if ((offset & 0xFF) < 16) {
this->escc->write((offset >> 1) & 0xF, value);
break;
}
// fallthrough
case 3: // ESCC MacRISC addressing
this->escc->write((offset >> 4) & 0xF, value);
break;
case 4: // AWACS case 4: // AWACS
this->awacs->snd_ctrl_write(offset & 0xFF, value, size); this->awacs->snd_ctrl_write(offset & 0xFF, value, size);
break; break;

1
devices/ioctrl/macio.h
View File

@ -112,6 +112,7 @@ private:
std::unique_ptr<AwacsScreamer> awacs; // AWACS audio codec instance std::unique_ptr<AwacsScreamer> awacs; // AWACS audio codec instance
std::unique_ptr<ViaCuda> viacuda; // VIA cell with Cuda MCU attached to it std::unique_ptr<ViaCuda> viacuda; // VIA cell with Cuda MCU attached to it
std::unique_ptr<NVram> nvram; // NVRAM module std::unique_ptr<NVram> nvram; // NVRAM module
std::unique_ptr<EsccController> escc; // ESCC serial controller
std::unique_ptr<DMAChannel> snd_out_dma; std::unique_ptr<DMAChannel> snd_out_dma;
}; };