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Added to Heathrow

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Plus some debugging stuff to help figure out what register 0x34 is responsible for.
This commit is contained in:
dingusdev 2021-01-08 15:29:43 -07:00
parent df8ea1b276
commit 2bac606365
3 changed files with 21 additions and 14 deletions
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6
cpu/ppc/ppcemu.h
View File

@ -256,12 +256,8 @@ extern void ppc_mmu_init();
[[noreturn]] void ppc_illegalop();
[[noreturn]] void ppc_fpu_off();
void ppc_illegalsubop19();
void ppc_illegalsubop31();
void ppc_illegalsubop59();
void ppc_illegalsubop63();
void ppc_opcode4();
//void ppc_opcode4();
void ppc_opcode16();
void ppc_opcode18();
void ppc_opcode19();

27
devices/heathrow.cpp
View File

@ -27,6 +27,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
#include <cinttypes>
#include <iostream>
#include <thirdparty/loguru/loguru.hpp>
#include <cpu/ppc/ppcemu.h>
/** Heathrow Mac I/O device emulation.
@ -170,7 +171,7 @@ void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int
uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
uint32_t res = 0;
switch (offset & 0xFF) {
switch (offset & 0xFC) {
case 0x14:
LOG_F(9, "read from MIO:Int_Mask2 register \n");
res = this->int_mask2;
@ -196,14 +197,15 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
res = this->int_levels1;
break;
case 0x34: /* heathrowIDs / HEATHROW_MBCR (Linux): media bay config reg? */
res = 0xF0700000UL;
LOG_F(9, "read from MIO:ID register at Address %x \n", ppc_state.pc);
res = this->macio_id;
break;
case 0x38:
LOG_F(9, "read from MIO:Feat_Ctrl register \n");
res = this->feat_ctrl;
break;
default:
LOG_F(WARNING, "unknown MIO register at %x \n", offset);
LOG_F(WARNING, "read from unknown MIO register at %x \n", offset);
break;
}
@ -211,17 +213,17 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
}
void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
switch (offset & 0xFF) {
switch (offset & 0xFC) {
case 0x14:
LOG_F(9, "read from MIO:Int_Mask2 register \n");
LOG_F(9, "write %x to MIO:Int_Mask2 register \n", value);
this->int_mask2 = value;
break;
case 0x18:
LOG_F(9, "read from MIO:Int_Clear2 register \n");
LOG_F(9, "write %x to MIO:Int_Clear2 register \n", value);
this->int_clear2 = value;
break;
case 0x1C:
LOG_F(9, "read from MIO:Int_Levels2 register \n");
LOG_F(9, "write %x to MIO:Int_Levels2 register \n", value);
this->int_levels2 = value;
break;
case 0x24:
@ -233,15 +235,22 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
this->int_clear1 = value;
break;
case 0x2C:
LOG_F(9, "read from MIO:Int_Levels1 register \n");
LOG_F(9, "write %x to MIO:Int_Levels1 register \n", value);
this->int_levels1 = value;
break;
case 0x34:
LOG_F(WARNING, "Attempted to write %x to MIO:ID at %x; Address : %x \n", value, offset, ppc_state.pc);
break;
case 0x38:
LOG_F(9, "write %x to MIO:Feat_Ctrl register \n", value);
this->feat_ctrl = value;
break;
case 0x3C:
LOG_F(9, "write %x to MIO:Aux_Ctrl register \n", value);
this->aux_ctrl = value;
break;
default:
LOG_F(WARNING, "unknown MIO register at %x \n", offset);
LOG_F(WARNING, "write %x to unknown MIO register at %x \n", value, offset);
break;
}
}

2
devices/macio.h
View File

@ -141,7 +141,9 @@ private:
uint32_t int_mask1 = 0;
uint32_t int_clear1 = 0;
uint32_t int_levels1 = 0;
uint32_t macio_id = 0xF0700008UL;
uint32_t feat_ctrl = 0; // features control register
uint32_t aux_ctrl = 0; // aux features control register
/* device cells */
ViaCuda* viacuda; /* VIA cell with Cuda MCU attached to it */