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https://github.com/dingusdev/dingusppc.git
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atirage: calculation of display parameters.
This commit is contained in:
Maxim Poliakovski
parent
19ca37c4ba
commit
2f4a3b955e
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@ -28,6 +28,12 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <map>
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#include <thirdparty/loguru/loguru.hpp>
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/* Mach64 post dividers. */
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static const int mach64_post_div[8] = {
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1, 2, 4, 8, // standard post dividers
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3, 5, 6, 12 // alternate post dividers
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};
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/* Human readable Mach64 HW register names for easier debugging. */
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static const std::map<uint16_t, std::string> mach64_reg_names = {
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{0x0000, "CRTC_H_TOTAL_DISP"},
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@ -45,6 +51,10 @@ static const std::map<uint16_t, std::string> mach64_reg_names = {
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{0x0040, "OVR_CLR"},
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{0x0044, "OVR_WID_LEFT_RIGHT"},
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{0x0048, "OVR_WID_TOP_BOTTOM"},
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{0x0060, "CUR_CLR0"},
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{0x0064, "CUR_CLR1"},
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{0x0068, "CUR_OFFSET"},
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{0x006C, "CUR_HORZ_VERT_POSN"},
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{0x0078, "GP_IO"},
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{0x007C, "HW_DEBUG"},
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{0x0080, "SCRATCH_REG0"},
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@ -176,6 +186,13 @@ void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) {
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write_mem(&this->block_io_regs[offset], value, size);
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switch (offset & ~3) {
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case ATI_CRTC_GEN_CNTL:
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if (this->block_io_regs[ATI_CRTC_GEN_CNTL+3] & 2) {
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this->crtc_enable();
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} else {
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this->crtc_on = false;
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}
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break;
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case ATI_GP_IO:
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if (offset < (ATI_GP_IO + 2)) {
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gpio_val = READ_DWORD_LE_A(&this->block_io_regs[ATI_GP_IO]);
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@ -193,6 +210,9 @@ void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) {
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uint8_t pll_data = this->block_io_regs[ATI_CLOCK_CNTL+2];
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this->plls[pll_addr] = pll_data;
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LOG_F(INFO, "ATI Rage: PLL #%d set to 0x%02X", pll_addr, pll_data);
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} else if (offset == ATI_CLOCK_CNTL && size == 1) {
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LOG_F(INFO, "ATI Rage: CLOCK_SEL = 0x%02X",
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this->block_io_regs[ATI_CLOCK_CNTL] & 3);
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}
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break;
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case ATI_DAC_REGS:
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@ -384,3 +404,91 @@ void ATIRage::write(uint32_t reg_start, uint32_t offset, uint32_t value, int siz
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LOG_F(WARNING, "ATI Rage: write attempt to unmapped aperture region at 0x%08X", offset);
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}
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}
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float ATIRage::calc_pll_freq(int scale, int fb_div) {
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return (ATI_XTAL * scale * fb_div) / this->plls[PLL_REF_DIV];
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}
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void ATIRage::verbose_pixel_format(int crtc_index) {
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if (crtc_index) {
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LOG_F(ERROR, "CRTC2 not supported yet");
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return;
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}
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const char* what = "Pixel format:";
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switch (this->block_io_regs[ATI_CRTC_GEN_CNTL+1] & 7) {
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case 1:
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LOG_F(INFO, "%s 4 bpp with DAC palette", what);
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break;
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case 2:
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LOG_F(INFO, "%s 8 bpp with DAC palette", what);
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break;
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case 3:
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LOG_F(INFO, "%s 15 bpp direct color", what);
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break;
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case 4:
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LOG_F(INFO, "%s 16 bpp direct color", what);
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break;
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case 5:
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LOG_F(INFO, "%s 24 bpp direct color", what);
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break;
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case 6:
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LOG_F(INFO, "%s 32 bpp direct color", what);
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break;
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default:
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LOG_F(ERROR, "ATI Rage: CRTC pixel format %d not supported",
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this->block_io_regs[ATI_CRTC_GEN_CNTL+2] & 7);
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}
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}
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void ATIRage::crtc_enable() {
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/* active (visible) width is specified in characters (8 px) - 1 */
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this->active_width = (this->block_io_regs[ATI_CRTC_H_TOTAL_DISP+2] + 1) * 8;
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/* active (visible) height is specified in lines - 1 */
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this->active_height =
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(READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_V_TOTAL_DISP+2]) & 0x7FFUL) + 1;
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if ((this->plls[PLL_VCLK_CNTL] & 3) == 3) {
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/* look up which VPLL ouput is requested */
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int clock_sel = this->block_io_regs[ATI_CLOCK_CNTL] & 3;
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/* calculate VPLL output frequency */
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float vpll_freq = calc_pll_freq(2, this->plls[VCLK0_FB_DIV + clock_sel]);
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/* calculate post divider's index */
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/* NOTE: post divider's index has been extended by an additional
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bit in Rage Pro. This bit is resided in PLL_EXT_CNTL register.
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*/
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int post_div_idx = ((this->plls[PLL_EXT_CNTL] >> (clock_sel + 2)) & 4) |
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((this->plls[VCLK_POST_DIV] >> (clock_sel * 2)) & 3);
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/* pixel clock = source_freq / post_div */
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this->pixel_clock = vpll_freq / mach64_post_div[post_div_idx];
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/* calculate display refresh rate */
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int hori_total =
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((READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_H_TOTAL_DISP])
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& 0x1FFUL) + 1) * 8;
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int vert_total =
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(READ_WORD_LE_A(&this->block_io_regs[ATI_CRTC_V_TOTAL_DISP]) & 0x7FFUL) + 1;
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this->refresh_rate = pixel_clock / hori_total / vert_total;
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LOG_F(INFO, "ATI Rage: primary CRT controller enabled:");
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LOG_F(INFO, "Video mode: %s",
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(this->block_io_regs[ATI_CRTC_GEN_CNTL+3] & 1) ? "extended" : "VGA");
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LOG_F(INFO, "Video width: %d px", this->active_width);
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LOG_F(INFO, "Video height: %d px", this->active_height);
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verbose_pixel_format(0);
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LOG_F(INFO, "VPLL frequency: %f MHz", vpll_freq * 1e-6);
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LOG_F(INFO, "Pixel (dot) clock: %f MHz", this->pixel_clock * 1e-6);
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LOG_F(INFO, "Refresh rate: %f Hz", this->refresh_rate);
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} else {
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LOG_F(WARNING, "ATI Rage: VLCK source != VPLL!");
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}
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this->crtc_on = true;
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}
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@ -171,9 +171,23 @@ enum {
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ATI_TVO_CNTL = 0x0500,
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};
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/* Mach64 PLL register indices. */
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enum {
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PLL_REF_DIV = 2, // reference divider, same for all Mach64 clocks
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PLL_VCLK_CNTL = 5,
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VCLK_POST_DIV = 6,
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VCLK0_FB_DIV = 7, // feedback divider for VCLK0
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VCLK1_FB_DIV = 8, // feedback divider for VCLK1
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VCLK2_FB_DIV = 9, // feedback divider for VCLK2
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VCLK3_FB_DIV = 10, // feedback divider for VCLK3
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PLL_EXT_CNTL = 11,
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};
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constexpr auto APERTURE_SIZE = 0x01000000UL; /* Mach64 aperture size */
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constexpr auto MEMMAP_OFFSET = 0x007FFC00UL; /* offset to memory mapped registers */
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constexpr auto ATI_XTAL = 14318180.0f; // external crystal oscillator frequency
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class ATIRage : public PCIDevice {
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public:
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ATIRage(uint16_t dev_id, uint32_t mem_amount);
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@ -200,25 +214,28 @@ public:
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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protected:
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uint32_t size_dep_read(uint8_t* buf, uint32_t size);
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void size_dep_write(uint8_t* buf, uint32_t val, uint32_t size);
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const char* get_reg_name(uint32_t reg_offset);
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bool io_access_allowed(uint32_t offset, uint32_t* p_io_base);
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uint32_t read_reg(uint32_t offset, uint32_t size);
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void write_reg(uint32_t offset, uint32_t value, uint32_t size);
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float calc_pll_freq(int scale, int fb_div);
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void verbose_pixel_format(int crtc_index);
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void crtc_enable();
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private:
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// uint32_t atirage_membuf_regs[9]; /* ATI Rage Memory Buffer Registers */
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// uint32_t atirage_scratch_regs[4]; /* ATI Rage Scratch Registers */
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// uint32_t atirage_cmdfifo_regs[3]; /* ATI Rage Command FIFO Registers */
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// uint32_t atirage_datapath_regs[12]; /* ATI Rage Data Path Registers*/
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uint8_t block_io_regs[512] = {0};
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uint8_t pci_cfg[256] = {0}; /* PCI configuration space */
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uint8_t plls[64] = {0}; // internal PLL registers
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/* CRT controller parameters */
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bool crtc_on = false;
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int active_width; // width of the visible display area
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int active_height; // height of the visible display area
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float pixel_clock;
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float refresh_rate;
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/* Video RAM variables */
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uint32_t vram_size;
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uint8_t* vram_ptr;
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