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https://github.com/dingusdev/dingusppc.git
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Fix compilation with Clang 11.
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3c7fc58ac0
commit
331b93d4d6
@ -169,6 +169,7 @@ if (DPPC_BUILD_PPC_TESTS)
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TARGET testppc POST_BUILD
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TARGET testppc POST_BUILD
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COMMAND ${CMAKE_COMMAND} -E copy
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COMMAND ${CMAKE_COMMAND} -E copy
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"${PROJECT_SOURCE_DIR}/cpu/ppc/test/ppcinttests.csv"
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"${PROJECT_SOURCE_DIR}/cpu/ppc/test/ppcinttests.csv"
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"${PROJECT_SOURCE_DIR}/cpu/ppc/test/ppcfloattests.csv"
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"${PROJECT_SOURCE_DIR}/cpu/ppc/test/ppcdisasmtest.csv"
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"${PROJECT_SOURCE_DIR}/cpu/ppc/test/ppcdisasmtest.csv"
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$<TARGET_FILE_DIR:${PROJECT_NAME}>)
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$<TARGET_FILE_DIR:${PROJECT_NAME}>)
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endif()
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endif()
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@ -186,7 +186,7 @@ void update_fex() {
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}
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}
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template <typename T, const FPOP fpop>
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template <typename T, const FPOP fpop>
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constexpr auto ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chosen_reg_3) {
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void ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chosen_reg_3) {
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T input_a = T(ppc_state.fpr[chosen_reg_1].int64_r);
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T input_a = T(ppc_state.fpr[chosen_reg_1].int64_r);
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T input_b = T(ppc_state.fpr[chosen_reg_2].int64_r);
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T input_b = T(ppc_state.fpr[chosen_reg_2].int64_r);
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T input_c = T(ppc_state.fpr[chosen_reg_3].int64_r);
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T input_c = T(ppc_state.fpr[chosen_reg_3].int64_r);
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@ -243,7 +243,7 @@ constexpr auto ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chose
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update_fex();
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update_fex();
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break;
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break;
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}
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}
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}
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}
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void fpresult_update(double set_result, bool confirm_arc) {
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void fpresult_update(double set_result, bool confirm_arc) {
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bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW);
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bool confirm_ov = (bool)std::fetestexcept(FE_OVERFLOW);
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@ -279,9 +279,9 @@ void ppc_changecrf1() {
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// Floating Point Arithmetic
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// Floating Point Arithmetic
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void dppc_interpreter::ppc_fadd() {
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void dppc_interpreter::ppc_fadd() {
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ppc_grab_regsfpdab();
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ppc_grab_regsfpdab();
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ppc_dblresult64_d = val_reg_a + val_reg_b;
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ppc_dblresult64_d = val_reg_a + val_reg_b;
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if (!isnan(ppc_dblresult64_d)) {
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if (!isnan(ppc_dblresult64_d)) {
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ppc_store_dfpresult_flt(reg_d);
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ppc_store_dfpresult_flt(reg_d);
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} else {
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} else {
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@ -377,7 +377,7 @@ void dppc_interpreter::ppc_fnmadd() {
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if (!isnan(ppc_dblresult64_d)) {
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if (!isnan(ppc_dblresult64_d)) {
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ppc_store_dfpresult_flt(reg_d);
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ppc_store_dfpresult_flt(reg_d);
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}
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}
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else {
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else {
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ppc_confirm_inf_nan<double, FNMADD>(reg_a, reg_b, reg_c);
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ppc_confirm_inf_nan<double, FNMADD>(reg_a, reg_b, reg_c);
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}
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}
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@ -525,7 +525,7 @@ void dppc_interpreter::ppc_fnmsubs() {
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intermediate = -intermediate;
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intermediate = -intermediate;
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ppc_dblresult64_d = static_cast<double>(intermediate);
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ppc_dblresult64_d = static_cast<double>(intermediate);
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if (!isnan(ppc_dblresult64_d)) {
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if (!isnan(ppc_dblresult64_d)) {
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ppc_store_sfpresult_flt(reg_d);
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ppc_store_sfpresult_flt(reg_d);
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} else {
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} else {
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@ -639,7 +639,7 @@ void dppc_interpreter::ppc_fres() {
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}
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}
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else if (std::isnan(start_num)) {
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else if (std::isnan(start_num)) {
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ppc_state.fpscr |= FPSCR::VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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}
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}
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else if (std::isinf(start_num)){
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else if (std::isinf(start_num)){
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ppc_state.fpscr |= FPSCR::VXSNAN;
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ppc_state.fpscr |= FPSCR::VXSNAN;
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ppc_state.fpscr &= 0xFFF9FFFF;
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ppc_state.fpscr &= 0xFFF9FFFF;
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