mirror of
https://github.com/dingusdev/dingusppc.git
synced 2024-06-01 14:41:34 +00:00
Many new test cases, many fixes
This commit is contained in:
dingusdev
parent
d4239c5aa1
commit
3d89b0438a
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@ -159,7 +159,7 @@ void fmt_twoop_tospr(string& buf, const char* opc, int dst, int src)
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void fmt_twoop_flt(string& buf, const char* opc, int dst, int src1)
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{
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buf = my_sprintf("%-8sfr%d, fr%d", opc, dst, src1);
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buf = my_sprintf("%-8sf%d, f%d", opc, dst, src1);
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}
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void fmt_threeop(string& buf, const char* opc, int dst, int src1, int src2)
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@ -185,12 +185,12 @@ void fmt_threeop_simm(string& buf, const char* opc, int dst, int src1, int imm)
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void fmt_threeop_flt(string& buf, const char* opc, int dst, int src1, int src2)
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{
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buf = my_sprintf("%-8sfr%d, fr%d, fr%d", opc, dst, src1, src2);
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buf = my_sprintf("%-8sf%d, f%d, f%d", opc, dst, src1, src2);
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}
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void fmt_fourop_flt(string& buf, const char* opc, int dst, int src1, int src2, int src3)
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{
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buf = my_sprintf("%-8sfr%d, fr%d, fr%d, fr%d", opc, dst, src1, src2, src3);
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buf = my_sprintf("%-8sf%d, f%d, f%d, f%d", opc, dst, src1, src2, src3);
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}
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void fmt_rotateop(string& buf, const char* opc, int dst, int src, int sh, int mb, int me, bool imm)
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@ -917,31 +917,29 @@ void opc_group31(PPCDisasmContext* ctx)
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case 0x17: /* indexed load/store instructions */
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if (index == 30) { /* stfiwx sneaks in here */
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if (rc_set) {
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opc_illegal(ctx);
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return;
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}
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else {
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if (ra == 0)
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ctx->instr_str = my_sprintf("%-8sf%d, 0, r%d", opc_idx_ldst[index], rs, rb);
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else {
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ctx->instr_str = my_sprintf("%-8sf%d, r%d, r%d", opc_idx_ldst[index], rs, ra, rb);
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}
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return;
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}
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}
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if (index > 23 || rc_set || strlen(opc_idx_ldst[index]) == 0) {
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opc_illegal(ctx);
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return;
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}
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if (index < 16) {
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if (index == 30) { /* stfiwx sneaks in here */
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if (rc_set) {
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opc_illegal(ctx);
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return;
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}
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else {
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if (ra == 0)
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ctx->instr_str = my_sprintf("%-8sr%d, 0, r%d", opc_idx_ldst[index], rs, rb);
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else {
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fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
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}
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return;
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}
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}
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else {
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fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
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}
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fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
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}
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else {
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ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d",
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ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d", \
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opc_idx_ldst[index], rs, ra, rb);
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}
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return;
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@ -981,10 +979,10 @@ void opc_group31(PPCDisasmContext* ctx)
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ctx->instr_str = my_sprintf("%-8s", opcode);
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return;
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}
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/* dcba, dcbf, dcbi, dcbst, dcbt, dcbz, icbi */
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/* dcba, dcbf, dcbi, dcbst, dcbt, dcbz */
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else if ((index == 1) | (index == 2) | (index == 7) \
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| (index == 8) | (index == 14) \
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| (index == 23) | (index == 30) | (index == 31)) {
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| (index == 23) | (index == 31)) {
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if (rc_set | (rs != 0)) {
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opc_illegal(ctx);
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return;
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@ -997,6 +995,12 @@ void opc_group31(PPCDisasmContext* ctx)
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return;
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}
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}
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else if (index == 30) { /* icbi */
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if (rs == 0)
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opc_illegal(ctx);
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else
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fmt_twoop(ctx->instr_str, opcode, ra, rb);
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}
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else if (index == 17) { /* tlbsync */
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ctx->instr_str = my_sprintf("%-8s", opcode);
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}
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@ -1016,7 +1020,7 @@ void opc_group31(PPCDisasmContext* ctx)
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmp", rs, ra, rb);
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ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, r%d", "cmp", (rs >> 2), (rs & 1), ra, rb);
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break;
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case 4: /* tw */
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if (rc_set) {
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@ -1028,7 +1032,7 @@ void opc_group31(PPCDisasmContext* ctx)
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if (strlen(opcode) != 0) {
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ctx->instr_str = my_sprintf("%-8sr%d, r%d", opcode, ra, rb);
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return;
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break;
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}
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}
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@ -1051,12 +1055,13 @@ void opc_group31(PPCDisasmContext* ctx)
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}
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break;
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case 26: /* cntlzw */
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strcpy(opcode, "cntlzw");
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printf("CASE REACH! \n");
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if (rc_set)
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strcat(opcode, ".");
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fmt_twoop(ctx->instr_str, "cntlzw.", rs, ra);
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else
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fmt_twoop(ctx->instr_str, "cntlzw", rs, ra);
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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break;
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case 29: /* maskg */
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strcpy(opcode, "maskg");
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@ -1070,7 +1075,7 @@ void opc_group31(PPCDisasmContext* ctx)
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sr%d, r%d, r%d", "cmpl", rs, ra, rb);
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ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, r%d", "cmpl", (rs >> 2), (rs & 1), ra, rb);
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break;
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case 83: /* mfmsr */
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ctx->instr_str = my_sprintf("%-8sr%d", "mfmsr",
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@ -1087,6 +1092,18 @@ void opc_group31(PPCDisasmContext* ctx)
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case 146: /* mtmsr */
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fmt_oneop(ctx->instr_str, "mtmsr", rs);
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break;
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case 210: /* mtsr */
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if (ra & 16)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8%d, r%d", "mtsr", ra, rs);
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break;
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case 242: /* mtsrin */
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if (rb & 16)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8r%d, r%d", "mtsr", rs, rb);
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break;
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case 277: /* lscbx */
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strcpy(opcode, "lscbx");
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@ -1163,7 +1180,7 @@ void opc_group31(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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break;
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case 533: /* lswx */
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if (rc_set) {
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@ -1182,13 +1199,16 @@ void opc_group31(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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return;
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case 597: /* lswi */
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if (rc_set) {
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opc_illegal(ctx);
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}
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else {
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if (rb == 0)
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rb = 32;
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if (ra == 0)
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ctx->instr_str = my_sprintf("%-8sr%d, 0, %x", "lswi", rs, rb);
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else
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@ -1214,6 +1234,9 @@ void opc_group31(PPCDisasmContext* ctx)
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return;
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}
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else {
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if (rb == 0)
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rb = 32;
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if (ra == 0)
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ctx->instr_str = my_sprintf("%-8sr%d, 0, %d", "stswi", rs, rb);
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else
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@ -1327,7 +1350,7 @@ void opc_group59(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1339,7 +1362,7 @@ void opc_group59(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1351,7 +1374,7 @@ void opc_group59(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1363,7 +1386,7 @@ void opc_group59(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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}
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@ -1469,7 +1492,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if ((rc != 0) | (ra != 0))
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", opcode, rs, rb);
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ctx->instr_str = my_sprintf("%-8sf%d, f%d", opcode, rs, rb);
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return;
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@ -1479,7 +1502,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1489,7 +1512,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1499,7 +1522,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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@ -1509,7 +1532,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rb, rc);
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fmt_fourop_flt(ctx->instr_str, opcode, rs, ra, rc, rb);
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return;
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}
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@ -1521,7 +1544,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rs & 3)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8scr%d, r%d, r%d,", "fcmpu", (rs >> 2), ra, rb);
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ctx->instr_str = my_sprintf("%-8scr%d, f%d, f%d", "fcmpu", (rs >> 2), ra, rb);
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break;
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case 12: /* frsp */
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if (ra != 0)
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@ -1545,7 +1568,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rs & 3)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8scr%d, r%d, r%d,", "fcmpo", (rs >> 2), ra, rb);
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ctx->instr_str = my_sprintf("%-8scr%d, f%d, f%d", "fcmpo", (rs >> 2), ra, rb);
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break;
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case 38: /* mtfsb1 */
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strcpy(opcode, "mtfsb1");
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@ -1553,7 +1576,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if (rc_set)
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strcat(opcode, ".");
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ctx->instr_str = my_sprintf("%-8scrb%d", opcode, rs);
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ctx->instr_str = my_sprintf("%-8s%d", opcode, rs);
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break;
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case 40: /* fneg */
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strcpy(opcode, "fneg");
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@ -1595,13 +1618,13 @@ void opc_group63(PPCDisasmContext* ctx)
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if (ra != 0)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", "fnabs", rs, rb);
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ctx->instr_str = my_sprintf("%-8sf%d, f%d", "fnabs", rs, rb);
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break;
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case 264: /* fabs */
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if (ra != 0)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, fr%d, fr%d", "fabs", rs, rb);
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ctx->instr_str = my_sprintf("%-8s%d, f%d, f%d", "fabs", rs, rb);
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break;
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case 583: /* mffs */
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strcpy(opcode, "mffs");
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@ -1612,7 +1635,7 @@ void opc_group63(PPCDisasmContext* ctx)
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if ((ra != 0) | (rb != 0))
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8sfr%d", opcode, rs);
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ctx->instr_str = my_sprintf("%-8sf%d", opcode, rs);
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break;
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case 711: /* mtfsf */
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ctx->instr_str = my_sprintf("%-8sfm%d, r%d", "mtfsf", fm, rb);
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@ -1663,11 +1686,11 @@ void opc_fltldst(PPCDisasmContext* ctx)
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}
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if (ra) {
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ctx->instr_str = my_sprintf("%-8sfr%d, %s0x%X(r%d)", opc_flt_ldst[opcode],
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ctx->instr_str = my_sprintf("%-8sf%d, %s0x%X(r%d)", opc_flt_ldst[opcode],
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rd, ((imm < 0) ? "-" : ""), abs(imm), ra);
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}
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else {
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ctx->instr_str = my_sprintf("%-8sfr%d, %s0x%X", opc_flt_ldst[opcode],
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ctx->instr_str = my_sprintf("%-8sf%d, %s0x%X", opc_flt_ldst[opcode],
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rd, ((imm < 0) ? "-" : ""), abs(imm));
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}
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}
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@ -1,12 +1,13 @@
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# Test data for PowerPC disassembler supplied as comma-separated values
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# Data format:
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# instruction address (hex), instruction code (hex), expected disassembly: opcode, [operands...]
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# (lines starting with "#" will be treated as comments and ignored)
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# (lines starting with a hash sign (#) will be treated as comments and ignored)
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# unconditional branches
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0xFFF03008,0x48000355,bl,0xFFF0335C
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0xFFF03000,0x4280035C,b,0xFFF0335C
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0xFFF03000,0x48000802,ba,0x00000800
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0xFFF03000,0x48000803,bla,0x00000800
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# bcctr variants with simplified mnemonics
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0xFFF03000,0x4E800420,bctr
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@ -193,9 +194,16 @@
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0xFFF00100,0x7E007120,mtcrf,0x07,r16
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# rotation instructions
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0xFFF00100,0x5084442E,rlwimi,r4,r4,8,16,23
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0xFFF00100,0x5400EFFE,rlwinm,r0,r0,29,31,31
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# shift instructions, primary opcode 0x1F
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0xFFF00100,0x7C695830,slw,r9,r3,r11
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0xFFF00100,0x7C00F831,slw.,r0,r0,r31
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0xFFF00100,0x7FC4FC30,srw,r4,r30,r31
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0xFFF00100,0x7CE92C31,srw.,r9,r7,r5
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0xFFF00100,0x7D235E30,sraw,r3,r9,r11
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0xFFF00100,0x7D290631,sraw.,r9,r9,r0
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0xFFF00100,0x7C65FE70,srawi,r5,r3,0x1F
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0xFFF00100,0x7D6B1E70,srawi,r11,r11,0x3
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0xFFF00100,0x7C090E71,srawi.,r9,r0,0x1
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@ -218,16 +226,22 @@
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0xFFF00100,0x7C6023B8,nand,r0,r3,r4
|
||||
0xFFF00100,0x7F8B63B9,nand.,r11,r28,r12
|
||||
|
||||
#logical immediate instructions
|
||||
0xFFF00100,0x60009BA5,ori,r0,r0,0x9BA5
|
||||
0xFFF00100,0x6744AAAA,oris,r4,r26,0xAAAA
|
||||
|
||||
# synchronization instructions
|
||||
0xFFF00100,0x7D201828,lwarx,r9,0,r3
|
||||
0xFFF00100,0x7D20192D,stwcx.,r9,0,r3
|
||||
0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0
|
||||
0xFFF03000,0x4C00012C,isync
|
||||
0xFFF00100,7C0006AC,eieio
|
||||
0xFFF00100,0x7C0004AC,sync
|
||||
0xFFF00100,0x7C0006AC,eieio
|
||||
0xFFF00100,0x7C05272C,sthbrx,r0,r5,r4
|
||||
|
||||
# trap instructions
|
||||
0xFFF00100,0x7F800008,tw,28,r0,r0
|
||||
0xFFF00100,0C000000,twi,0,r0,0
|
||||
0xFFF00100,0x0C000000,twi,0,r0,0
|
||||
|
||||
# integer load and stores
|
||||
0xFFF00100,0x80BF0808,lwz,r5,0x808(r31)
|
||||
|
|
@ -266,13 +280,42 @@
|
|||
0xFFF00100,0xBB41FFE8,lmw,r26,-0x18(r1)
|
||||
0xFFF00100,0xBC410008,stmw,r2,0x8(r1)
|
||||
0xFFF00100,0xBFC1FFF8,stmw,r30,-0x8(r1)
|
||||
0xFFF00100,0xD58B0004,stfsu,f12,4(r11)
|
||||
|
||||
#floating point operations
|
||||
0xFFF00100,0xFC03282A,fadd,f0,f3,f5
|
||||
0xFFF00100,0xFDAD682B,fadd.,f13,f13,f13
|
||||
0xFFF00100,0xFC0D0024,fdiv,f0,f13,f0
|
||||
0xFFF00100,0xFC2B0025,fdiv.,f1,f11,f0
|
||||
0xFFF00100,0xFD8952FC,fnmsub,f12,f9,f11,f10
|
||||
0xFFF00100,0xFD600110,fnabs,f11,f0
|
||||
0xFFF00100,0xFD002034,frsqrte,f8,f4
|
||||
0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
|
||||
|
||||
#compare instructions
|
||||
0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23
|
||||
0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11
|
||||
0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0
|
||||
0xFFF00100,0x2AA3FFFF,cmpli,cr5,1,r3,0xFFFF
|
||||
0xFFF00100,0xFE17C840,fcmpo,cr4,f23,f25
|
||||
0xFFF00100,0xFF0C6800,fcmpu,cr6,f12,f13
|
||||
|
||||
# misc instructions
|
||||
0xFFF00100,0x7D453D2A,stswx,r10,r5,r7
|
||||
0xFFF00100,0x7D290034,cntlzw,r9,r9
|
||||
0xFFF00100,0x7FFF0035,cntlzw.,r31,r31
|
||||
0xFFF00100,0x7C00D7AC,icbi,r0,r26
|
||||
0xFFF00100,0x7D604828,lwarx,r11,0,r9
|
||||
0xFFF00100,0x7CBC04AA,lswi,r5,r28,0x20
|
||||
0xFFF00100,0x7FEF2C2A,lswx,r31,r15,r5
|
||||
0xFFF00100,0x7E000400,mcrxr,cr4
|
||||
0xFFF00100,0xFFE0004C,mtfsb1,31
|
||||
0xFFF00100,0xFFE0048F,mffs.,f31
|
||||
0xFFF00100,0x7FEF01A4,mtsr,15,r31
|
||||
0xFFF00100,0x7C6021E4,mtsrin,r3,r4
|
||||
0xFFF00100,0x7CA305AA,stswi,r5,r3,0x20
|
||||
0xFFF00100,0x7D453D2A,stswx,r10,r5,r7
|
||||
0xFFF00100,0x7C0002E4,tlbia
|
||||
0xFFF00100,0x7C004A64,tlbie,r9
|
||||
|
||||
# various simplified (extended) mnemonics
|
||||
0xFFF00100,0x60000000,nop
|
||||
|
|
@ -289,4 +332,7 @@
|
|||
0xFFF00100,0x7C642D90,dc.l,0x7C642D90
|
||||
|
||||
# POWER/PPC601 specific instructions
|
||||
#0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28
|
||||
0xFFF00100,0x7C440426,clcs,r2,r4
|
||||
0xFFF00100,0x24000800,dozi,r0,r0,0x800
|
||||
0xFFF00100,0x7C00003A,maskg,r0,r0,r0
|
||||
0xFFF00100,0x7E3EE43A,maskir,r30,r17,r28
|
||||
|
Can't render this file because it contains an unexpected character in line 4 and column 24.
|
Loading…
Reference in New Issue
Block a user