Basic MESH emulation.

devices/common/scsi/mesh.cpp

@@ -1,6 +1,6 @@
 /*
 DingusPPC - The Experimental PowerPC Macintosh emulator
-Copyright (C) 2018-21 divingkatae and maximum
+Copyright (C) 2018-23 divingkatae and maximum
                       (theweirdo)     spatium
 
 (Contact divingkatae#1017 or powermax#2286 on Discord for more info)
@@ -23,20 +23,41 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 #include <devices/common/scsi/mesh.h>
 #include <devices/deviceregistry.h>
+#include <loguru.hpp>
+#include <machines/machinebase.h>
 
 #include <cinttypes>
-#include <loguru.hpp>
 
 using namespace MeshScsi;
 
-uint8_t MESHController::read(uint8_t reg_offset)
+int MeshController::device_postinit()
+{
+    this->bus_obj = dynamic_cast<ScsiBus*>(gMachineObj->get_comp_by_name("SCSI0"));
+
+    return 0;
+}
+
+void MeshController::reset(bool is_hard_reset)
+{
+    this->cur_cmd       = SeqCmd::NoOperation;
+    this->int_mask      = 0;
+
+    if (is_hard_reset) {
+        this->bus_stat      = 0;
+        this->sync_params   = 2; // guessed
+    }
+}
+
+uint8_t MeshController::read(uint8_t reg_offset)
 {
     switch(reg_offset) {
     case MeshReg::BusStatus0:
-        LOG_F(9, "MESH: read from BusStatus0 register");
-        return 0;
+        return this->bus_obj->test_ctrl_lines(0xFFU);
+    case MeshReg::BusStatus1:
+        return this->bus_obj->test_ctrl_lines(0xE000U) >> 8;
+    case MeshReg::IntMask:
+        return this->int_mask;
     case MeshReg::MeshID:
-        LOG_F(INFO, "MESH: read from MeshID register");
         return this->chip_id; // tell them who we are
     default:
         LOG_F(WARNING, "MESH: read from unimplemented register at offset 0x%x", reg_offset);
@@ -45,34 +66,67 @@ uint8_t MESHController::read(uint8_t reg_offset)
     return 0;
 }
 
-void MESHController::write(uint8_t reg_offset, uint8_t value)
+void MeshController::write(uint8_t reg_offset, uint8_t value)
 {
+    uint16_t new_stat;
+
     switch(reg_offset) {
     case MeshReg::Sequence:
-        LOG_F(INFO, "MESH: write 0x%02X to Sequence register", value);
+        perform_command(value);
         break;
     case MeshReg::BusStatus1:
-        LOG_F(INFO, "MESH: write 0x%02X to BusStatus1 register", value);
+        new_stat = value << 8;
+        if (new_stat != this->bus_stat) {
+            for (uint16_t mask = SCSI_CTRL_RST; mask >= SCSI_CTRL_SEL; mask >>= 1) {
+                if ((new_stat ^ this->bus_stat) & mask) {
+                    if (new_stat & mask)
+                        this->bus_obj->assert_ctrl_line(new_stat, mask);
+                    else
+                        this->bus_obj->release_ctrl_line(new_stat, mask);
+                }
+            }
+            this->bus_stat = new_stat;
+        }
         break;
     case MeshReg::IntMask:
-        LOG_F(INFO, "MESH: write 0x%02X to IntMask register", value);
+        this->int_mask = value;
         break;
     case MeshReg::Interrupt:
-        LOG_F(INFO, "MESH: write 0x%02X to Interrupt register", value);
+        this->int_stat &= ~(value & INT_MASK); // clear requested interrupt bits
         break;
     case MeshReg::SourceID:
-        LOG_F(INFO, "MESH: write 0x%02X to SourceID register", value);
+        this->src_id = value;
+        break;
+    case MeshReg::DestID:
+        this->dst_id = value;
         break;
     case MeshReg::SyncParms:
-        LOG_F(INFO, "MESH: write 0x%02X to SyncParms register", value);
+        this->sync_params = value;
         break;
     default:
-        LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x", reg_offset);
+        LOG_F(WARNING, "MESH: write to unimplemented register at offset 0x%x",
+              reg_offset);
+    }
+}
+
+void MeshController::perform_command(const uint8_t cmd)
+{
+    this->cur_cmd = cmd & 0xF;
+
+    this->int_stat &= ~INT_CMD_DONE;
+
+    switch (this->cur_cmd) {
+    case SeqCmd::ResetMesh:
+        this->reset(false);
+        this->int_stat |= INT_CMD_DONE;
+        break;
+    default:
+        LOG_F(ERROR, "MESH: unsupported sequencer command 0x%X", this->cur_cmd);
     }
 }
 
 static const DeviceDescription Mesh_Descriptor = {
-    MESHController::create, {}, {}
+    MeshController::create, {}, {}
 };
 
 REGISTER_DEVICE(Mesh, Mesh_Descriptor);

devices/common/scsi/mesh.h

@@ -1,6 +1,6 @@
 /*
 DingusPPC - The Experimental PowerPC Macintosh emulator
-Copyright (C) 2018-21 divingkatae and maximum
+Copyright (C) 2018-23 divingkatae and maximum
                       (theweirdo)     spatium
 
 (Contact divingkatae#1017 or powermax#2286 on Discord for more info)
@@ -25,6 +25,7 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 #define MESH_H
 
 #include <devices/common/hwcomponent.h>
+#include <devices/common/scsi/scsi.h>
 
 #include <cinttypes>
 #include <memory>
@@ -34,7 +35,7 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 namespace MeshScsi {
 
-// MESH registers offsets
+// MESH registers offsets.
 enum MeshReg : uint8_t {
     XferCount0 = 0,
     XferCount1 = 1,
@@ -54,26 +55,58 @@ enum MeshReg : uint8_t {
     SelTimeOut = 0xF
 };
 
+// MESH Sequencer commands.
+enum SeqCmd : uint8_t {
+    NoOperation = 0,
+    Arbitrate   = 1,
+    ResetMesh   = 0xE,
+};
+
+// Interrupt register bits.
+enum {
+    INT_CMD_DONE    = 1 << 0,
+    INT_EXCEPTION   = 1 << 1,
+    INT_ERROR       = 1 << 2,
+    INT_MASK        = INT_CMD_DONE | INT_EXCEPTION | INT_ERROR
+};
+
 }; // namespace MeshScsi
 
-class MESHController : public HWComponent {
+class MeshController : public HWComponent {
 public:
-    MESHController(uint8_t mesh_id) {
+    MeshController(uint8_t mesh_id) {
         supports_types(HWCompType::SCSI_HOST | HWCompType::SCSI_DEV);
         this->chip_id = mesh_id;
+        this->reset(true);
     };
-    ~MESHController() = default;
+    ~MeshController() = default;
 
     static std::unique_ptr<HWComponent> create() {
-        return std::unique_ptr<MESHController>(new MESHController(HeathrowMESHID));
+        return std::unique_ptr<MeshController>(new MeshController(HeathrowMESHID));
     }
 
     // MESH registers access
     uint8_t read(uint8_t reg_offset);
     void   write(uint8_t reg_offset, uint8_t value);
 
+    // HWComponent methods
+    int device_postinit();
+
+protected:
+    void    reset(bool is_hard_reset);
+    void    perform_command(const uint8_t cmd);
+
 private:
-    uint8_t chip_id; // Chip ID for the MESH controller
+    uint8_t     chip_id;
+    uint8_t     int_mask;
+    uint8_t     int_stat = 0;
+    uint8_t     sync_params;
+    uint8_t     src_id;
+    uint8_t     dst_id;
+    uint8_t     cur_cmd;
+
+    ScsiBus*    bus_obj;
+    uint16_t    bus_stat;
 };
 
 #endif // MESH_H

devices/ioctrl/heathrow.cpp

@@ -77,7 +77,7 @@ HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow"), InterruptCtrl()
     );
 
     // connect SCSI HW
-    this->mesh = dynamic_cast<MESHController*>(gMachineObj->get_comp_by_name("Mesh"));
+    this->mesh = dynamic_cast<MeshController*>(gMachineObj->get_comp_by_name("Mesh"));
 
     // connect IDE HW
     this->ide_0 = dynamic_cast<IdeChannel*>(gMachineObj->get_comp_by_name("Ide0"));

devices/ioctrl/macio.h

@@ -228,10 +228,10 @@ private:
 
     NVram*              nvram;    // NVRAM
     ViaCuda*            viacuda;  // VIA cell with Cuda MCU attached to it
-    MESHController*     mesh;     // MESH SCSI cell instance
+    MeshController*     mesh;     // MESH SCSI cell instance
     EsccController*     escc;     // ESCC serial controller
-    IdeChannel*         ide_0;   // Internal ATA
-    IdeChannel*         ide_1;   // Media Bay ATA
+    IdeChannel*         ide_0;    // Internal ATA
+    IdeChannel*         ide_1;    // Media Bay ATA
     Swim3::Swim3Ctrl*   swim3;    // floppy disk controller
 
     std::unique_ptr<DMAChannel>     snd_out_dma;