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Initial work on setting up for interrupts
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dingusdev
parent
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commit
49a5951647
65
devices/common/hwinterrupt.cpp
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65
devices/common/hwinterrupt.cpp
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu/ppc/ppcemu.h>
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#include "hwinterrupt.h"
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#include <cinttypes>
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#include <string>
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#include <loguru.hpp>
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using namespace std;
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InterruptManager::InterruptManager(std::string sys_type) {
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if (sys_type.compare("Heathrow") == 0) {
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scsi0_dma_mask_bit = (1 << 0);
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scca_dma_out_mask_bit = (1 << 4);
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scca_dma_in_mask_bit = (1 << 5);
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sccb_dma_out_mask_bit = (1 << 6);
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sccb_dma_in_mask_bit = (1 << 7);
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dav_dma_out_mask_bit = (1 << 8);
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dav_dma_in_mask_bit = (1 << 9);
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scsi0_mask_bit = (1 << 12);
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scca_mask_bit = (1 << 15);
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sccb_mask_bit = (1 << 16);
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davbus_mask_bit = (1 << 17);
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cuda_mask_bit = (1 << 18);
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nmi_mask_bit = (1 << 20);
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}
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else if (sys_type.compare("AMIC") == 0) {
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LOG_F(WARNING, "Missing interrupt handling for %s!", sys_type.c_str());
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}
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else {
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LOG_F(ERROR, "Cannot determine interrupt layout for %s!", sys_type.c_str());
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}
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}
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uint32_t InterruptManager::ack_interrupts(){
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}
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uint32_t InterruptManager::clear_interrupts(){
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}
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void InterruptManager::call_ppc_handler(uint32_t device_bits) {
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ppc_exception_handler(Except_Type::EXC_EXT_INT, device_bits);
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}
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55
devices/common/hwinterrupt.h
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55
devices/common/hwinterrupt.h
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@ -0,0 +1,55 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef HWINTERRUPT_H
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#define HWINTERRUPT_H
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#include <cinttypes>
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#include <memory>
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class InterruptManager {
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public:
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InterruptManager(std::string sys_type = "None");
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~InterruptManager() = default;
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uint32_t ack_interrupts();
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uint32_t clear_interrupts();
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void call_ppc_handler(uint32_t device_bits);
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private:
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uint32_t int1_flags;
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uint32_t int2_flags;
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uint32_t scsi0_dma_mask_bit = 0;
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uint32_t scca_dma_out_mask_bit = 0;
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uint32_t scca_dma_in_mask_bit = 0;
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uint32_t sccb_dma_out_mask_bit = 0;
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uint32_t sccb_dma_in_mask_bit = 0;
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uint32_t dav_dma_out_mask_bit = 0;
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uint32_t dav_dma_in_mask_bit = 0;
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uint32_t scsi0_mask_bit = 0;
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uint32_t scca_mask_bit = 0;
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uint32_t sccb_mask_bit = 0;
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uint32_t davbus_mask_bit = 0;
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uint32_t cuda_mask_bit = 0;
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uint32_t nmi_mask_bit = 0;
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};
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#endif /* HWINTERRUPT_H */
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@ -129,6 +129,9 @@ uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
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case 0x10:
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res = this->mesh->read((offset >> 4) & 0xF);
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break;
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case 0x11: // BMAC
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LOG_F(WARNING, "Attempted to read from BMAC: %x \n", (offset - 0x11000));
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break;
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case 0x12: // ESCC compatible
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return this->escc->read_compat((offset >> 4) & 0xF);
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case 0x13: // ESCC MacRISC
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@ -136,10 +139,17 @@ uint32_t HeathrowIC::read(uint32_t reg_start, uint32_t offset, int size) {
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case 0x14:
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res = this->screamer->snd_ctrl_read(offset - 0x14000, size);
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break;
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case 0x15: // BMAC
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LOG_F(WARNING, "Attempted to read from SWIM3: %x \n", (offset - 0x15000));
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break;
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case 0x16:
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case 0x17:
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res = this->viacuda->read((offset - 0x16000) >> 9);
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break;
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case 0x20: // IDE
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case 0x21:
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LOG_F(WARNING, "Attempted to read from IDE: %x \n", (offset - 0x20000));
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break;
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default:
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if (sub_addr >= 0x60) {
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res = this->nvram->read_byte((offset - 0x60000) >> 4);
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@ -166,6 +176,9 @@ void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int
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case 0x10:
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this->mesh->write((offset >> 4) & 0xF, value);
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break;
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case 0x11: // BMAC
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LOG_F(WARNING, "Attempted to write to BMAC: %x \n", (offset - 0x11000));
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break;
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case 0x12: // ESCC compatible
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this->escc->write_compat((offset >> 4) & 0xF, value);
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break;
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@ -175,10 +188,17 @@ void HeathrowIC::write(uint32_t reg_start, uint32_t offset, uint32_t value, int
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case 0x14:
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this->screamer->snd_ctrl_write(offset - 0x14000, value, size);
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break;
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case 0x15: // SWIM 3
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LOG_F(WARNING, "Attempted to write to SWIM 3: %x \n", (offset - 0x15000));
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break;
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case 0x16:
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case 0x17:
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this->viacuda->write((offset - 0x16000) >> 9, value);
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break;
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case 0x20: // IDE
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case 0x21:
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LOG_F(WARNING, "Attempted to write to IDE: %x \n", (offset - 0x20000));
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break;
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default:
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if (sub_addr >= 0x60) {
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this->nvram->write_byte((offset - 0x60000) >> 4, value);
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@ -192,28 +212,36 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
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uint32_t res = 0;
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switch (offset & 0xFC) {
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case 0x10:
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LOG_F(0, "read from MIO:Int_Events2 register \n");
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res = this->int_events2;
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break;
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case 0x14:
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LOG_F(9, "read from MIO:Int_Mask2 register \n");
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LOG_F(0, "read from MIO:Int_Mask2 register \n");
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res = this->int_mask2;
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break;
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case 0x18:
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LOG_F(9, "read from MIO:Int_Clear2 register \n");
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LOG_F(0, "read from MIO:Int_Clear2 register \n");
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res = this->int_clear2;
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break;
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case 0x1C:
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LOG_F(9, "read from MIO:Int_Levels2 register \n");
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LOG_F(0, "read from MIO:Int_Levels2 register \n");
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res = this->int_levels2;
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break;
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case 0x20:
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LOG_F(0, "read from MIO:Int_Events1 register \n");
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res = this->int_events2;
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break;
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case 0x24:
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LOG_F(9, "read from MIO:Int_Mask1 register \n");
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LOG_F(0, "read from MIO:Int_Mask1 register \n");
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res = this->int_mask1;
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break;
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case 0x28:
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LOG_F(9, "read from MIO:Int_Clear1 register \n");
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LOG_F(0, "read from MIO:Int_Clear1 register \n");
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res = this->int_clear1;
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break;
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case 0x2C:
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LOG_F(9, "read from MIO:Int_Levels1 register \n");
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LOG_F(0, "read from MIO:Int_Levels1 register \n");
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res = this->int_levels1;
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break;
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case 0x34: /* heathrowIDs / HEATHROW_MBCR (Linux): media bay config reg? */
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@ -234,28 +262,36 @@ uint32_t HeathrowIC::mio_ctrl_read(uint32_t offset, int size) {
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void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
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switch (offset & 0xFC) {
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case 0x10:
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LOG_F(0, "write %x to MIO:Int_Events2 register \n", value);
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this->int_events2 = value;
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break;
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case 0x14:
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LOG_F(9, "write %x to MIO:Int_Mask2 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Mask2 register \n", value);
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this->int_mask2 = value;
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break;
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case 0x18:
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LOG_F(9, "write %x to MIO:Int_Clear2 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Clear2 register \n", value);
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this->int_clear2 = value;
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break;
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case 0x1C:
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LOG_F(9, "write %x to MIO:Int_Levels2 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Levels2 register \n", value);
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this->int_levels2 = value;
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break;
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case 0x20:
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LOG_F(0, "write %x to MIO:Int_Events1 register \n", value);
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this->int_events1 = value;
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break;
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case 0x24:
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LOG_F(9, "write %x to MIO:Int_Mask1 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Mask1 register \n", value);
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this->int_mask1 = value;
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break;
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case 0x28:
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LOG_F(9, "write %x to MIO:Int_Clear1 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Clear1 register \n", value);
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this->int_clear1 = value;
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break;
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case 0x2C:
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LOG_F(9, "write %x to MIO:Int_Levels1 register \n", value);
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LOG_F(0, "write %x to MIO:Int_Levels1 register \n", value);
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this->int_levels1 = value;
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break;
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case 0x34:
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@ -276,7 +312,7 @@ void HeathrowIC::mio_ctrl_write(uint32_t offset, uint32_t value, int size) {
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void HeathrowIC::feature_control(const uint32_t value)
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{
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LOG_F(9, "write %x to MIO:Feat_Ctrl register \n", value);
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LOG_F(0, "write %x to MIO:Feat_Ctrl register \n", value);
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this->feat_ctrl = value;
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@ -143,9 +143,11 @@ private:
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0x00 // unknown defaults
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};
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uint32_t int_events2 = 0;
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uint32_t int_mask2 = 0;
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uint32_t int_clear2 = 0;
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uint32_t int_levels2 = 0;
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uint32_t int_events1 = 0;
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uint32_t int_mask1 = 0;
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uint32_t int_clear1 = 0;
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uint32_t int_levels1 = 0;
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