Heathrow: use common PCI configuration code.

devices/ioctrl/heathrow.cpp

@@ -1,6 +1,6 @@
 /*
 DingusPPC - The Experimental PowerPC Macintosh emulator
-Copyright (C) 2018-21 divingkatae and maximum
+Copyright (C) 2018-22 divingkatae and maximum
                       (theweirdo)     spatium
 
 (Contact divingkatae#1017 or powermax#2286 on Discord for more info)
@@ -43,9 +43,22 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
 
 using namespace std;
 
-HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow") {
+HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow"), InterruptCtrl()
+{
     supports_types(HWCompType::MMIO_DEV | HWCompType::INT_CTRL);
 
+    // populate my PCI config header
+    this->vendor_id   = PCI_VENDOR_APPLE;
+    this->device_id   = 0x0010;
+    this->class_rev   = 0xFF000001;
+    this->cache_ln_sz = 8;
+    this->lat_timer   = 0x40;
+    this->bars_cfg[0] = 0xFFF80000UL; // declare 512Kb of memory-mapped I/O space
+
+    this->pci_notify_bar_change = [this](int bar_num) {
+        this->notify_bar_change(bar_num);
+    };
+
     this->nvram = std::unique_ptr<NVram> (new NVram());
 
     this->viacuda = std::unique_ptr<ViaCuda> (new ViaCuda());
@@ -65,30 +78,18 @@ HeathrowIC::HeathrowIC() : PCIDevice("mac-io/heathrow") {
     this->swim3 = std::unique_ptr<Swim3::Swim3Ctrl> (new Swim3::Swim3Ctrl());
 }
 
-uint32_t HeathrowIC::pci_cfg_read(uint32_t reg_offs, uint32_t size) {
+void HeathrowIC::notify_bar_change(int bar_num)
-    return this->pci_cfg_hdr[reg_offs & 0xFF];
+{
-}
+    if (bar_num) // only BAR0 is supported
+        return;
 
-void HeathrowIC::pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size) {
+    if (this->base_addr != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
-    switch (reg_offs) {
+        if (this->base_addr) {
-    case CFG_REG_BAR0:    // base address register
+            LOG_F(WARNING, "Heathrow: deallocating I/O memory not implemented");
-        value = LE2BE(value);
-        if (value == 0xFFFFFFFF) {
-            LOG_F(
-                ERROR,
-                "%s err: BAR0 block size determination not \
-                implemented yet \n",
-                this->name.c_str());
-        } else if (value & 1) {
-            LOG_F(ERROR, "%s err: BAR0 I/O space not supported! \n", this->name.c_str());
-        } else if (value & 0x06) {
-            LOG_F(ERROR, "%s err: BAR0 64-bit I/O space not supported! \n", this->name.c_str());
-        } else {
-            this->base_addr = value & 0xFFF80000;
-            this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this);
-            LOG_F(INFO, "%s base address set to %x \n", this->name.c_str(), this->base_addr);
         }
-        break;
+        this->base_addr = this->bars[0] & 0xFFFFFFF0UL;
+        this->host_instance->pci_register_mmio_region(this->base_addr, 0x80000, this);
+        LOG_F(INFO, "%s: base address set to 0x%X", this->pci_name.c_str(), this->base_addr);
     }
 }
 
@@ -302,3 +303,21 @@ void HeathrowIC::feature_control(const uint32_t value)
         LOG_F(9, "Heathrow: Monitor sense disabled");
     }
 }
+
+uint32_t HeathrowIC::register_dev_int(IntSrc src_id)
+{
+    return 0;
+}
+
+uint32_t HeathrowIC::register_dma_int(IntSrc src_id)
+{
+    return 0;
+}
+
+void HeathrowIC::ack_int(uint32_t irq_id, uint8_t irq_line_state)
+{
+}
+
+void HeathrowIC::ack_dma_int(uint32_t irq_id, uint8_t irq_line_state)
+{
+}

devices/ioctrl/macio.h

@@ -92,23 +92,21 @@ along with this program.  If not, see <https://www.gnu.org/licenses/>.
     VIA-CUDA       register space: 0x00016000, size: 0x00002000
 */
 
-class HeathrowIC : public PCIDevice {
+class HeathrowIC : public PCIDevice, public InterruptCtrl {
 public:
     HeathrowIC();
     ~HeathrowIC() = default;
 
-    /* PCI device methods */
+    // MMIO device methods
-    bool supports_io_space(void) {
-        return false;
-    };
-
-    uint32_t pci_cfg_read(uint32_t reg_offs, uint32_t size);
-    void pci_cfg_write(uint32_t reg_offs, uint32_t value, uint32_t size);
-
-    /* MMIO device methods */
     uint32_t read(uint32_t reg_start, uint32_t offset, int size);
     void write(uint32_t reg_start, uint32_t offset, uint32_t value, int size);
 
+    // InterruptCtrl methods
+    uint32_t register_dev_int(IntSrc src_id);
+    uint32_t register_dma_int(IntSrc src_id);
+    void ack_int(uint32_t irq_id, uint8_t irq_line_state);
+    void ack_dma_int(uint32_t irq_id, uint8_t irq_line_state);
+
 protected:
     uint32_t dma_read(uint32_t offset, int size);
     void dma_write(uint32_t offset, uint32_t value, int size);
@@ -116,29 +114,12 @@ protected:
     uint32_t mio_ctrl_read(uint32_t offset, int size);
     void mio_ctrl_write(uint32_t offset, uint32_t value, int size);
 
+    void notify_bar_change(int bar_num);
+
     void feature_control(const uint32_t value);
 
 private:
-    uint8_t pci_cfg_hdr[256] = {
+    uint32_t base_addr   = 0;
-        0x6B,
-        0x10,    // vendor ID: Apple Computer Inc.
-        0x10,
-        0x00,    // device ID: Heathrow Mac I/O
-        0x00,
-        0x00,    // PCI command (set to 0 at power-up?)
-        0x00,
-        0x00,    // PCI status (set to 0 at power-up?)
-        0x01,    // revision ID
-        // class code is reported in OF property "class-code" as 0xff0000
-        0x00,    // standard programming
-        0x00,    // subclass code
-        0xFF,    // class code: unassigned
-        0x00,
-        0x00,    // unknown defaults
-        0x00,
-        0x00    // unknown defaults
-    };
-
     uint32_t int_mask2   = 0;
     uint32_t int_clear2  = 0;
     uint32_t int_levels2 = 0;