From 503556196a417f66016fbf252cb45dc81158acab Mon Sep 17 00:00:00 2001 From: joevt Date: Thu, 27 Jul 2023 11:39:19 -0700 Subject: [PATCH] dbdma: Add missing flags, fields, comments. --- devices/common/dbdma.cpp | 8 +++++--- devices/common/dbdma.h | 38 +++++++++++++++++++++++++++++--------- 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/devices/common/dbdma.cpp b/devices/common/dbdma.cpp index d2adcc3..dd741c0 100644 --- a/devices/common/dbdma.cpp +++ b/devices/common/dbdma.cpp @@ -130,7 +130,7 @@ void DMAChannel::finish_cmd() { this->cur_cmd = cmd_desc[3] >> 4; // all commands except STOP update cmd.xferStatus and - // perform actions under control of "i", "b" and "w" bits + // perform actions under control of "i" interrupt, "b" branch, and "w" wait bits if (this->cur_cmd < DBDMA_Cmd::STOP) { // react to cmd.w (wait) bits if (cmd_desc[2] & 3) { @@ -344,8 +344,10 @@ void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) { break; case DMAReg::CH_STAT: break; // ingore writes to ChannelStatus - case DMAReg::CMD_PTR_HI: // Mac OS X writes this optional register with zero - LOG_F(9, "CommandPtrHi set to 0x%X", value); + case DMAReg::CMD_PTR_HI: + if (value != 0) { + LOG_F(WARNING, "%s: Unsupported DMA channel register write @%02x.%c = %0*x", this->get_name().c_str(), offset, SIZE_ARG(size), size * 2, value); + } break; case DMAReg::CMD_PTR_LO: if (!(this->ch_stat & CH_STAT_RUN) && !(this->ch_stat & CH_STAT_ACTIVE)) { diff --git a/devices/common/dbdma.h b/devices/common/dbdma.h index 02ac9cd..cb40ca1 100644 --- a/devices/common/dbdma.h +++ b/devices/common/dbdma.h @@ -40,28 +40,48 @@ class InterruptCtrl; enum DMAReg : uint32_t { CH_CTRL = 0, CH_STAT = 4, - CMD_PTR_HI = 8, + CMD_PTR_HI = 8, // not implemented CMD_PTR_LO = 12, INT_SELECT = 16, BRANCH_SELECT = 20, WAIT_SELECT = 24, +// TANSFER_MODES = 28, +// DATA_2_PTR_HI = 32, // not implemented +// DATA_2_PTR_LO = 36, +// RESERVED_1 = 40, +// ADDRESS_HI = 44, +// RESERVED_2_0 = 48, +// RESERVED_2_1 = 52, +// RESERVED_2_2 = 56, +// RESERVED_2_3 = 60, +// UNIMPLEMENTED = 64, +// UNDEFINED = 128, }; /** Channel Status bits (DBDMA spec, 5.5.3) */ enum : uint16_t { - CH_STAT_ACTIVE = 0x400, - CH_STAT_DEAD = 0x800, - CH_STAT_WAKE = 0x1000, - CH_STAT_FLUSH = 0x2000, - CH_STAT_PAUSE = 0x4000, - CH_STAT_RUN = 0x8000 + CH_STAT_S0 = 0x0001, // general purpose status and control + CH_STAT_S1 = 0x0002, // general purpose status and control + CH_STAT_S2 = 0x0004, // general purpose status and control + CH_STAT_S3 = 0x0008, // general purpose status and control + CH_STAT_S4 = 0x0010, // general purpose status and control + CH_STAT_S5 = 0x0020, // general purpose status and control + CH_STAT_S6 = 0x0040, // general purpose status and control + CH_STAT_S7 = 0x0080, // general purpose status and control + CH_STAT_BT = 0x0100, // hardware status bit + CH_STAT_ACTIVE = 0x0400, // hardware status bit + CH_STAT_DEAD = 0x0800, // hardware status bit + CH_STAT_WAKE = 0x1000, // command bit set by software and cleared by hardware once the action has been performed + CH_STAT_FLUSH = 0x2000, // command bit set by software and cleared by hardware once the action has been performed + CH_STAT_PAUSE = 0x4000, // control bit set and cleared by software + CH_STAT_RUN = 0x8000 // control bit set and cleared by software }; /** DBDMA command (DBDMA spec, 5.6.1) - all fields are little-endian! */ typedef struct DMACmd { uint16_t req_count; - uint8_t cmd_bits; - uint8_t cmd_key; + uint8_t cmd_bits; // wait: & 3, branch: & 0xC, interrupt: & 0x30, reserved: & 0xc0 + uint8_t cmd_key; // key: & 7, reserved: & 8, cmd: >> 4 uint32_t address; uint32_t cmd_arg; uint16_t res_count;