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atirage: Use register bit field names.

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joevt 2024-02-26 16:29:32 -08:00 committed by dingusdev
parent c2ab86d4ba
commit 55b79c1518
1 changed files with 33 additions and 33 deletions
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66
devices/video/atirage.cpp
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@ -135,7 +135,7 @@ ATIRage::ATIRage(uint16_t dev_id)
};
// stuff default values into chip registers
this->regs[ATI_CONFIG_CHIP_ID] = (asic_id << 24) | dev_id;
this->regs[ATI_CONFIG_CHIP_ID] = (asic_id << ATI_CFG_CHIP_MAJOR) | (dev_id << ATI_CFG_CHIP_TYPE);
// initialize display identification
this->disp_id = std::unique_ptr<DisplayID> (new DisplayID());
@ -215,8 +215,8 @@ uint32_t ATIRage::read_reg(uint32_t reg_offset, uint32_t size) {
case ATI_CLOCK_CNTL:
result = this->regs[ATI_CLOCK_CNTL];
if ((offset + size - 1) >= 2) {
uint8_t pll_addr = (this->regs[ATI_CLOCK_CNTL] >> 10) & 0x3F;
insert_bits<uint64_t>(result, this->plls[pll_addr], 16, 8);
uint8_t pll_addr = extract_bits<uint64_t>(result, ATI_PLL_ADDR, ATI_PLL_ADDR_size);
insert_bits<uint64_t>(result, this->plls[pll_addr], ATI_PLL_DATA, ATI_PLL_DATA_size);
}
break;
case ATI_DAC_REGS:
@ -285,21 +285,21 @@ void ATIRage::write_reg(uint32_t reg_offset, uint32_t value, uint32_t size) {
}
break;
case ATI_CRTC_GEN_CNTL:
if (bit_changed(this->regs[reg_offset], value, 6)) {
if (value & 0x40) {
this->regs[reg_offset] |= (1 << 6);
if (bit_changed(this->regs[reg_offset], value, ATI_CRTC_DISPLAY_DIS)) {
if (bit_set(value, ATI_CRTC_DISPLAY_DIS)) {
this->regs[reg_offset] |= (1 << ATI_CRTC_DISPLAY_DIS);
this->blank_on = true;
this->blank_display();
} else {
this->regs[reg_offset] &= ~(1 << 6);
this->regs[reg_offset] &= ~(1 << ATI_CRTC_DISPLAY_DIS);
this->blank_on = false;
}
}
if (bit_changed(this->regs[reg_offset], value, 25)) {
if (bit_changed(this->regs[reg_offset], value, ATI_CRTC_ENABLE)) {
this->regs[reg_offset] = value;
if (bit_set(this->regs[reg_offset], 25) &&
!bit_set(this->regs[reg_offset], 6)) {
if (bit_set(this->regs[reg_offset], ATI_CRTC_ENABLE) &&
!bit_set(this->regs[reg_offset], ATI_CRTC_DISPLAY_DIS)) {
this->crtc_update();
}
return;
@ -319,9 +319,9 @@ void ATIRage::write_reg(uint32_t reg_offset, uint32_t value, uint32_t size) {
return;
case ATI_CLOCK_CNTL:
this->regs[reg_offset] = value;
if ((offset + size - 1) >= 2 && bit_set(this->regs[ATI_CLOCK_CNTL], 9)) {
uint8_t pll_addr = (this->regs[ATI_CLOCK_CNTL] >> 10) & 0x3F;
uint8_t pll_data = (value >> 16) & 0xFF;
if ((offset + size - 1) >= 2 && bit_set(this->regs[ATI_CLOCK_CNTL], ATI_PLL_WR_EN)) {
uint8_t pll_addr = extract_bits<uint32_t>(this->regs[ATI_CLOCK_CNTL], ATI_PLL_ADDR, ATI_PLL_ADDR_size);
uint8_t pll_data = extract_bits<uint32_t>(value, ATI_PLL_DATA, ATI_PLL_DATA_size);
this->plls[pll_addr] = pll_data;
LOG_F(9, "%s: PLL #%d set to 0x%02X", this->name.c_str(), pll_addr, pll_data);
}
@ -350,18 +350,18 @@ void ATIRage::write_reg(uint32_t reg_offset, uint32_t value, uint32_t size) {
}
return;
case ATI_GEN_TEST_CNTL:
if (bit_changed(this->regs[reg_offset], value, 7)) {
if (bit_set(value, 7))
if (bit_changed(this->regs[reg_offset], value, ATI_GEN_CUR_ENABLE)) {
if (bit_set(value, ATI_GEN_CUR_ENABLE))
this->setup_hw_cursor();
else
this->cursor_on = false;
}
if (bit_changed(this->regs[reg_offset], value, 8)) {
if (!bit_set(value, 8))
if (bit_changed(this->regs[reg_offset], value, ATI_GEN_GUI_RESETB)) {
if (!bit_set(value, ATI_GEN_GUI_RESETB))
LOG_F(9, "%s: reset GUI engine", this->name.c_str());
}
if (bit_changed(this->regs[reg_offset], value, 9)) {
if (bit_set(value, 9))
if (bit_changed(this->regs[reg_offset], value, ATI_GEN_SOFT_RESET)) {
if (bit_set(value, ATI_GEN_SOFT_RESET))
LOG_F(9, "%s: reset memory controller", this->name.c_str());
}
if (value & 0xFFFFFC00) {
@ -457,7 +457,7 @@ void ATIRage::verbose_pixel_format(int crtc_index) {
return;
}
uint32_t fmt = extract_bits<uint32_t>(this->regs[ATI_CRTC_GEN_CNTL], 8, 3);
uint32_t fmt = extract_bits<uint32_t>(this->regs[ATI_CRTC_GEN_CNTL], ATI_CRTC_PIX_WIDTH, ATI_CRTC_PIX_WIDTH_size);
const char* what = "Pixel format:";
@ -467,7 +467,7 @@ void ATIRage::verbose_pixel_format(int crtc_index) {
break;
case 2:
// check the undocumented DAC_DIRECT bit
if (bit_set(this->regs[ATI_DAC_CNTL], 10)) {
if (bit_set(this->regs[ATI_DAC_CNTL], ATI_DAC_DIRECT)) {
LOG_F(INFO, "%s 8 bpp direct color (RGB322)", what);
} else {
LOG_F(INFO, "%s 8 bpp with DAC palette", what);
@ -494,7 +494,7 @@ void ATIRage::crtc_update() {
uint32_t new_width, new_height, new_htotal, new_vtotal;
// check for unsupported modes and fail early
if (!bit_set(this->regs[ATI_CRTC_GEN_CNTL], 24))
if (!bit_set(this->regs[ATI_CRTC_GEN_CNTL], ATI_CRTC_EXT_DISP_EN))
ABORT_F("%s: VGA not supported", this->name.c_str());
if ((this->plls[PLL_VCLK_CNTL] & 3) != 3)
@ -502,16 +502,16 @@ void ATIRage::crtc_update() {
bool need_recalc = false;
new_width = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], 16, 8) + 1) * 8;
new_height = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], 16, 11) + 1;
new_width = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], ATI_CRTC_H_DISP, ATI_CRTC_H_DISP_size) + 1) * 8;
new_height = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], ATI_CRTC_V_DISP, ATI_CRTC_V_DISP_size) + 1;
if (new_width != this->active_width || new_height != this->active_height) {
this->create_display_window(new_width, new_height);
need_recalc = true;
}
new_htotal = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], 0, 9) + 1) * 8;
new_vtotal = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], 0, 11) + 1;
new_htotal = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP], ATI_CRTC_H_TOTAL, ATI_CRTC_H_TOTAL_size) + 1) * 8;
new_vtotal = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP], ATI_CRTC_V_TOTAL, ATI_CRTC_V_TOTAL_size) + 1;
if (new_htotal != this->hori_total || new_vtotal != this->vert_total) {
this->hori_total = new_htotal;
@ -523,7 +523,7 @@ void ATIRage::crtc_update() {
return;
// look up which VPLL ouput is requested
int clock_sel = this->regs[ATI_CLOCK_CNTL] & 3;
int clock_sel = extract_bits<uint32_t>(this->regs[ATI_CLOCK_CNTL], ATI_CLOCK_SEL, ATI_CLOCK_SEL_size);
// calculate VPLL output frequency
float vpll_freq = calc_pll_freq(2, this->plls[VCLK0_FB_DIV + clock_sel]);
@ -541,7 +541,7 @@ void ATIRage::crtc_update() {
this->refresh_rate = pixel_clock / this->hori_total / this->vert_total;
// set up frame buffer converter
int pix_fmt = extract_bits<uint32_t>(this->regs[ATI_CRTC_GEN_CNTL], 8, 3);
int pix_fmt = extract_bits<uint32_t>(this->regs[ATI_CRTC_GEN_CNTL], ATI_CRTC_PIX_WIDTH, ATI_CRTC_PIX_WIDTH_size);
switch (pix_fmt) {
case 1:
@ -550,7 +550,7 @@ void ATIRage::crtc_update() {
};
break;
case 2:
if (bit_set(this->regs[ATI_DAC_CNTL], 10)) {
if (bit_set(this->regs[ATI_DAC_CNTL], ATI_DAC_DIRECT)) {
this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) {
this->convert_frame_8bpp(dst_buf, dst_pitch);
};
@ -594,7 +594,7 @@ void ATIRage::crtc_update() {
LOG_F(INFO, "%s: primary CRT controller enabled:", this->name.c_str());
LOG_F(INFO, "Video mode: %s",
bit_set(this->regs[ATI_CRTC_GEN_CNTL], 24) ? "extended" : "VGA");
bit_set(this->regs[ATI_CRTC_GEN_CNTL], ATI_CRTC_EXT_DISP_EN) ? "extended" : "VGA");
LOG_F(INFO, "Video width: %d px", this->active_width);
LOG_F(INFO, "Video height: %d px", this->active_height);
verbose_pixel_format(0);
@ -611,7 +611,7 @@ void ATIRage::crtc_update() {
void ATIRage::draw_hw_cursor(uint8_t *dst_buf, int dst_pitch) {
uint8_t *src_buf, *src_row, *dst_row, px4;
int vert_offset = extract_bits<uint32_t>(this->regs[ATI_CUR_HORZ_VERT_OFF], 16, 5);
int vert_offset = extract_bits<uint32_t>(this->regs[ATI_CUR_HORZ_VERT_OFF], ATI_CUR_VERT_OFF, ATI_CUR_VERT_OFF_size);
src_buf = &this->vram_ptr[this->regs[ATI_CUR_OFFSET] * 8];
@ -648,8 +648,8 @@ void ATIRage::draw_hw_cursor(uint8_t *dst_buf, int dst_pitch) {
}
void ATIRage::get_cursor_position(int& x, int& y) {
x = this->regs[ATI_CUR_HORZ_VERT_POSN] & 0xFFFFU;
y = (this->regs[ATI_CUR_HORZ_VERT_POSN] >> 16) & 0xFFFFU;
x = extract_bits<uint32_t>(this->regs[ATI_CUR_HORZ_VERT_POSN], ATI_CUR_HORZ_POSN, ATI_CUR_HORZ_POSN_size);
y = extract_bits<uint32_t>(this->regs[ATI_CUR_HORZ_VERT_POSN], ATI_CUR_VERT_POSN, ATI_CUR_VERT_POSN_size);
}
static const PropMap AtiRage_Properties = {