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ppcopcodes: Write protect XER zero bits.

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joevt 2024-02-17 00:40:24 -08:00 committed by Maxim Poliakovski
parent 8764beba39
commit 748e9c5d86
1 changed files with 10 additions and 8 deletions
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18
cpu/ppc/ppcopcodes.cpp
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@ -989,7 +989,6 @@ void dppc_interpreter::ppc_mfspr() {
void dppc_interpreter::ppc_mtspr() { void dppc_interpreter::ppc_mtspr() {
uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31); uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
reg_s = (ppc_cur_instruction >> 21) & 31;
#ifdef CPU_PROFILING #ifdef CPU_PROFILING
if (ref_spr > 31) { if (ref_spr > 31) {
@ -997,17 +996,20 @@ void dppc_interpreter::ppc_mtspr() {
} }
#endif #endif
uint32_t val = ppc_state.gpr[reg_s]; if (ref_spr == SPR::PVR) { // prevent writes to the read-only PVR
return;
if (ref_spr != SPR::PVR) { // prevent writes to the read-only PVR
ppc_state.spr[ref_spr] = val;
} }
if (ref_spr == SPR::SDR1) { // adapt to SDR1 changes uint32_t val = ppc_state.gpr[(ppc_cur_instruction >> 21) & 31];
mmu_pat_ctx_changed(); ppc_state.spr[ref_spr] = val;
}
switch (ref_spr) { switch (ref_spr) {
case SPR::XER:
ppc_state.spr[ref_spr] = val & 0xe000ff7f;
break;
case SPR::SDR1:
mmu_pat_ctx_changed(); // adapt to SDR1 changes
break;
case SPR::RTCL_S: case SPR::RTCL_S:
calc_rtcl_value(); calc_rtcl_value();
rtc_lo = val & 0x3FFFFF80UL; rtc_lo = val & 0x3FFFFF80UL;