diff --git a/cpu/ppc/ppcfpopcodes.cpp b/cpu/ppc/ppcfpopcodes.cpp
index 29e3642..dd5f874 100644
--- a/cpu/ppc/ppcfpopcodes.cpp
+++ b/cpu/ppc/ppcfpopcodes.cpp
@@ -186,7 +186,7 @@ void ppc_confirm_inf_nan(int chosen_reg_1, int chosen_reg_2, int chosen_reg_3, b
 
     switch (fpop) {
         case FPOP::DIV:
-            if (isnan(input_a) && isnan(input_b)) {
+            if (isinf(input_a) && isinf(input_b)) {
                 ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXIDI);
             } else if ((input_a == FP_ZERO) && (input_b == FP_ZERO)) {
                 ppc_state.fpscr |= (FPSCR::FX | FPSCR::VXZDZ);
@@ -244,11 +244,15 @@ void fpresult_update(double set_result, bool confirm_arc) {
 
     if (set_result > 0.0) {
         ppc_state.fpscr |= FPSCR::FPCC_POS;
-    } else if (set_result < 0.0) {
+    } 
+    else if (set_result < 0.0) {
         ppc_state.fpscr |= FPSCR::FPCC_NEG;
-    } else if (set_result == 0.0) {
+    } 
+    else {
         ppc_state.fpscr |= FPSCR::FPCC_ZERO;
-    } else {
+    } 
+
+    if (isnan(set_result) || isinf(set_result)) {
         ppc_state.fpscr |= FPSCR::FPCC_FPRCD;
     }
 
@@ -305,7 +309,7 @@ void dppc_interpreter::ppc_fdiv() {
 
     ppc_dblresult64_d = val_reg_a / val_reg_b;
 
-    if (!isnan(ppc_dblresult64_d)) {
+    if (!isnan(ppc_dblresult64_d) || !isinf(ppc_dblresult64_d)) {
         ppc_store_dfpresult_flt(reg_d);
         fpresult_update(ppc_dblresult64_d, rc_flag);
     } else {
@@ -370,6 +374,7 @@ void dppc_interpreter::ppc_fnmadd() {
 
     ppc_dblresult64_d = (val_reg_a * val_reg_c);
     ppc_dblresult64_d += val_reg_b;
+    ppc_dblresult64_d = -(ppc_dblresult64_d);
 
     if (!isnan(ppc_dblresult64_d)) {
         ppc_store_dfpresult_flt(reg_d);
@@ -388,7 +393,7 @@ void dppc_interpreter::ppc_fnmsub() {
 
     ppc_dblresult64_d = (val_reg_a * val_reg_c);
     ppc_dblresult64_d -= val_reg_b;
-    ppc_dblresult64_d = -ppc_dblresult64_d;
+    ppc_dblresult64_d = -(ppc_dblresult64_d);
 
     if (!isnan(ppc_dblresult64_d)) {
         ppc_store_dfpresult_flt(reg_d);
diff --git a/cpu/ppc/test/genppctests.py b/cpu/ppc/test/genppctests.py
index c5cfe8d..e1a30f3 100644
--- a/cpu/ppc/test/genppctests.py
+++ b/cpu/ppc/test/genppctests.py
@@ -112,9 +112,9 @@ def gen_ppc_opcode(opc_str, imm):
     elif opc_str == "FADDS.":
         return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 11) + (0x15 << 1) + 1
     elif opc_str == "FCMPO":
-        return (0x3B << 26) + (3 << 16) + (4 << 11) + (0x20 << 1)
+        return (0x3F << 26) + (3 << 16) + (4 << 11) + (0x20 << 1)
     elif opc_str == "FCMPU":
-        return (0x3B << 26) + (3 << 16) + (4 << 11)
+        return (0x3F << 26) + (3 << 16) + (4 << 11)
     elif opc_str == "FCTIW":
         return (0x3B << 26) + (3 << 16) + (4 << 11) + (0xE << 1)
     elif opc_str == "FCTIW.":
@@ -152,9 +152,9 @@ def gen_ppc_opcode(opc_str, imm):
     elif opc_str == "FNABS.":
         return (0x3F << 26) + (3 << 21) + (4 << 11) + (0x88 << 1) + 1
     elif opc_str == "FNEG":
-        return (0x3B << 26) + (3 << 21) + (4 << 11) + (0x28 << 1)
+        return (0x3F << 26) + (3 << 21) + (4 << 11) + (0x28 << 1)
     elif opc_str == "FNEG.":
-        return (0x3B << 26) + (3 << 21) + (4 << 11) + (0x28 << 1) + 1
+        return (0x3F << 26) + (3 << 21) + (4 << 11) + (0x28 << 1) + 1
     elif opc_str == "FMULS.":
         return (0x3B << 26) + (3 << 21) + (3 << 16) + (4 << 6) + (0x28 << 1) + 1
     elif opc_str == "FMSUB":
diff --git a/cpu/ppc/test/ppcfloattest.txt b/cpu/ppc/test/ppcfloattest.txt
index b36f13d..cdf5e99 100644
--- a/cpu/ppc/test/ppcfloattest.txt
+++ b/cpu/ppc/test/ppcfloattest.txt
@@ -2027,4 +2027,28 @@ FSUBS.    (RTN) :: frD 0x7FF8000000000000 | frA -inf | frB -inf | FPSCR: 0xA0811
 FSUBS.    (RTZ) :: frD 0x7FF8000000000000 | frA -inf | frB -inf | FPSCR: 0xA0811001 | CR: 0x4A000002
 FSUBS.   (RTPI) :: frD 0x7FF8000000000000 | frA -inf | frB -inf | FPSCR: 0xA0811002 | CR: 0x4A000002
 FSUBS.   (RTNI) :: frD 0x7FF8000000000000 | frA -inf | frB -inf | FPSCR: 0xA0811003 | CR: 0x4A000002
-FSUBS.     (VE) :: frD 0x0000000000000000 | frA -inf | frB -inf | FPSCR: 0xE0800080 | CR: 0x0E000000
\ No newline at end of file
+FSUBS.     (VE) :: frD 0x0000000000000000 | frA -inf | frB -inf | FPSCR: 0xE0800080 | CR: 0x0E000000
+FCMPO    :: frA 0.000000e+00 | frB 0.000000e+00 | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPO    :: frA 0.000000e+00 | frB 1.000000e+00 | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPO    :: frA 1.000000e+00 | frB 0.000000e+00 | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPO    :: frA 5.000000e-01 | frB 5.000000e-01 | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPO    :: frA 0.000000e+00 | frB 5.000000e-01 | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPO    :: frA 5.000000e-01 | frB 0.000000e+00 | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPO    :: frA nan | frB nan | FPSCR: 0xA0081000 | CR: 0x01000000
+FCMPO    :: frA nan | frB nan | FPSCR: 0xA1081000 | CR: 0x01000000
+FCMPO    :: frA inf | frB inf | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPO    :: frA inf | frB -inf | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPO    :: frA -inf | frB inf | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPO    :: frA -inf | frB -inf | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPU    :: frA 0.000000e+00 | frB 0.000000e+00 | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPU    :: frA 0.000000e+00 | frB 1.000000e+00 | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPU    :: frA 1.000000e+00 | frB 0.000000e+00 | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPU    :: frA 5.000000e-01 | frB 5.000000e-01 | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPU    :: frA 0.000000e+00 | frB 5.000000e-01 | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPU    :: frA 5.000000e-01 | frB 0.000000e+00 | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPU    :: frA nan | frB nan | FPSCR: 0x00001000 | CR: 0x01000000
+FCMPU    :: frA nan | frB nan | FPSCR: 0xA1001000 | CR: 0x01000000
+FCMPU    :: frA inf | frB inf | FPSCR: 0x00002000 | CR: 0x02000000
+FCMPU    :: frA inf | frB -inf | FPSCR: 0x00004000 | CR: 0x04000000
+FCMPU    :: frA -inf | frB inf | FPSCR: 0x00008000 | CR: 0x08000000
+FCMPU    :: frA -inf | frB -inf | FPSCR: 0x00002000 | CR: 0x02000000
\ No newline at end of file
diff --git a/cpu/ppc/test/ppcfloattests.csv b/cpu/ppc/test/ppcfloattests.csv
index cdda5f1..033ad2c 100644
--- a/cpu/ppc/test/ppcfloattests.csv
+++ b/cpu/ppc/test/ppcfloattests.csv
@@ -2028,3 +2028,27 @@ FSUBS.,0xEC63202B,round=RTZ,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA08
 FSUBS.,0xEC63202B,round=RPI,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811002,CR=0x0A000002
 FSUBS.,0xEC63202B,round=RNI,frD=0x7FF8000000000000,frA=-inf,frB=-inf,FPSCR=0xA0811003,CR=0x0A000002
 FSUBS.,0xEC63202B,round=VEN,frD=0x0000000000000000,frA=-inf,frB=-inf,FPSCR=0xE0800080,CR=0x0E000000
+FCMPO,0xFC032040,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002000,CR=0x02000000
+FCMPO,0xFC032040,frA=0.000000e+00,frB=1.000000e+00,FPSCR=0x00008000,CR=0x08000000
+FCMPO,0xFC032040,frA=1.000000e+00,frB=0.000000e+00,FPSCR=0x00004000,CR=0x04000000
+FCMPO,0xFC032040,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002000,CR=0x02000000
+FCMPO,0xFC032040,frA=0.000000e+00,frB=5.000000e-01,FPSCR=0x00008000,CR=0x08000000
+FCMPO,0xFC032040,frA=5.000000e-01,frB=0.000000e+00,FPSCR=0x00004000,CR=0x04000000
+FCMPO,0xFC032040,frA=nan,frB=nan,FPSCR=0xA0081000,CR=0x01000000
+FCMPO,0xFC032040,frA=nan,frB=nan,FPSCR=0xA1081000,CR=0x01000000
+FCMPO,0xFC032040,frA=inf,frB=inf,FPSCR=0x00002000,CR=0x02000000
+FCMPO,0xFC032040,frA=inf,frB=-inf,FPSCR=0x00004000,CR=0x04000000
+FCMPO,0xFC032040,frA=-inf,frB=inf,FPSCR=0x00008000,CR=0x08000000
+FCMPO,0xFC032040,frA=-inf,frB=-inf,FPSCR=0x00002000,CR=0x02000000
+FCMPU,0xFC032000,frA=0.000000e+00,frB=0.000000e+00,FPSCR=0x00002000,CR=0x02000000
+FCMPU,0xFC032000,frA=0.000000e+00,frB=1.000000e+00,FPSCR=0x00008000,CR=0x08000000
+FCMPU,0xFC032000,frA=1.000000e+00,frB=0.000000e+00,FPSCR=0x00004000,CR=0x04000000
+FCMPU,0xFC032000,frA=5.000000e-01,frB=5.000000e-01,FPSCR=0x00002000,CR=0x02000000
+FCMPU,0xFC032000,frA=0.000000e+00,frB=5.000000e-01,FPSCR=0x00008000,CR=0x08000000
+FCMPU,0xFC032000,frA=5.000000e-01,frB=0.000000e+00,FPSCR=0x00004000,CR=0x04000000
+FCMPU,0xFC032000,frA=nan,frB=nan,FPSCR=0x00001000,CR=0x01000000
+FCMPU,0xFC032000,frA=nan,frB=nan,FPSCR=0xA1001000,CR=0x01000000
+FCMPU,0xFC032000,frA=inf,frB=inf,FPSCR=0x00002000,CR=0x02000000
+FCMPU,0xFC032000,frA=inf,frB=-inf,FPSCR=0x00004000,CR=0x04000000
+FCMPU,0xFC032000,frA=-inf,frB=inf,FPSCR=0x00008000,CR=0x08000000
+FCMPU,0xFC032000,frA=-inf,frB=-inf,FPSCR=0x00002000,CR=0x02000000