mirror of
https://github.com/dingusdev/dingusppc.git
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debugger: disassembler integration.
This commit is contained in:
Maxim Poliakovski
dingusdev
parent
d6d85a750f
commit
825da69a10
399
cpu/ppc/ppcdisasm.cpp
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399
cpu/ppc/ppcdisasm.cpp
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@ -0,0 +1,399 @@
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#include <iostream>
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#include <string>
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#include "ppcdisasm.h"
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using namespace std;
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template< typename... Args >
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std::string my_sprintf(const char* format, Args... args)
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{
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int length = std::snprintf( nullptr, 0, format, args... );
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if (length <= 0)
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return {}; /* empty string in C++11 */
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char* buf = new char[length + 1];
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std::snprintf(buf, length + 1, format, args...);
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std::string str(buf);
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delete[] buf;
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return str;
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}
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const char *bx_mnem[4] = {
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"b", "bl", "ba", "bla"
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};
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const char *br_cond[8] = { /* simplified branch conditions */
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"ge", "le", "ne", "ns", "lt", "gt", "eq", "so"
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};
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const char *opc_idx_ldst[24] = { /* indexed load/store opcodes */
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"lwzx", "lwzux", "lbzx", "lbzux", "stwx", "stwux", "stbx", "stbux", "lhzx",
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"lhzux", "lhax", "lhaux", "sthx", "sthux", "", "", "lfsx", "lfsux", "lfdx",
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"lfdux", "stfsx", "stfsux", "stfdx", "stfdux"
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};
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const char *opc_logic[16] = { /* indexed load/store opcodes */
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"and", "andc", "", "nor", "", "", "", "", "eqv", "xor", "", "", "orc", "or",
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"nand", ""
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};
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const char *opc_subs[16] = { /* subtracts & friends */
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"subfc", "subf", "", "neg", "subfe", "", "subfze", "subfme", "doz", "", "",
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"abs", "", "", "", "nabs"
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};
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const char *opc_adds[9] = { /* additions */
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"addc", "", "", "", "adde", "", "addze", "addme", "add"
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};
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const char *opc_muldivs[16] = { /* multiply and division instructions */
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"mulhwu", "", "mulhw", "mul", "", "", "", "mullw", "", "", "div", "divs",
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"", "", "divwu", "divw"
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};
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/** various formatting helpers. */
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void fmt_twoop(string& buf, const char *opc, int dst, int src)
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{
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buf = my_sprintf("%-8sr%d, r%d", opc, dst, src);
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}
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void fmt_twoop_imm(string& buf, const char *opc, int dst, int imm)
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{
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buf = my_sprintf("%-8sr%d, 0x%04X", opc, dst, imm);
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}
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void fmt_threeop(string& buf, const char *opc, int dst, int src1, int src2)
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{
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buf = my_sprintf("%-8sr%d, r%d, r%d", opc, dst, src1, src2);
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}
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void fmt_threeop_imm(string& buf, const char *opc, int dst, int src1, int imm)
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{
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buf = my_sprintf("%-8sr%d, r%d, 0x%04X", opc, dst, src1, imm);
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}
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void opc_illegal(PPCDisasmContext *ctx)
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{
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ctx->instr_str = my_sprintf("%-8s0x%08X", "dc.l", ctx->instr_code);
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}
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void opc_twi(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_group4(PPCDisasmContext *ctx)
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{
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printf("Altivec group 4 not supported yet\n");
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}
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void opc_mulli(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_subfic(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void power_dozi(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_cmpli(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_cmpi(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_addic(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_addicdot(PPCDisasmContext *ctx)
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{
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//return "DEADBEEF";
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}
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void opc_addi(PPCDisasmContext *ctx)
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{
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto rd = (ctx->instr_code >> 21) & 0x1F;
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auto imm = ctx->instr_code & 0xFFFF;
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if (ra == 0 && ctx->simplified)
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fmt_twoop_imm(ctx->instr_str, "li", rd, imm);
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else
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fmt_threeop_imm(ctx->instr_str, "addi", rd, ra, imm);
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}
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void generic_bcx(PPCDisasmContext *ctx, uint32_t bo, uint32_t bi, uint32_t dst)
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{
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char opcode[10] = "bc";
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if (ctx->instr_code & 1) {
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strcat(opcode, "l"); /* add suffix "l" if the LK bit is set */
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}
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if (ctx->instr_code & 2) {
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strcat(opcode, "a"); /* add suffix "a" if the AA bit is set */
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}
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ctx->instr_str = my_sprintf("%-8s%d, %d, 0x%08X", opcode, bo, bi, dst);
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}
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void opc_bcx(PPCDisasmContext *ctx)
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{
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uint32_t bo, bi, dst, cr;
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char opcode[10] = "b";
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char operands[10] = "";
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bo = (ctx->instr_code >> 21) & 0x1F;
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bi = (ctx->instr_code >> 16) & 0x1F;
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cr = bi >> 2;
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dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr) +
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SIGNEXT(ctx->instr_code & 0xFFFC, 15);
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if (!ctx->simplified || ((bo & 0x10) && bi) ||
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(((bo & 0x14) == 0x14) && (bo & 0xB) && bi)) {
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generic_bcx(ctx, bo, bi, dst);
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return;
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}
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if ((bo & 0x14) == 0x14) {
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ctx->instr_str = my_sprintf("%-8s0x%08X", bx_mnem[0], dst);
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return;
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}
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if (!(bo & 4)) {
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strcat(opcode, "d");
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strcat(opcode, (bo & 2) ? "z" : "nz");
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if (!(bo & 0x10)) {
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strcat(opcode, (bo & 8) ? "t" : "f");
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if (cr) {
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strcat(operands, "4*cr0+");
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operands[4] = cr + '0';
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}
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strcat(operands, br_cond[4 + (bi & 3)]);
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}
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} else { /* CTR ignored */
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strcat(opcode, br_cond[((bo >> 1) & 4) | (bi & 3)]);
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if (cr) {
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strcat(operands, "cr0");
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operands[2] = cr + '0';
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}
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}
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if (ctx->instr_code & 1) {
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strcat(opcode, "l"); /* add suffix "l" if the LK bit is set */
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}
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if (ctx->instr_code & 2) {
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strcat(opcode, "a"); /* add suffix "a" if the AA bit is set */
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}
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if (bo & 1) { /* incorporate prediction bit if set */
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strcat(opcode, (ctx->instr_code & 0x8000) ? "-" : "+");
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}
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ctx->instr_str = my_sprintf("%-8s%s, 0x%08X", opcode, operands, dst);
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}
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void opc_bx(PPCDisasmContext *ctx)
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{
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uint32_t dst = ((ctx->instr_code & 2) ? 0 : ctx->instr_addr)
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+ SIGNEXT(ctx->instr_code & 0x3FFFFFC, 25);
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ctx->instr_str = my_sprintf("%-8s0x%08X", bx_mnem[ctx->instr_code & 3], dst);
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}
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void opc_ori(PPCDisasmContext *ctx)
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{
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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auto imm = ctx->instr_code & 0xFFFF;
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if (!ra && !rs && !imm && ctx->simplified) {
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ctx->instr_str = "nop";
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return;
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}
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if (imm == 0 && ctx->simplified) { /* inofficial, produced by IDA */
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fmt_twoop(ctx->instr_str, "mr", ra, rs);
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return;
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}
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fmt_threeop_imm(ctx->instr_str, "ori", ra, rs, imm);
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}
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void opc_group31(PPCDisasmContext *ctx)
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{
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char opcode[10] = "";
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auto rb = (ctx->instr_code >> 11) & 0x1F;
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auto ra = (ctx->instr_code >> 16) & 0x1F;
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auto rs = (ctx->instr_code >> 21) & 0x1F;
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int ext_opc = (ctx->instr_code >> 1) & 0x3FF; /* extract extended opcode */
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int index = ext_opc >> 5;
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bool rc_set = ctx->instr_code & 1;
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switch(ext_opc & 0x1F) {
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case 8: /* subtracts & friends */
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index &= 0xF; /* strip OE bit */
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if (!strlen(opc_subs[index])) {
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opc_illegal(ctx);
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} else {
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strcpy(opcode, opc_subs[index]);
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if (ext_opc & 0x200) /* check OE bit */
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strcat(opcode, "o");
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if (rc_set)
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strcat(opcode, ".");
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if (index == 3 || index == 6 || index == 7 || index == 11 ||
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index == 15) { /* ugly check for two-operands instructions */
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if (rb != 0)
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opc_illegal(ctx);
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else
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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} else
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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}
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return;
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case 10: /* additions */
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index &= 0xF; /* strip OE bit */
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if (index > 8 || !strlen(opc_adds[index])) {
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opc_illegal(ctx);
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} else {
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strcpy(opcode, opc_adds[index]);
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if (ext_opc & 0x200) /* check OE bit */
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strcat(opcode, "o");
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if (rc_set)
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strcat(opcode, ".");
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if (index == 6 || index == 7) {
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if (rb != 0)
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opc_illegal(ctx);
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else
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fmt_twoop(ctx->instr_str, opcode, rs, ra);
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} else
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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}
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return;
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case 11: /* integer multiplications and divisions */
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index &= 0xF; /* strip OE bit */
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if (!strlen(opc_muldivs[index])) {
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opc_illegal(ctx);
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} else {
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strcpy(opcode, opc_muldivs[index]);
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if (ext_opc & 0x200) /* check OE bit */
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strcat(opcode, "o");
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if (rc_set)
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strcat(opcode, ".");
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if ((!index || index == 2) && (ext_opc & 0x200))
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opc_illegal(ctx);
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else
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fmt_threeop(ctx->instr_str, opcode, rs, ra, rb);
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}
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return;
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case 0x1C: /* logical instructions */
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if (index == 13 && rs == rb && ctx->simplified) {
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fmt_twoop(ctx->instr_str, rc_set ? "mr." : "mr", ra, rs);
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} else {
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strcpy(opcode, opc_logic[index]);
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if (!strlen(opcode)) {
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opc_illegal(ctx);
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} else {
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if (rc_set)
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strcat(opcode, ".");
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fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
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}
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}
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return;
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case 0x17: /* indexed load/store instructions */
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if (index > 23 || rc_set || strlen(opc_idx_ldst[index]) == 0) {
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opc_illegal(ctx);
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return;
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}
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if (index < 16)
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fmt_threeop(ctx->instr_str, opc_idx_ldst[index], rs, ra, rb);
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else
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ctx->instr_str = my_sprintf("%-8sfp%d, r%d, r%d",
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opc_idx_ldst[index], rs, ra, rb);
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return;
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break;
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}
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switch(ext_opc) {
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case 4:
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if (rc_set)
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opc_illegal(ctx);
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else
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ctx->instr_str = my_sprintf("%-8s%d, r%d, r%d", "tw", rs, ra, rb);
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break;
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case 144: /* mtcrf */
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if (ctx->instr_code & 0x100801)
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opc_illegal(ctx);
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else {
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ctx->instr_str = my_sprintf("%-8s0x%02X, r%d", "mtcrf",
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(ctx->instr_code >> 12) & 0xFF, rs);
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}
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break;
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default:
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opc_illegal(ctx);
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}
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}
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/** main dispatch table. */
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static std::function<void(PPCDisasmContext*)> OpcodeDispatchTable[64] = {
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opc_illegal, opc_illegal, opc_illegal, opc_twi,
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opc_group4, opc_illegal, opc_illegal, opc_mulli,
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opc_subfic, power_dozi, opc_cmpli, opc_cmpi,
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opc_addic, opc_addicdot, opc_addi, opc_illegal,
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opc_bcx, opc_illegal, opc_bx, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_ori, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_group31,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal,
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opc_illegal, opc_illegal, opc_illegal, opc_illegal
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/*
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{15, &opc_addis}, {16, &opc_bcx}, {17, &opc_sc},
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{18, &opc_bx}, {19, &opc_opcode19}, {20, &opc_rlwimi},
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{21, &opc_rlwinm}, {22, &power_rlmi}, {23, &opc_rlwnm},
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{24, &opc_ori}, {25, &opc_oris}, {26, &opc_xori},
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{27, &opc_xoris}, {28, &opc_andidot}, {29, &opc_andisdot},
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{30, &opc_illegal}, {31, &opc_group31}, {32, &opc_lwz},
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{33, &opc_lwzu}, {34, &opc_lbz}, {35, &opc_lbzu},
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{36, &opc_stw}, {37, &opc_stwu}, {38, &opc_stb},
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{39, &opc_stbu}, {40, &opc_lhz}, {41, &opc_lhzu},
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{42, &opc_lha}, {43, &opc_lhau}, {44, &opc_sth},
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{45, &opc_sthu}, {46, &opc_lmw}, {47, &opc_stmw},
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{48, &opc_lfs}, {49, &opc_lfsu}, {50, &opc_lfd},
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{51, &opc_lfdu}, {52, &opc_stfs}, {53, &opc_stfsu},
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{54, &opc_stfd}, {55, &opc_stfdu}, {56, &opc_psq_l},
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{57, &opc_psq_lu}, {58, &opc_illegal}, {59, &opc_illegal},
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{60, &opc_psq_st}, {61, &opc_psq_stu}, {62, &opc_illegal},
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{63, &opc_opcode63}
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*/
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};
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string disassemble_single(PPCDisasmContext *ctx)
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{
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OpcodeDispatchTable[ctx->instr_code >> 26](ctx);
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ctx->instr_addr += 4;
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return ctx->instr_str;
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}
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19
cpu/ppc/ppcdisasm.h
Normal file
19
cpu/ppc/ppcdisasm.h
Normal file
@ -0,0 +1,19 @@
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#ifndef PPCDISASM_H
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#define PPCDISASM_H
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#include <cinttypes>
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#include <string>
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typedef struct PPCDisasmContext {
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uint32_t instr_addr;
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uint32_t instr_code;
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std::string instr_str;
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bool simplified; /* true if we should output simplified mnemonics */
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} PPCDisasmContext;
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std::string disassemble_single(PPCDisasmContext *ctx);
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/** sign-extend an integer. */
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#define SIGNEXT(x, sb) ((x) | (((x) & (1 << (sb))) ? ~((1 << (sb))-1) : 0))
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#endif /* PPCDISASM_H */
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@ -13,6 +13,7 @@
|
||||
#include <map>
|
||||
#include "ppcemu.h"
|
||||
#include "../cpu/ppc/ppcmmu.h"
|
||||
#include "../cpu/ppc/ppcdisasm.h"
|
||||
|
||||
|
||||
using namespace std;
|
||||
@ -45,6 +46,18 @@ void dump_regs()
|
||||
cout << "MSR: " << hex << ppc_state.ppc_msr << endl;
|
||||
}
|
||||
|
||||
void disasm()
|
||||
{
|
||||
PPCDisasmContext ctx;
|
||||
|
||||
quickinstruction_translate(ppc_state.ppc_pc);
|
||||
|
||||
ctx.instr_addr = ppc_state.ppc_pc;
|
||||
ctx.instr_code = ppc_cur_instruction;
|
||||
ctx.simplified = true;
|
||||
cout << hex << ppc_state.ppc_pc << " " << disassemble_single(&ctx) << endl;
|
||||
}
|
||||
|
||||
void enter_debugger()
|
||||
{
|
||||
string inp, cmd, addr_str, expr_str, reg_expr, last_cmd;
|
||||
@ -101,7 +114,7 @@ void enter_debugger()
|
||||
addr = stoul(addr_str, NULL, 16);
|
||||
ppc_exec_until(addr);
|
||||
} else if (cmd == "disas") {
|
||||
cout << "Disassembling not implemented yet. Sorry!" << endl;
|
||||
disasm();
|
||||
} else {
|
||||
cout << "Unknown command: " << cmd << endl;
|
||||
continue;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user