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Documentation Update

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dingusdev 2020-03-05 21:38:14 -07:00
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zdocs/adb.md
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The Apple Desktop Bus is a bit-serial peripheral bus, Apple themselves cited a 2-MHz Motorola 68HC11 microcontroller as an example platform to implement the ADB standard with. Its transfer speed is usually around 10.0 kilobits per second, roughly comparable to a PS/2 port at 12.0 kilobits per second.
The device commands are in the form of single byte strings. The first four bits are to signal which of the 16 devices are to be used. The next two bits are for which action to execute (talk, listen, flush, or reset). These are followed by two bits which determine the register to reference (register 0 is usually a communications register, while register 3 is used for device info).
# Commands
| Command Name | Number |

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zdocs/atirage.md
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The ATI Rage is a video card that comes bundled with early Power Mac G3s and New World Macs (like the first revisions of the iMac G3).
#Memory Map
# Memory Map
The ATI Rage can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x9000. However, the video memory appears to be at 0x81000000.
# Register Map
| Register Name | Offset |
|:-------------------:|:------:|
| BUS_CNTL | 0xA0 |
| EXT_MEM_CNTL | 0xAC |
| MEM_CNTL | 0xB0 |
| MEM_VGA_WP_SEL | 0xB4 |
| MEM_VGA_RP_SEL | 0xB8 |
| GEN_TEST_CNTL | 0xD0 |
| CONFIG_CNTL | 0xDC |
| CONFIG_CHIP_ID | 0xE0 |
| CONFIG_STAT0 | 0xE4 |
| DST_CNTL | 0x130 |
| SRC_OFF_PITCH | 0x180 |
| SRC_X | 0x184 |
| SRC_Y | 0x188 |
| SRC_Y_X | 0x18C |
| SRC_WIDTH1 | 0x190 |
| SRC_HEIGHT1 | 0x194 |
| SRC_HEIGHT1_WIDTH1 | 0x198 |
| SRC_CNTL | 0x1B4 |
| SCALE_3D_CNTL | 0x1FC |
| HOST_DATA0 | 0x200 |
| HOST_CNTL | 0x240 |
| DP_PIX_WIDTH | 0x2D0 |
| DP_SRC | 0x2D8 |

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zdocs/awacs.md
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AWACS can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x14000.
AWACS is an audio controller present on several Old World Macs and can usually be located at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x14000.
# Register Maps

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zdocs/heathrow.md
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@ -3,3 +3,12 @@ The Heathrow is an I/O subsystem and a DMA controller.
It contains a feature control register, an auxiliary control register, and some registers to save states for the DBDMA and the VIA Cuda.
It also contains the emulations for the VIA Cuda, SWIM 3 floppy drive, ESCC, and MESH components.
# Register Map
| Register Name | Offset |
|:-------------------:|:------:|
| Base Address 0 | 0x10 |
| Media Bay Control | 0x34 |
| Feature Control | 0x38 |
| Auxiliary Control | 0x3C |

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zdocs/misc.md
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The Old World ROM is always 4 megabytes (MB). The first three MB are reserved for the 68k code, while the last MB is for the PowerPC boot-up code.
# BMac
The BMac is an ethernet controller.
BMac is an Ethernet controller featured in G3 and early G4 Macs. As described by a Linux contributor, this controller "appears to have some parts in common with the Sun "Happy Meal" (HME) controller".
The max frame size is 0x5EE bytes.
It resides on 0xF3011000, with Writing DMA on 0xF3008200 and Reading DMA on 0xF3008300.
Swim3 is located at 0xF3015000.
## Register Map
| Register Name | Offset |
|:-------------:|:------:|
| XIFC | 0x000 |
| TXFIFOCSR | 0x100 |
| TXTH | 0x110 |
| RXFIFOCSR | 0x120 |
| MEMADD | 0x130 |
| XCVRIF | 0x160 |
| CHIPID | 0x170 |
| TXPNTR | 0x1A0 |
| RXPNTR | 0x1B0 |
| STATUS | 0x200 |
| INTDISABLE | 0x210 |
| TXRST | 0x420 |
| TXCFG | 0x430 |
| RXRST | 0x620 |
| RXCFG | 0x630 |
# Serial
@ -34,14 +52,39 @@ The Description-Based Direct Memory Access relies on memory-based descriptions,
| AUDIO IN | 0x9 |
| SCSI1 | 0xA |
# NCR 53C94
The NCR 53C94 is the SCSI controller.
# Register Map
| Offset | Read functionality |Write functionality |
|:------:|:------------------------:|:-------------------------:|
| 0x0 | Transfer counter LSB | Transfer counter LSB |
| 0x1 | Transfer counter MSB | Transfer counter MSB |
| 0x2 | FIFO | FIFO |
| 0x3 | Command | Command |
| 0x4 | Status | Destination Bus ID |
| 0x5 | Interrupt | Select/reselect timeout |
| 0x6 | Sequence step | Synch period |
| 0x7 | FIFO flags/sequence step | Synch offset |
| 0x8 | Configuration 1 | Configuration 1 |
| 0x9 | | Clock conversion factor |
| 0xA | | Test mode |
| 0xB | Configuration 2 | Configuration 2 |
| 0xC | Configuration 3 | Configuration 3 |
| 0xF | | Reserve FIFO Byte (Cfg 2) |
# SWIM 3
The SWIM 3 (Sanders-Wozniak integrated machine 3) is the floppy drive disk controller. As can be inferred by the name, the SWIM III chip is the improvement of a combination of floppy disk driver designs by Steve Wozniak (who worked on his own floppy drive controller for early Apple computers) and Wendell B. Sander (who worked on an MFM-compatible IBM floppy drive controller).
The SWIM chip is resided on the logic board. It sits between the I/O controller and the floppy disk connector. Its function is to translate the I/O commands to specialized signals to drive the floppy disk drive, i.e. disk spinning speed, head position, phase sync, etc.
The SWIM chip is resided on the logic board physically and is located at IOBase + 0x15000 in the device tree. It sits between the I/O controller and the floppy disk connector. Its function is to translate the I/O commands to specialized signals to drive the floppy disk drive, i.e. disk spinning speed, head position, phase sync, etc.
The floppy drives themselves were provided by Sony.
Some New World Macs do have a SWIM 3 driver present, but this normally goes unused due to no floppy drive being connected.
# NVRAM
Mac OS relies on 8 KB of NVRAM at minimum to run properly. It's usually found at IOBase (ex.: 0xF3000000 for Power Mac G3 Beige) + 0x60000.

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zdocs/powerpc.md
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@ -10,6 +10,10 @@ Code execution generally begins at 0xFFF00100, which the reset exception vector.
The 601 BATs are emulated by the OpenFirmware.
# TLBs
Up to 128 instruction entries and 128 data entries can be stored at a time.
# Processor Revisions
| Model | PVR Number | Notable Aspects |
@ -33,3 +37,9 @@ The 601 BATs are emulated by the OpenFirmware.
| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
| Machine State Register | 1 | |
# Eccentricities
* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.
* Apple's memcpy routine uses double floating-point registers rather than general purpose registers to load and store 2 32-bit values at once. As the PowerPC usually operates on at least a 64-bit bus and floating-point processing comes with the processors by default, this saves some instructions and results in slightly faster speeds.

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zdocs/viacuda.md
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@ -42,7 +42,7 @@ Within the emulated CUDA, these registers are spaced apart by 0x200 bytes. Apple
| Drive Select | 0x10 |
| Disk Head Select | 0x20 |
## Auxiliary Contral
## Auxiliary Control
| Register Bit | Bit Mask |
|:---------------------------------:|:--------:|