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ppcdisasm: new tests and fixes for rlwinm/rlwimi.

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This commit is contained in:
Maxim Poliakovski 2020-02-16 23:00:58 +01:00
parent 8babfa9987
commit 8671517a08
2 changed files with 96 additions and 195 deletions
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243
cpu/ppc/ppcdisasm.cpp
View File

@ -248,138 +248,6 @@ void fmt_rotateop(string& buf, const char* opc, int dst, int src, int sh, int mb
buf = my_sprintf("%-8sr%d, r%d, r%d, %d, %d", opc, dst, src, sh, mb, me);
}
/* Mnemonics for rlwinm */
void opc_rotlwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "rotlwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
}
void opc_rotrwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "rotrwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
}
void opc_slwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "slwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
return;
}
void opc_srwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "clrlwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
return;
}
void opc_clrlwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "clrlwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
return;
}
void opc_clrrwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n) {
char opcode[10];
strcpy(opcode, "clrrwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, field_n);
return;
}
void opc_extlwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n, uint32_t field_b) {
char opcode[10];
strcpy(opcode, "extrwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_fourop(ctx->instr_str, opcode, ra, rs, field_n, field_b);
return;
}
void opc_extrwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n, uint32_t field_b) {
char opcode[10];
strcpy(opcode, "extrwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_fourop(ctx->instr_str, opcode, ra, rs, field_n, field_b);
return;
}
void opc_inslwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n, uint32_t field_b) {
char opcode[10];
strcpy(opcode, "inslwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_fourop(ctx->instr_str, opcode, ra, rs, field_n, field_b);
return;
}
void opc_insrwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n, uint32_t field_b) {
char opcode[10];
strcpy(opcode, "inslwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_fourop(ctx->instr_str, opcode, ra, rs, field_n, field_b);
return;
}
void opc_clrlslwi(PPCDisasmContext* ctx, uint32_t ra, uint32_t rs, uint32_t field_n, uint32_t field_b) {
char opcode[10];
strcpy(opcode, "clrlslwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_fourop(ctx->instr_str, opcode, ra, rs, field_n, field_b);
return;
}
/* Opcodes */
void opc_illegal(PPCDisasmContext* ctx)
@ -461,6 +329,29 @@ void power_dozi(PPCDisasmContext* ctx)
fmt_threeop_simm(ctx->instr_str, "dozi", rd, ra, imm);
}
void fmt_rot_imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n)
{
char opcode[10];
strcpy(opcode, opc);
if (ctx->instr_code & 1)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d", opcode, ra, rs, n);
}
void fmt_rot_2imm(PPCDisasmContext* ctx, const char* opc, int ra, int rs, int n,
int b)
{
char opcode[10];
strcpy(opcode, opc);
if (ctx->instr_code & 1)
strcat(opcode, ".");
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", opcode, ra, rs, n, b);
}
void opc_rlwimi(PPCDisasmContext* ctx)
{
char opcode[10];
@ -471,25 +362,13 @@ void opc_rlwimi(PPCDisasmContext* ctx)
auto me = (ctx->instr_code >> 1) & 0x1F;
if (ctx->simplified) {
if (sh > 0) {
if ((32 - mb) == sh) {
strcpy(opcode, "inslwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
uint32_t field_n = me + 1 - mb;
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", opcode, rs, ra, field_n, mb);
}
else if ((32 - (mb + sh)) == mb) {
strcpy(opcode, "insrwi");
if (ctx->instr_code & 1)
strcat(opcode, ".");
uint32_t field_n = me + 1 - mb;
ctx->instr_str = my_sprintf("%-8sr%d, r%d, %d, %d", opcode, rs, ra, field_n, mb);
}
if ((32 - sh) == mb) {
fmt_rot_2imm(ctx, "inslwi", ra, rs, me + 1 - mb, mb);
return;
}
else if (sh == 32 - (me + 1)) {
fmt_rot_2imm(ctx, "insrwi", ra, rs, (me - mb + 1), mb);
return;
}
}
@ -510,47 +389,37 @@ void opc_rlwinm(PPCDisasmContext* ctx)
auto me = (ctx->instr_code >> 1) & 0x1F;
if (ctx->simplified) {
if ((mb == 0) & (me == 31)) {
if (sh < 16){
opc_rotlwi(ctx, ra, rs, sh);
return;
}
else {
opc_rotrwi(ctx, ra, rs, 32 - sh);
return;
if ((mb == 0) && (me == 31)) {
if (sh < 16) {
fmt_rot_imm(ctx, "rotlwi", ra, rs, sh);
} else {
fmt_rot_imm(ctx, "rotrwi", ra, rs, 32 - sh);
}
return;
}
else if (me == 31) {
if ((32 - sh) == mb) {
opc_srwi(ctx, ra, rs, mb);
return;
}
else if (sh == 0) {
opc_clrlwi(ctx, ra, rs, mb);
return;
}
else {
opc_extrwi(ctx, ra, rs, (32 - mb), (sh - (32 - mb)));
return;
fmt_rot_imm(ctx, "srwi", ra, rs, mb);
} else if (sh == 0) {
fmt_rot_imm(ctx, "clrlwi", ra, rs, mb);
} else {
fmt_rot_2imm(ctx, "extrwi", ra, rs, (32 - mb), (sh - (32 - mb)));
}
return;
}
else if (mb == 0) {
if ((31 - me) == sh) {
opc_slwi(ctx, ra, rs, sh);
return;
}
else if (sh == 0) {
opc_clrrwi(ctx, ra, rs, (31 - me));
return;
}
else {
opc_extlwi(ctx, ra, rs, (me + 1), sh);
return;
fmt_rot_imm(ctx, "slwi", ra, rs, sh);
} else if (sh == 0) {
fmt_rot_imm(ctx, "clrrwi", ra, rs, (31 - me));
} else {
fmt_rot_2imm(ctx, "extlwi", ra, rs, (me + 1), sh);
}
return;
}
else if (mb) {
if ((31 - me) == sh) {
opc_clrlslwi(ctx, ra, rs, (mb + sh), sh);
fmt_rot_2imm(ctx, "clrlslwi", ra, rs, (mb + sh), sh);
return;
}
}
@ -559,7 +428,7 @@ void opc_rlwinm(PPCDisasmContext* ctx)
strcpy(opcode, "rlwinm");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_rotateop(ctx->instr_str, opcode, ra, rs, sh, mb, me, true);
}
@ -587,12 +456,12 @@ void opc_rlwnm(PPCDisasmContext* ctx)
auto me = (ctx->instr_code >> 1) & 0x1F;
if (ctx->simplified) {
if ((me == 31) & (mb == 0)) {
if ((me == 31) && (mb == 0)) {
strcpy(opcode, "rotlw");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_threeop(ctx->instr_str, opcode, ra, rs, rb);
return;
}
@ -600,7 +469,7 @@ void opc_rlwnm(PPCDisasmContext* ctx)
strcpy(opcode, "rlwnm");
if (ctx->instr_code & 1)
strcat(opcode, ".");
fmt_rotateop(ctx->instr_str, "rlwnm", ra, rs, rb, mb, me, false);
}
@ -618,7 +487,7 @@ void opc_cmp_i_li(PPCDisasmContext* ctx)
ctx->instr_str = my_sprintf("%-8scr%d, r%d, 0x%X", "cmpwi", crfd, ra, imm);
else
ctx->instr_str = my_sprintf("%-8scr%d, r%d, 0x%04X", "cmplwi", crfd, ra, imm);
return;
}
}
@ -1207,7 +1076,7 @@ void opc_group31(PPCDisasmContext* ctx)
return;
}
}
ctx->instr_str = my_sprintf("%-8scr%d, %d, r%d, r%d", "cmp", (rs >> 2), (rs & 1), ra, rb);
break;
case 4: /* tw */
@ -1932,4 +1801,4 @@ string disassemble_single(PPCDisasmContext* ctx)
ctx->instr_addr += 4;
return ctx->instr_str;
}
}

48
cpu/ppc/test/ppcdisasmtest.csv
View File

@ -185,9 +185,39 @@
0xFFF00100,0x7D080120,mtcrf,0x80,r8
0xFFF00100,0x7E007120,mtcrf,0x07,r16
# rotation instructions
0xFFF00100,0x5084442E,rlwimi,r4,r4,8,16,23
0xFFF00100,0x5400EFFE,rlwinm,r0,r0,29,31,31
# rotation instructions and their simplified mnemonics
#0xFFF00100,0x5084442E,rlwimi,r4,r4,8,16,23
0xFFF00100,0x54DF0FBC,clrlslwi,r31,r6,31,1
0xFFF00100,0x54DFF042,clrlslwi,r31,r6,31,30
0xFFF00100,0x54DF087C,clrlslwi,r31,r6,2,1
0xFFF00100,0x54A30FBC,clrlslwi,r3,r5,31,1
0xFFF00100,0x547AE884,clrlslwi,r26,r3,31,29
0xFFF00100,0x5485007E,clrlwi,r5,r4,1
0xFFF00100,0x572007FF,clrlwi.,r0,r25,31
0xFFF00100,0x5404003C,clrrwi,r4,r0,1
0xFFF00100,0x54000001,clrrwi.,r0,r0,31
0xFFF00100,0x558C083A,extlwi,r12,r12,30,1
0xFFF00100,0x55CEF839,extlwi.,r14,r14,29,31
0xFFF00100,0x558CF83A,extlwi,r12,r12,30,31
0xFFF00100,0x5486657F,extrwi.,r6,r4,11,1
0xFFF00100,0x5400EFFE,extrwi,r0,r0,1,28
0xFFF00100,0x5583FFFE,extrwi,r3,r12,1,30
0xFFF00100,0x509E0FFE,inslwi,r30,r4,1,31
0xFFF00100,0x5068F87F,inslwi.,r8,r3,31,1
0xFFF00100,0x50A5402E,insrwi,r5,r5,24,0
0xFFF00100,0x5084442E,insrwi,r4,r4,8,16
0xFFF00100,0x514407FE,insrwi,r4,r10,1,31
0xFFF00100,0x5C8B183E,rotlw,r11,r4,r3
0xFFF00100,0x5EB5883F,rotlw.,r21,r21,r17
0xFFF00100,0x55C4083E,rotlwi,r4,r14,1
0xFFF00100,0x56BF783E,rotlwi,r31,r21,15
0xFFF00100,0x56BF803E,rotrwi,r31,r21,16
0xFFF00100,0x55C4F83F,rotrwi.,r4,r14,1
0xFFF00100,0x574B083C,slwi,r11,r26,1
0xFFF00100,0x55C4C00F,slwi.,r4,r14,24
0xFFF00100,0x55E4F800,slwi,r4,r15,31
0xFFF00100,0x5480F87E,srwi,r0,r4,1
0xFFF00100,0x54060FFE,srwi,r6,r0,31
# shift instructions, primary opcode 0x1F
0xFFF00100,0x7C695830,slw,r9,r3,r11
@ -218,7 +248,7 @@
0xFFF00100,0x7C6023B8,nand,r0,r3,r4
0xFFF00100,0x7F8B63B9,nand.,r11,r28,r12
#logical immediate instructions
# logical immediate instructions
0xFFF00100,0x60009BA5,ori,r0,r0,0x9BA5
0xFFF00100,0x6744AAAA,oris,r4,r26,0xAAAA
0xFFF00100,0x6B24002D,xori,r4,r25,0x2D
@ -231,6 +261,7 @@
0xFFF00100,0x7C604C2C,lwbrx,r3,0,r9
0xFFF00100,0x7D201828,lwarx,r9,0,r3
0xFFF00100,0x7D20192D,stwcx.,r9,0,r3
0xFFF00100,0x7EA1E12D,stwcx.,r21,r1,r28
0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0
0xFFF03000,0x4C00012C,isync
0xFFF00100,0x7C0004AC,sync
@ -279,7 +310,7 @@
0xFFF00100,0xBC410008,stmw,r2,0x8(r1)
0xFFF00100,0xBFC1FFF8,stmw,r30,-0x8(r1)
#floating point load and stores
# floating point load and stores
0xFFF00100,0x7C0BF5AE,stfdx,f0,r11,r30
0xFFF00100,0x7C0525EE,stfdux,f0,r5,r4
0xFFF00100,0x7D89FD2E,stfsx,f12,r9,r31
@ -306,7 +337,7 @@
0xFFF00100,0x7C4325AE,stfdx,f2,r3,r4
0xFFF00100,0x7C4325EE,stfdux,f2,r3,r4
#floating point operations
# floating point operations
0xFFF00100,0xFC03282A,fadd,f0,f3,f5
0xFFF00100,0xFDAD682B,fadd.,f13,f13,f13
0xFFF00100,0xFC0D6028,fsub,f0,f13,f12
@ -323,7 +354,8 @@
0xFFF00100,0xFD002034,frsqrte,f8,f4
0xFFF00100,0x7FF957AE,stfiwx,f31,r25,r10
#compare instructions
# compare instructions
0xFFF00100,0x7C15A000,cmpw,r21,r20
0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23
0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11
0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0
@ -385,4 +417,4 @@
0xFFF00100,0x7C4105B2,sreq,r1,r2,r0
0xFFF00100,0x7C4105B3,sreq.,r1,r2,r0
0xFFF00100,0x7E042570,sriq,r4,r16,0x4
0xFFF00100,0x7E042571,sriq.,r4,r16,0x4
0xFFF00100,0x7E042571,sriq.,r4,r16,0x4

1 # Test data for PowerPC disassembler supplied as comma-separated values
185 0xFFF00100,0x7D235E30,sraw,r3,r9,r11 0xFFF00100,0x572007FF,clrlwi.,r0,r25,31
186 0xFFF00100,0x7D290631,sraw.,r9,r9,r0 0xFFF00100,0x5404003C,clrrwi,r4,r0,1
187 0xFFF00100,0x7C65FE70,srawi,r5,r3,0x1F 0xFFF00100,0x54000001,clrrwi.,r0,r0,31
188 0xFFF00100,0x7D6B1E70,srawi,r11,r11,0x3 0xFFF00100,0x558C083A,extlwi,r12,r12,30,1
189 0xFFF00100,0x7C090E71,srawi.,r9,r0,0x1 0xFFF00100,0x55CEF839,extlwi.,r14,r14,29,31
190 # logical instructions, primary opcode 0x1F 0xFFF00100,0x558CF83A,extlwi,r12,r12,30,31
191 0xFFF00100,0x5486657F,extrwi.,r6,r4,11,1
192 0xFFF00100,0x5400EFFE,extrwi,r0,r0,1,28
193 0xFFF00100,0x5583FFFE,extrwi,r3,r12,1,30
194 0xFFF00100,0x509E0FFE,inslwi,r30,r4,1,31
195 0xFFF00100,0x5068F87F,inslwi.,r8,r3,31,1
196 0xFFF00100,0x50A5402E,insrwi,r5,r5,24,0
197 0xFFF00100,0x5084442E,insrwi,r4,r4,8,16
198 0xFFF00100,0x514407FE,insrwi,r4,r10,1,31
199 0xFFF00100,0x5C8B183E,rotlw,r11,r4,r3
200 0xFFF00100,0x5EB5883F,rotlw.,r21,r21,r17
201 0xFFF00100,0x55C4083E,rotlwi,r4,r14,1
202 0xFFF00100,0x56BF783E,rotlwi,r31,r21,15
203 0xFFF00100,0x56BF803E,rotrwi,r31,r21,16
204 0xFFF00100,0x55C4F83F,rotrwi.,r4,r14,1
205 0xFFF00100,0x574B083C,slwi,r11,r26,1
206 0xFFF00100,0x55C4C00F,slwi.,r4,r14,24
207 0xFFF00100,0x55E4F800,slwi,r4,r15,31
208 0xFFF00100,0x5480F87E,srwi,r0,r4,1
209 0xFFF00100,0x54060FFE,srwi,r6,r0,31
210 # shift instructions, primary opcode 0x1F
211 0xFFF00100,0x7C695830,slw,r9,r3,r11
212 0xFFF00100,0x7C00F831,slw.,r0,r0,r31
213 0xFFF00100,0x7FC4FC30,srw,r4,r30,r31
214 0xFFF00100,0x7CE92C31,srw.,r9,r7,r5
215 0xFFF00100,0x7D235E30,sraw,r3,r9,r11
216 0xFFF00100,0x7D290631,sraw.,r9,r9,r0
217 0xFFF00100,0x7C65FE70,srawi,r5,r3,0x1F
218 0xFFF00100,0x7D6B1E70,srawi,r11,r11,0x3
219 0xFFF00100,0x7C090E71,srawi.,r9,r0,0x1
220 # logical instructions, primary opcode 0x1F
221 0xFFF00100,0x7FC32838,and,r3,r30,r5
222 0xFFF00100,0x7C672039,and.,r7,r3,r4
223 0xFFF00100,0x7D281878,andc,r8,r9,r3
248 0xFFF00100,0x7D20192D,stwcx.,r9,0,r3
249 0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0 0xFFF00100,0x7EA1E12D,stwcx.,r21,r1,r28
250 0xFFF03000,0x4C00012C,isync 0xFFF00100,0x7FAB052C,stwbrx,r29,r11,r0
251 0xFFF00100,0x7C0004AC,sync 0xFFF03000,0x4C00012C,isync
252 0xFFF00100,0x7C0006AC,eieio 0xFFF00100,0x7C0004AC,sync
253 0xFFF00100,0x7C05272C,sthbrx,r0,r5,r4 0xFFF00100,0x7C0006AC,eieio
254 # trap instructions 0xFFF00100,0x7C05272C,sthbrx,r0,r5,r4
261 0xFFF00100,0x8506003C,lwzu,r8,0x3C(r6) 0xFFF00100,0x80002F3C,lwz,r0,0x2F3C
262 0xFFF00100,0x8403FFF8,lwzu,r0,-0x8(r3) 0xFFF00100,0x8506003C,lwzu,r8,0x3C(r6)
263 0xFFF00100,0x88FD00FA,lbz,r7,0xFA(r29) 0xFFF00100,0x8403FFF8,lwzu,r0,-0x8(r3)
264 0xFFF00100,0x88FD00FA,lbz,r7,0xFA(r29)
265 0xFFF00100,0x889EFFF4,lbz,r4,-0xC(r30)
266 0xFFF00100,0x8D480001,lbzu,r10,0x1(r8)
267 0xFFF00100,0x8FC3FFFF,lbzu,r30,-0x1(r3)
310 0xFFF00100,0x7CAA7CEE,lfdux,f5,r10,r15
311 0xFFF00100,0x7FEF2C6E,lfsux,f31,r15,r5
312 0xFFF00100,0x7C09DC2E,lfsx,f0,r9,r27
313 0xFFF00100,0x7C43242E,lfsx,f2,r3,r4
314 0xFFF00100,0x7C43246E,lfsux,f2,r3,r4
315 0xFFF00100,0x7D491CAE,lfdx,f10,r9,r3
316 0xFFF00100,0x7C4324EE,lfdux,f2,r3,r4
337 #compare instructions # compare instructions
338 0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23 0xFFF00100,0x7C15A000,cmpw,r21,r20
339 0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11 0xFFF00100,0x7FBFB800,cmp,cr7,1,r31,r23
340 0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0 0xFFF00100,0x7FA05840,cmpl,cr7,1,r0,r11
341 0xFFF00100,0x2AA3FFFF,cmpli,cr5,1,r3,0xFFFF 0xFFF00100,0x2FA90000,cmpi,cr7,1,r9,0x0
342 0xFFF00100,0xFE17C840,fcmpo,cr4,f23,f25 0xFFF00100,0x2AA3FFFF,cmpli,cr5,1,r3,0xFFFF
343 0xFFF00100,0xFF0C6800,fcmpu,cr6,f12,f13 0xFFF00100,0xFE17C840,fcmpo,cr4,f23,f25
354 0xFFF00100,0x7FEF01A4,mtsr,15,r31 0xFFF00100,0xFFE0048F,mffs.,f31
355 0xFFF00100,0x7C6021E4,mtsrin,r3,r4 0xFFF00100,0x7FEF01A4,mtsr,15,r31
356 0xFFF00100,0x7CA305AA,stswi,r5,r3,0x20 0xFFF00100,0x7C6021E4,mtsrin,r3,r4
357 0xFFF00100,0x7D453D2A,stswx,r10,r5,r7 0xFFF00100,0x7CA305AA,stswi,r5,r3,0x20
358 0xFFF00100,0x7D453D2A,stswx,r10,r5,r7
359 0xFFF00100,0x7C0002E4,tlbia
360 0xFFF00100,0x7C004A64,tlbie,r9
361 # various simplified (extended) mnemonics
417
418
419
420