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dingusdev 2024-08-26 06:48:55 -07:00
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10
zdocs/developers/awacs.md
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@ -26,6 +26,16 @@ All registers are 32-bit here.
| Codec Status | 0x20 |
| Clipping Count | 0x30 |
| Byte Swapping | 0x40 |
| Frame Count | 0x50 |
##Sound Control Register bits
| Register | Bit Mask |
|:-------------------------:|:--------:|
| Input Subframe Select | 0x000F |
| Output Subframe Select | 0x00F0 |
| Sound Rate | 0x0700 |
| Error | 0x0800 |
Separate volume controls exist for the CD drive and the microphone.

1
zdocs/developers/bebox.md
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@ -10,6 +10,7 @@ It also has a unique 37-pin connector dubbed the Geekport to allow hobbyists to
* MPC105 PCI Bridge (Codename: Eagle) - Predecessor to the MPC106 (Grackle); Used for bridging between the motherboard and PCI slots
* Intel 82378ZB - Used for bridging between the motherboard and ISA slots
* SYM53C810A - SCSI I/O Processor
* bq3285 - Used for the Real-Time Clock
### Motherboard registers

59
zdocs/developers/powerpc.md → zdocs/developers/cpu/powerpc/powerpc.md
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@ -1,11 +1,9 @@
The PowerPC is the main processor behind Power Macs. Currently, DingusPPC only implements the 32-bit variant.
The PowerPC is the main processor used for Power Macs. Currently, DingusPPC only implements the 32-bit variant.
# General Notes
All instructions are 32 bits wide, regardless of whether the PowerPC is in 32-bit or 64-bit mode.
Code execution generally begins at 0xFFF00100, which the reset exception vector.
# BATs
The 601 BATs are emulated by the Open Firmware.
@ -27,17 +25,17 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
# Registers
| Register Type | Number | Purpose |
| :-------------------------------- | :--------------------- | :---------------------------------------------------- |
| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
| Vector Status and Control Register (VSCR) | 1 | Stores conditions based on the results of vector operations |
| Machine State Register | 1 | |
| Register Type | Number | Purpose |
| :----------------------------------------- | :--------------------- | :------------------------------------------------------------------ |
| General Purpose (GPR) | 32 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Floating Point (FPR) | 32 | Calculate, Store, and Load 32-bit or 64-bit floating-point numbers |
| Special Purpose (SPR) | Up to 1024 (in theory) | Store and load specialized 32-bit fixed-point numbers |
| Segment (SR) | 16 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Time Base Facility (TBR) | 2 | Calculate, Store, and Load 32-bit fixed-point numbers |
| Condition Register | 1 | Stores conditions based on the results of fixed-point operations |
| Floating Point Condition Register | 1 | Stores conditions based on the results of floating-point operations |
| Vector Status and Control Register (VSCR) | 1 | Stores conditions based on the results of vector operations |
| Machine State Register (MSR) | 1 | Stores the state of the processor |
# Special Registers
@ -50,6 +48,9 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
| RTC Lower Register (RTCL) | 5 | (601 only) |
| Link Register (LR) | 8 | |
| Counter Quotient Register (CTR) | 9 | |
| Search Description Register (SDR1)| 25 | Specifies starting address of the page table |
| Save and Restore Register 0 (SRR0)| 26 | |
| Save and Restore Register 1 (SRR1)| 27 | |
| Vector Save/Restore | 256 | (G4+) |
| Time Base Lower (TBL) | 268 | (603+) |
| Time Base Upper (TBU) | 269 | (603+) |
@ -58,7 +59,7 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
| Hardware Implementation 0 (HID0) | 1008 | |
| Hardware Implementation 1 (HID1) | 1009 | |
# HID 0
## HID 0
| Model | Bits Enabled |
| :------------ | :------------------ |
@ -70,6 +71,34 @@ Up to 128 instruction entries and 128 data entries can be stored at a time.
| 604E | NHR |
| 750 (G3) | NHR, DOZE/NAP/SLEEP |
# Exceptions
nnn is either 0x000 or 0xFFF, depending on the 25th bit (0x40) set in the MSR. Usually, the 25th bit is set when booting up a system and unset after it is set.
| Exception | Address |
| :------------------------------------ | :--------- |
| System Reset | 0xnnn00100 |
| Machine Check | 0xnnn00200 |
| DSI | 0xnnn00300 |
| ISI | 0xnnn00400 |
| External Interrupt | 0xnnn00500 |
| Alignment | 0xnnn00600 |
| Program | 0xnnn00700 |
| Floating Point Unavailable | 0xnnn00800 |
| Decrementer | 0xnnn00900 |
| System Call | 0xnnn00C00 |
| Trace | 0xnnn00D00 |
| Performance Monitor (G3+) | 0xnnn00F00 |
| AltiVec Unavailable (G4+) | 0xnnn00F20 |
| Instruction Address Breakpoint (G3+) | 0xnnn01300 |
| System Management Interrupt (G3+) | 0xnnn01400 |
| AltiVec Assist (G4+) | 0xnnn01600 |
| Thermal Management Interrupt (G3+) | 0xnnn01700 |
# Endianness
PowerPC supports both big-endian and little-endian modes. Mac OS largely operates in big-endian mode, due to its 68k heritage.
# Eccentricities
* The HW Init routine used in the ROMs uses the DEC (decrement; SPR 22) register to measure CPU speed. With a PowerPC 601, the DEC register operates on the same frequency as RTC - 7.8125 MHz but uses only 25 most significant bits. In other words, it decrements by 128 at 1/7.8125 MHz.

17
zdocs/developers/dbdma.md
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@ -14,7 +14,7 @@ The Description-Based Direct Memory Access (DBDMA) relies on memory-based descri
| AUDIO IN | 0x9 |
| SCSI1 | 0xA |
What's notable about the registers is that they are in little-endian format.
What's notable about the registers is that they are in little-endian format, thus Mac OS uses the stwbrx and lwbrx instructions to store values.
| Register | Offset |
|:-----------------:|:------:|
@ -52,7 +52,20 @@ What's notable about the registers is that they are in little-endian format.
| KEY_SYSTEM | 0x6 |
| KEY_DEVICE | 0x7 |
# References
## Control Register
| Value | Offset |
|:-----------:|:------:|
| Branch | 0x100 |
| Active | 0x400 |
| Dead | 0x800 |
| Wake | 0x1000 |
| Flush | 0x2000 |
| Pause | 0x4000 |
| Run | 0x8000 |
## References
* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_io.pdf
* https://stuff.mit.edu/afs/sipb/contrib/doc/specs/protocol/chrp/chrp_hrpa.pdf

16
zdocs/developers/valkyrie.md Normal file
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@ -0,0 +1,16 @@
The Valkyrie video chip is included in some Quadras and Performas. The Marathon games (2 and Infinity, at least) use this chip to blit 16-bit video.
| Register Name | Offset |
|:-------------------------:|:------:|
| CLUT Address | 0x4000 |
| CLUT Graphic | 0x4004 |
| CLUT Video Data | 0x4008 |
| CLUT Color Key | 0x400C |
| Subsystem Config | 0xA00C |
| Video In Control | 0xA020 |
| Window X Start | 0xA060 |
| Window Y Start | 0xA064 |
| Window Width | 0xA070 |
| Window Height | 0xA074 |
| Video Field X Start | 0xA080 |
| Video Field Y Start | 0xA084 |