From 8d30fea63bcd87d3a94e4205e01a73c2e40161cc Mon Sep 17 00:00:00 2001 From: Maxim Poliakovski Date: Fri, 9 Feb 2024 09:49:33 +0100 Subject: [PATCH] platinum: implement video emulation. --- devices/memctrl/platinum.cpp | 321 ++++++++++++++++++++++++++++++----- devices/memctrl/platinum.h | 99 +++++++++-- 2 files changed, 369 insertions(+), 51 deletions(-) diff --git a/devices/memctrl/platinum.cpp b/devices/memctrl/platinum.cpp index 7e275cf..0676d86 100644 --- a/devices/memctrl/platinum.cpp +++ b/devices/memctrl/platinum.cpp @@ -1,6 +1,6 @@ /* DingusPPC - The Experimental PowerPC Macintosh emulator -Copyright (C) 2018-22 divingkatae and maximum +Copyright (C) 2018-24 divingkatae and maximum (theweirdo) spatium (Contact divingkatae#1017 or powermax#2286 on Discord for more info) @@ -21,41 +21,101 @@ along with this program. If not, see . /** Platinum Memory/Display Controller emulation. */ +#include #include +#include #include #include #include +#include +#include #include using namespace Platinum; -PlatinumCtrl::PlatinumCtrl() : MemCtrlBase() -{ - this->name = "Platinum Memory Controller"; +PlatinumCtrl::PlatinumCtrl() : MemCtrlBase(), VideoCtrlBase(640, 480) { + set_name("Platinum"); supports_types(HWCompType::MEM_CTRL | HWCompType::MMIO_DEV); + // add MMIO region for VRAM + add_mmio_region(VRAM_REGION_BASE, 0x01000000, this); + // add MMIO region for the configuration and status registers - add_mmio_region(0xF8000000, 0x500, this); + add_mmio_region(PLATINUM_IOREG_BASE, 0x500, this); - // determine actual VRAM size (min. 1MB, max. 4MB) - this->vram_size = 1 << 20; + // get VRAM size + this->vram_megs = GET_INT_PROP("gfxmem_size"); + this->vram_size = this->vram_megs << 20; - // insert video memory region into the main memory map - this->add_ram_region(0xF1000000UL, this->vram_size); + // enable half bank access if 1MB VRAM + FB_CONFIG_1[CFG1_FULL_BANKS] = 1 + this->half_bank = !!(this->vram_megs == 1); + this->half_access = 0; + + // allocate VRAM + this->vram_ptr = std::unique_ptr (new uint8_t[this->vram_size]); // initialize the CPUID register with the following CPU: - // PowerPC 601 @ 75 MHz, bus frequency: 37,5 MHz - this->cpu_id = (0x3001 << 16) | ClkSrc3 | (CpuSpeed3::CPU_75_BUS_38 << 8); + // PowerPC 601 @ 90 MHz, bus frequency: 45 MHz + this->cpu_id = (0x3001 << 16) | ClkSrc2 | (CpuSpeed2::CPU_90_BUS_45 << 8); this->display_id = std::unique_ptr (new DisplayID()); + + // attach DACula RAMDAC + this->dacula = std::unique_ptr(new AppleRamdac(DacFlavour::DACULA)); + this->dacula->set_clut_entry_cb = [this](uint8_t index, uint8_t *colors) { + this->set_palette_color(index, colors[0], colors[1], colors[2], 0xFF); + }; + this->dacula->cursor_ctrl_cb = [this](bool cursor_on) { + if (cursor_on) { + this->dacula->measure_hw_cursor(&this->vram_ptr[this->fb_offset]); + this->cursor_ovl_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->dacula->draw_hw_cursor(&this->vram_ptr[this->fb_offset], + dst_buf, dst_pitch); + }; + } else { + this->cursor_ovl_cb = nullptr; + } + }; } -uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size) -{ +int PlatinumCtrl::device_postinit() { + // register DACula with the I/O controller as IOBus Device #2 + GrandCentral* gc_obj = dynamic_cast(gMachineObj->get_comp_by_name("GrandCentral")); + gc_obj->attach_iodevice(1, this->dacula.get()); + + this->int_ctrl = dynamic_cast( + gMachineObj->get_comp_by_type(HWCompType::INT_CTRL)); + this->irq_id = 1UL << 30; // FIXME: hardcoded IRQ ID + + this->vbl_cb = [this](uint8_t irq_line_state) { + this->update_irq(irq_line_state, SWATCH_INT_VBL); + }; + + return 0; +} + +uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size) { + if (rgn_start == VRAM_REGION_BASE) { + if (offset < this->vram_size) { + // HACK: half bank configurations should return invalid data + // for the lower DWORD (in the PPC order!) to be recognized. + // The simplest way to achieve that is to redirect access + // to the upper DWORD by setting bit 2 of the address. + if (this->half_access) + offset |= 4; + return read_mem(&this->vram_ptr[offset], size); + } else { + LOG_F(WARNING, "%s: read from unmapped aperture address 0x%X", + this->name.c_str(), this->fb_addr + offset); + return (uint32_t)-1; + } + } + if (size != 4) { - LOG_F(WARNING, "Platinum: unsupported register access size %d!", size); + LOG_F(WARNING, "%s: unsupported register access size %d!", this->name.c_str(), + size); return 0; } @@ -78,10 +138,21 @@ uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size) case PlatinumReg::FB_BASE_ADDR: return this->fb_addr; case PlatinumReg::MON_ID_SENSE: - LOG_F(INFO, "Platinum: display sense read"); - return (this->cur_mon_id ^ 7); + return (this->mon_sense ^ 7); + case PlatinumReg::SWATCH_CONFIG: + return this->swatch_config; + case PlatinumReg::SWATCH_INT_STAT: + return this->swatch_int_stat; + case PlatinumReg::CLR_CURSOR_INT: + this->update_irq(0, SWATCH_INT_CURSOR); + return 0; + case PlatinumReg::TIMING_ADJUST: + return this->timing_adjust; + case PlatinumReg::IRIDIUM_CONFIG: + return this->iridium_cfg; default: - LOG_F(WARNING, "Platinum: unknown register read at offset 0x%X", offset); + LOG_F(WARNING, "%s: unknown register read at offset 0x%X", this->name.c_str(), + offset); } return 0; @@ -89,6 +160,15 @@ uint32_t PlatinumCtrl::read(uint32_t rgn_start, uint32_t offset, int size) void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) { + if (rgn_start == VRAM_REGION_BASE) { + if (offset < this->vram_size) + write_mem(&this->vram_ptr[offset], value, size); + else + LOG_F(WARNING, "%s: write to unmapped aperture address 0x%X", + this->name.c_str(), this->fb_addr + offset); + return; + } + switch (offset) { case PlatinumReg::ROM_TIMING: this->rom_timing = value; @@ -110,11 +190,18 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4] = value; break; case PlatinumReg::FB_BASE_ADDR: - this->fb_addr = value; - LOG_F(INFO, "Platinum: Framebuffer address set to 0x%X", value); + this->fb_addr = value; + this->fb_offset = value & 0x3FFFFF; + break; + case PlatinumReg::ROW_WORDS: + this->row_words = value & ~7; + break; + case PlatinumReg::CLOCK_DIVISOR: + this->clock_divisor = value; break; case PlatinumReg::FB_CONFIG_1: this->fb_config_1 = value; + this->half_bank = !!(this->vram_megs == 1 && (value & CFG1_FULL_BANKS)); break; case PlatinumReg::FB_CONFIG_2: this->fb_config_2 = value; @@ -123,11 +210,30 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in this->vmem_fp_mode = value; break; case PlatinumReg::MON_ID_SENSE: - LOG_F(INFO, "Platinum: display sense written with 0x%X", value); - this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7); + value &= 7; + this->mon_sense = this->display_id->read_monitor_sense(value, value ^ 7) + << (value ^ 7); break; case PlatinumReg::FB_RESET: + static uint8_t vid_enable_seq[] = {3, 2, 0}; + + if (value == 7 && this->crtc_on) { + LOG_F(INFO, "%s: video disabled", this->name.c_str()); + this->reset_step = 0; + } else if (value == vid_enable_seq[this->reset_step]) { + if (++this->reset_step >= 3) { + if (this->fb_config_1 & CFG1_VID_ENABLE) { + LOG_F(INFO, "%s: video enabled", this->name.c_str()); + this->enable_display(); + } else { + this->blank_display(); + } + this->reset_step = 0; + } + } else + this->reset_step = 0; this->fb_reset = value; + this->half_access = !!(this->half_bank && value == 6); break; case PlatinumReg::VRAM_REFRESH: this->vram_refresh = value; @@ -137,31 +243,50 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in break; case PlatinumReg::SWATCH_INT_MASK: this->swatch_int_mask = value; + if (this->swatch_int_mask & SWATCH_INT_VBL) + LOG_F(INFO, "%s: VBL interrupt enabled", this->name.c_str()); break; + case PlatinumReg::CURSOR_LINE: + this->cursor_line = value; + if (this->swatch_int_mask & SWATCH_INT_CURSOR) + this->enable_cursor_int(); + break; + case PlatinumReg::SWATCH_HSERR: + case PlatinumReg::SWATCH_HLFLN: + case PlatinumReg::SWATCH_HEQ: + case PlatinumReg::SWATCH_HSP: + case PlatinumReg::SWATCH_HBWAY: + case PlatinumReg::SWATCH_HBRST: + case PlatinumReg::SWATCH_HBP: case PlatinumReg::SWATCH_HAL: - LOG_F(INFO, "Swatch HAL set to 0x%X", value); - break; case PlatinumReg::SWATCH_HFP: - LOG_F(INFO, "Swatch HFP set to 0x%X", value); - break; case PlatinumReg::SWATCH_HPIX: - LOG_F(INFO, "Swatch HPIX set to 0x%X", value); - break; + case PlatinumReg::SWATCH_VHLINE: + case PlatinumReg::SWATCH_VSYNC: + case PlatinumReg::SWATCH_VBPEQ: + case PlatinumReg::SWATCH_VBP: case PlatinumReg::SWATCH_VAL: - LOG_F(INFO, "Swatch VAL set to 0x%X", value); - break; case PlatinumReg::SWATCH_VFP: - LOG_F(INFO, "Swatch VFP set to 0x%X", value); + case PlatinumReg::SWATCH_VFPEQ: + this->swatch_params[REG_TO_INDEX(offset)] = value; + break; + case PlatinumReg::TIMING_ADJUST: + this->timing_adjust = value; + break; + case PlatinumReg::IRIDIUM_CONFIG: + if (!(value & 1)) + ABORT_F("%s: little-endian system bus is not implemented", this->name.c_str()); + this->iridium_cfg = (this->iridium_cfg & ~7) | (value & 7); break; default: - LOG_F(WARNING, "Platinum: unknown register write at offset 0x%X", offset); + LOG_F(WARNING, "%s: unknown register write at offset 0x%X", this->name.c_str(), + offset); } } -void PlatinumCtrl::insert_ram_dimm(int slot_num, uint32_t capacity) -{ +void PlatinumCtrl::insert_ram_dimm(int slot_num, uint32_t capacity) { if (slot_num < 0 || slot_num >= 4) { - ABORT_F("Platinum: invalid DIMM slot %d", slot_num); + ABORT_F("%s: invalid DIMM slot %d", this->name.c_str(), slot_num); } switch (capacity) { @@ -178,12 +303,11 @@ void PlatinumCtrl::insert_ram_dimm(int slot_num, uint32_t capacity) this->bank_size[slot_num * 2 + 1] = DRAM_CAP_64MB; break; default: - ABORT_F("Platinum: unsupported DRAM capacity %d", capacity); + ABORT_F("%s: unsupported DRAM capacity %d", this->name.c_str(), capacity); } } -void PlatinumCtrl::map_phys_ram() -{ +void PlatinumCtrl::map_phys_ram() { uint32_t total_ram = 0; for (int i = 0; i < 8; i++) { @@ -191,16 +315,133 @@ void PlatinumCtrl::map_phys_ram() } if (total_ram > DRAM_CAP_64MB) { - ABORT_F("Platinum: RAM bigger than 64MB not supported yet"); + ABORT_F("%s: RAM bigger than 64MB not supported yet", this->name.c_str()); } if (!add_ram_region(0x00000000, total_ram)) { - ABORT_F("Platinum: could not allocate RAM storage"); + ABORT_F("%s: could not allocate RAM storage", this->name.c_str()); } } +// ====================== Framebuffer controller stuff ======================= +void PlatinumCtrl::enable_display() { + int clock_divisor = this->dacula->get_clock_div(); + + this->pixel_clock = this->dacula->get_dot_freq(); + + // calculate active_width and active_height from Swatch parameters + int new_width = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HFP)] - + swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HAL)]; + int new_height = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VFP)] - + swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VAL)]; + + this->hori_blank = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HAL)] + + (swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HSP)] - + swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_HFP)]); + + new_width *= clock_divisor; + this->hori_blank *= clock_divisor; + + this->vert_blank = swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VAL)] + + (swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VSYNC)] - + swatch_params[REG_TO_INDEX(PlatinumReg::SWATCH_VFP)]); + + if (!(this->fb_config_1 & CFG1_INTERLACE)) { + new_height >>= 1; + this->vert_blank >>= 1; + } + + this->active_width = new_width; + this->active_height = new_height; + + this->hori_total = this->hori_blank + new_width; + this->vert_total = this->vert_blank + new_height; + + // set framebuffer parameters + this->fb_ptr = &this->vram_ptr[this->fb_offset]; + this->fb_pitch = this->row_words; + + this->pixel_depth = this->dacula->get_pix_width(); + if (pixel_depth > 8) + this->fb_ptr += 16; + + // attach framebuffer conversion routine + switch (this->pixel_depth) { + case 8: + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_8bpp_indexed(dst_buf, dst_pitch); + }; + break; + case 16: + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_15bpp_BE(dst_buf, dst_pitch); + }; + break; + case 32: + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_32bpp_BE(dst_buf, dst_pitch); + }; + break; + default: + ABORT_F("%s: invalid pixel width %d", this->name.c_str(), this->pixel_depth); + } + + this->dacula->set_fb_parameters(this->active_width, this->active_height, this->fb_pitch); + + this->stop_refresh_task(); + + this->refresh_rate = (double)(this->pixel_clock) / (this->hori_total * this->vert_total); + this->start_refresh_task(); + + LOG_F(INFO, "%s: video width=%d, height=%d", this->name.c_str(), new_width, new_height); + LOG_F(INFO, "%s: refresh rate set to %f Hz", this->name.c_str(), this->refresh_rate); + + this->blank_on = false; + this->crtc_on = true; +} + +void PlatinumCtrl::enable_cursor_int() { + if (!(this->swatch_int_mask & SWATCH_INT_CURSOR)) + return; + + uint64_t cursor_int_freq = static_cast((1.0f / (double)this->pixel_clock) * + this->hori_total * this->cursor_line * NS_PER_SEC + 0.5f); + LOG_F(INFO, "%s: cursor interrupt frequency %lld ns", this->name.c_str(), + cursor_int_freq); + + if (this->cursor_task_id) + TimerManager::get_instance()->cancel_timer(this->cursor_task_id); + + this->cursor_task_id = TimerManager::get_instance()->add_cyclic_timer( + cursor_int_freq, + [this]() { + this->update_irq(1, SWATCH_INT_CURSOR); // generate cursor interrupt + } + ); +} + +void PlatinumCtrl::update_irq(uint8_t irq_line_state, uint8_t irq_mask) { + if (irq_line_state != !!(this->swatch_int_stat & irq_mask)) { + if (irq_line_state) + this->swatch_int_stat |= irq_mask; + else + this->swatch_int_stat &= ~irq_mask; + + if (this->swatch_int_mask & irq_mask) + this->int_ctrl->ack_int(this->irq_id, irq_line_state); + } +} + +// ========================== Device registry stuff ========================== +static const PropMap Platinum_Properties = { + {"gfxmem_size", + new IntProperty(1, vector({1, 2, 4}))}, + {"mon_id", + new StrProperty("HiRes12-14in")}, +}; + static const DeviceDescription Platinum_Descriptor = { - PlatinumCtrl::create, {}, {} + PlatinumCtrl::create, {}, Platinum_Properties }; REGISTER_DEVICE(Platinum, Platinum_Descriptor); diff --git a/devices/memctrl/platinum.h b/devices/memctrl/platinum.h index f47a242..264ce2e 100644 --- a/devices/memctrl/platinum.h +++ b/devices/memctrl/platinum.h @@ -1,6 +1,6 @@ /* DingusPPC - The Experimental PowerPC Macintosh emulator -Copyright (C) 2018-22 divingkatae and maximum +Copyright (C) 2018-24 divingkatae and maximum (theweirdo) spatium (Contact divingkatae#1017 or powermax#2286 on Discord for more info) @@ -23,7 +23,7 @@ along with this program. If not, see . Author: Max Poliakovski - Platinum is a single chip memory and video subsystem controller designed + Platinum is a single-chip memory and video subsystem controller designed especially for the Power Macintosh 7200 computer, code name Catalyst. */ @@ -33,7 +33,9 @@ along with this program. If not, see . #include #include #include +#include #include +#include #include #include @@ -120,22 +122,58 @@ enum PlatinumReg : uint32_t { GP_SW_SCRATCH = 0x0E0, PCI_ADDR_MASK = 0x0F0, FB_BASE_ADDR = 0x100, + ROW_WORDS = 0x120, + CLOCK_DIVISOR = 0x130, FB_CONFIG_1 = 0x140, FB_CONFIG_2 = 0x150, VMEM_PAGE_MODE = 0x160, MON_ID_SENSE = 0x170, FB_RESET = 0x180, VRAM_REFRESH = 0x1B0, + + // Swatch timing generator registers SWATCH_CONFIG = 0x200, SWATCH_INT_MASK = 0x210, + SWATCH_INT_STAT = 0x220, + CLR_CURSOR_INT = 0x230, + CLR_ANIM_INT = 0x240, + CLR_VBL_INT = 0x250, + CURSOR_LINE = 0x260, + ANIMATE_LINE = 0x270, + COUNTER_TEST = 0x280, + SWATCH_HSERR = 0x290, + SWATCH_HLFLN = 0x2A0, + SWATCH_HEQ = 0x2B0, + SWATCH_HSP = 0x2C0, + SWATCH_HBWAY = 0x2D0, + SWATCH_HBRST = 0x2E0, + SWATCH_HBP = 0x2F0, SWATCH_HAL = 0x300, SWATCH_HFP = 0x310, SWATCH_HPIX = 0x320, + SWATCH_VHLINE = 0x330, + SWATCH_VSYNC = 0x340, + SWATCH_VBPEQ = 0x350, + SWATCH_VBP = 0x360, SWATCH_VAL = 0x370, SWATCH_VFP = 0x380, + SWATCH_VFPEQ = 0x390, + TIMING_ADJUST = 0x3A0, + CURRENT_LINE = 0x3B0, + + // Iridium datapath registers IRIDIUM_CONFIG = 0x4A0, }; +#define REG_TO_INDEX(reg) ((((reg) - SWATCH_HSERR) >> 4) & 0xF) + +// FB_CONFIG_1 register bits. +enum { + CFG1_INTERLACE = (1 << 2), // 1 - interlaced video enabled + CFG1_VID_ENABLE = (1 << 4), // 1 - display refresh enabled + CFG1_FULL_BANKS = (1 << 12), // full VRAM banks (64-bit) access enable +}; + // FB_RESET register bits. enum { VRAM_SM_RESET = (1 << 0), // VRAM state machine reset @@ -143,9 +181,22 @@ enum { SWATCH_RESET = (1 << 2), // Swatch reset }; +// SWATCH_INT_MASK register bits. +enum { + SWATCH_INT_VBL = (1 << 0), + SWATCH_INT_ANIM = (1 << 1), + SWATCH_INT_CURSOR = (1 << 2) +}; + +#define DAMFB_VERSION_PLATINUM 6 // DAMFB cell version in the Platinum ASIC +#define IRIDIUM_VENDOR_VLSI 0 // Vendor ID for the Iridium ASIC => VLSI + +constexpr auto VRAM_REGION_BASE = 0xF1000000UL; +constexpr auto PLATINUM_IOREG_BASE = 0xF8000000UL; + }; // namespace Platinum -class PlatinumCtrl : public MemCtrlBase, public MMIODevice { +class PlatinumCtrl : public MemCtrlBase, public VideoCtrlBase, public MMIODevice { public: PlatinumCtrl(); ~PlatinumCtrl() = default; @@ -154,13 +205,21 @@ public: return std::unique_ptr(new PlatinumCtrl()); } - /* MMIODevice methods */ + // HWComponent methods + int device_postinit(); + + // MMIODevice methods uint32_t read(uint32_t rgn_start, uint32_t offset, int size); void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size); void insert_ram_dimm(int slot_num, uint32_t capacity); void map_phys_ram(); +protected: + void enable_display(); + void enable_cursor_int(); + void update_irq(uint8_t irq_line_state, uint8_t irq_mask); + private: uint32_t cpu_id; uint8_t cpu_type; // 0 - MPC601, 1 - 603/604 CPU @@ -170,23 +229,41 @@ private: uint32_t dram_timing = 0xEFF; uint32_t dram_refresh = 0x1F4; uint32_t bank_base[8]; - uint32_t bank_size[8] = { 0 }; + uint32_t bank_size[8] = {}; - // display controller state - uint32_t fb_addr = 0xF1000000; + // frame buffer controller state + uint32_t fb_addr = Platinum::VRAM_REGION_BASE; + uint32_t fb_offset = 0; uint32_t fb_config_1 = 0x1F00; uint32_t fb_config_2 = 0x1FFF; + uint32_t clock_divisor = 0; + uint32_t row_words = 0; uint32_t fb_reset = 7; + int reset_step = 0; + uint32_t fb_test = DAMFB_VERSION_PLATINUM << 9; uint32_t vram_refresh = 0x1F4; uint32_t vram_size = 0; + uint32_t iridium_cfg = (IRIDIUM_VENDOR_VLSI << 24) | 1; // big-endian bus + uint8_t vram_megs = 0; + uint8_t half_bank = 0; + uint8_t half_access = 0; uint8_t vmem_fp_mode = 0; - uint8_t cur_mon_id = 0; + uint8_t mon_sense = 0; // video timing generator (Swatch) state - uint32_t swatch_config = 0xFFD; - uint32_t swatch_int_mask = 0; + uint32_t swatch_config = 0xFFD; + uint32_t swatch_params[17] = {}; + uint32_t timing_adjust = 0; - std::unique_ptr display_id; + // interrupt related state + uint32_t swatch_int_mask = 0; + uint32_t swatch_int_stat = 0; + uint32_t cursor_line = 0; + uint32_t cursor_task_id = 0; + + std::unique_ptr vram_ptr = nullptr; + std::unique_ptr display_id = nullptr; + std::unique_ptr dacula = nullptr; }; #endif // PLATINUM_MEMCTRL_H