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platinum: implement video controller registers.
This commit is contained in:
Maxim Poliakovski
parent
8889759f33
commit
913944c607
@ -19,12 +19,14 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/** Platinum Memory Controller emulation. */
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/** Platinum Memory/Display Controller emulation. */
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#include "platinum.h"
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#include <devices/memctrl/platinum.h>
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#include <devices/video/displayid.h>
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#include <loguru.hpp>
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#include <cinttypes>
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#include <memory>
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using namespace Platinum;
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@ -35,9 +37,17 @@ PlatinumCtrl::PlatinumCtrl() : MemCtrlBase()
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// add MMIO region for the configuration and status registers
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add_mmio_region(0xF8000000, 0x500, this);
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// determine actual VRAM size (min. 1MB, max. 4MB)
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this->vram_size = 1 << 20;
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// insert video memory region into the main memory map
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this->add_ram_region(0xF1000000UL, this->vram_size);
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// initialize the CPUID register with the following CPU:
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// PowerPC 601 @ 75 MHz, bus frequency: 37,5 MHz
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this->cpu_id = (0x3001 << 16) | ClkSrc3 | (CpuSpeed3::CPU_75_BUS_38 << 8);
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this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
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}
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uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size)
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@ -63,6 +73,11 @@ uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size)
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return this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4];
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case PlatinumReg::CACHE_CONFIG:
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return 0; // report no L2 cache installed
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case PlatinumReg::FB_BASE_ADDR:
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return this->fb_addr;
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case PlatinumReg::MON_ID_SENSE:
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LOG_F(INFO, "Platinum: display sense read");
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return (this->cur_mon_id ^ 7);
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default:
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LOG_F(WARNING, "Platinum: unknown register read at offset 0x%X", offset);
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}
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@ -82,12 +97,6 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
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case PlatinumReg::DRAM_REFRESH:
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this->dram_refresh = value;
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break;
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case PlatinumReg::FB_CONFIG_2:
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this->fb_config_2 = value;
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break;
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case PlatinumReg::VRAM_REFRESH:
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this->vram_refresh = value;
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break;
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case PlatinumReg::BANK_0_BASE:
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case PlatinumReg::BANK_1_BASE:
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case PlatinumReg::BANK_2_BASE:
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@ -98,6 +107,50 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
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case PlatinumReg::BANK_7_BASE:
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this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4] = value;
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break;
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case PlatinumReg::FB_BASE_ADDR:
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this->fb_addr = value;
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LOG_F(INFO, "Platinum: Framebuffer address set to 0x%X", value);
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break;
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case PlatinumReg::FB_CONFIG_1:
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this->fb_config_1 = value;
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break;
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case PlatinumReg::FB_CONFIG_2:
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this->fb_config_2 = value;
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break;
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case PlatinumReg::VMEM_PAGE_MODE:
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this->vmem_fp_mode = value;
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break;
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case PlatinumReg::MON_ID_SENSE:
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LOG_F(INFO, "Platinum: display sense written with 0x%X", value);
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this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
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break;
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case PlatinumReg::FB_RESET:
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this->fb_reset = value;
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break;
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case PlatinumReg::VRAM_REFRESH:
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this->vram_refresh = value;
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break;
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case PlatinumReg::SWATCH_CONFIG:
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this->swatch_config = value;
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break;
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case PlatinumReg::SWATCH_INT_MASK:
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this->swatch_int_mask = value;
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break;
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case PlatinumReg::SWATCH_HAL:
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LOG_F(INFO, "Swatch HAL set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_HFP:
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LOG_F(INFO, "Swatch HFP set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_HPIX:
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LOG_F(INFO, "Swatch HPIX set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_VAL:
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LOG_F(INFO, "Swatch VAL set to 0x%X", value);
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break;
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case PlatinumReg::SWATCH_VFP:
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LOG_F(INFO, "Swatch VFP set to 0x%X", value);
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break;
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default:
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LOG_F(WARNING, "Platinum: unknown register write at offset 0x%X", offset);
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}
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@ -33,8 +33,10 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <devices/common/hwcomponent.h>
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#include <devices/common/mmiodevice.h>
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#include <devices/memctrl/memctrlbase.h>
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#include <devices/video/displayid.h>
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#include <cinttypes>
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#include <memory>
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namespace Platinum {
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@ -101,25 +103,37 @@ enum CpuSpeed3 {
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/** Configuration and status register offsets. */
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enum PlatinumReg : uint32_t {
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CPU_ID = 0x000,
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ASIC_REVISION = 0x010,
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ROM_TIMING = 0x020,
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CACHE_CONFIG = 0x030,
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DRAM_TIMING = 0x040,
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DRAM_REFRESH = 0x050,
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BANK_0_BASE = 0x060,
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BANK_1_BASE = 0x070,
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BANK_2_BASE = 0x080,
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BANK_3_BASE = 0x090,
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BANK_4_BASE = 0x0A0,
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BANK_5_BASE = 0x0B0,
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BANK_6_BASE = 0x0C0,
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BANK_7_BASE = 0x0D0,
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GP_SW_SCRATCH = 0x0E0,
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PCI_ADDR_MASK = 0x0F0,
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FB_CONFIG_1 = 0x140,
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FB_CONFIG_2 = 0x150,
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VRAM_REFRESH = 0x1B0,
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CPU_ID = 0x000,
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ASIC_REVISION = 0x010,
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ROM_TIMING = 0x020,
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CACHE_CONFIG = 0x030,
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DRAM_TIMING = 0x040,
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DRAM_REFRESH = 0x050,
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BANK_0_BASE = 0x060,
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BANK_1_BASE = 0x070,
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BANK_2_BASE = 0x080,
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BANK_3_BASE = 0x090,
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BANK_4_BASE = 0x0A0,
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BANK_5_BASE = 0x0B0,
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BANK_6_BASE = 0x0C0,
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BANK_7_BASE = 0x0D0,
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GP_SW_SCRATCH = 0x0E0,
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PCI_ADDR_MASK = 0x0F0,
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FB_BASE_ADDR = 0x100,
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FB_CONFIG_1 = 0x140,
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FB_CONFIG_2 = 0x150,
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VMEM_PAGE_MODE = 0x160,
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MON_ID_SENSE = 0x170,
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FB_RESET = 0x180,
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VRAM_REFRESH = 0x1B0,
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SWATCH_CONFIG = 0x200,
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SWATCH_INT_MASK = 0x210,
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SWATCH_HAL = 0x300,
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SWATCH_HFP = 0x310,
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SWATCH_HPIX = 0x320,
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SWATCH_VAL = 0x370,
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SWATCH_VFP = 0x380,
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IRIDIUM_CONFIG = 0x4A0,
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};
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enum {
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@ -132,6 +146,13 @@ enum {
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DRAM_CAP_128MB = (1 << 27),
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};
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// FB_RESET register bits.
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enum {
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VRAM_SM_RESET = (1 << 0), // VRAM state machine reset
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VREFRESH_SM_RESET = (1 << 1), // Video refresh state machine reset
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SWATCH_RESET = (1 << 2), // Swatch reset
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};
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}; // namespace Platinum
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class PlatinumCtrl : public MemCtrlBase, public MMIODevice {
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@ -158,10 +179,24 @@ private:
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uint32_t rom_timing = 0;
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uint32_t dram_timing = 0xEFF;
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uint32_t dram_refresh = 0x1F4;
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uint32_t fb_config_2 = 0x1FFF;
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uint32_t vram_refresh = 0x1F4;
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uint32_t bank_base[8];
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uint32_t bank_size[8] = { 0 };
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// display controller state
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uint32_t fb_addr = 0xF1000000;
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uint32_t fb_config_1 = 0x1F00;
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uint32_t fb_config_2 = 0x1FFF;
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uint32_t fb_reset = 7;
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uint32_t vram_refresh = 0x1F4;
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uint32_t vram_size = 0;
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uint8_t vmem_fp_mode = 0;
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uint8_t cur_mon_id = 0;
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// video timing generator (Swatch) state
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uint32_t swatch_config = 0xFFD;
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uint32_t swatch_int_mask = 0;
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std::unique_ptr<DisplayID> display_id;
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};
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#endif // PLATINUM_MEMCTRL_H
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@ -83,7 +83,7 @@ static const PropMap CatalystSettings = {
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{"gfxmem_size",
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new IntProperty( 1, vector<uint32_t>({1, 2, 4}))},
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{"mon_id",
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new StrProperty("")},
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new StrProperty("HiRes12-14in")},
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{"fdd_img",
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new StrProperty("")},
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{"serial_backend", new StrProperty("null", CharIoBackends)},
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