Macintosh-Tools
/
dingusppc
mirror of https://github.com/dingusdev/dingusppc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

platinum: implement video controller registers.

This commit is contained in:
Maxim Poliakovski 2022-06-09 23:16:03 +02:00
parent 8889759f33
commit 913944c607
3 changed files with 118 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
devices/memctrl/platinum.cpp
View File

@ -19,12 +19,14 @@ You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
/** Platinum Memory Controller emulation. */
/** Platinum Memory/Display Controller emulation. */
#include "platinum.h"
#include <devices/memctrl/platinum.h>
#include <devices/video/displayid.h>
#include <loguru.hpp>
#include <cinttypes>
#include <memory>
using namespace Platinum;
@ -35,9 +37,17 @@ PlatinumCtrl::PlatinumCtrl() : MemCtrlBase()
// add MMIO region for the configuration and status registers
add_mmio_region(0xF8000000, 0x500, this);
// determine actual VRAM size (min. 1MB, max. 4MB)
this->vram_size = 1 << 20;
// insert video memory region into the main memory map
this->add_ram_region(0xF1000000UL, this->vram_size);
// initialize the CPUID register with the following CPU:
// PowerPC 601 @ 75 MHz, bus frequency: 37,5 MHz
this->cpu_id = (0x3001 << 16) | ClkSrc3 | (CpuSpeed3::CPU_75_BUS_38 << 8);
this->display_id = std::unique_ptr<DisplayID> (new DisplayID());
}
uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size)
@ -63,6 +73,11 @@ uint32_t PlatinumCtrl::read(uint32_t reg_start, uint32_t offset, int size)
return this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4];
case PlatinumReg::CACHE_CONFIG:
return 0; // report no L2 cache installed
case PlatinumReg::FB_BASE_ADDR:
return this->fb_addr;
case PlatinumReg::MON_ID_SENSE:
LOG_F(INFO, "Platinum: display sense read");
return (this->cur_mon_id ^ 7);
default:
LOG_F(WARNING, "Platinum: unknown register read at offset 0x%X", offset);
}
@ -82,12 +97,6 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
case PlatinumReg::DRAM_REFRESH:
this->dram_refresh = value;
break;
case PlatinumReg::FB_CONFIG_2:
this->fb_config_2 = value;
break;
case PlatinumReg::VRAM_REFRESH:
this->vram_refresh = value;
break;
case PlatinumReg::BANK_0_BASE:
case PlatinumReg::BANK_1_BASE:
case PlatinumReg::BANK_2_BASE:
@ -98,6 +107,50 @@ void PlatinumCtrl::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
case PlatinumReg::BANK_7_BASE:
this->bank_base[(offset - PlatinumReg::BANK_0_BASE) >> 4] = value;
break;
case PlatinumReg::FB_BASE_ADDR:
this->fb_addr = value;
LOG_F(INFO, "Platinum: Framebuffer address set to 0x%X", value);
break;
case PlatinumReg::FB_CONFIG_1:
this->fb_config_1 = value;
break;
case PlatinumReg::FB_CONFIG_2:
this->fb_config_2 = value;
break;
case PlatinumReg::VMEM_PAGE_MODE:
this->vmem_fp_mode = value;
break;
case PlatinumReg::MON_ID_SENSE:
LOG_F(INFO, "Platinum: display sense written with 0x%X", value);
this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
break;
case PlatinumReg::FB_RESET:
this->fb_reset = value;
break;
case PlatinumReg::VRAM_REFRESH:
this->vram_refresh = value;
break;
case PlatinumReg::SWATCH_CONFIG:
this->swatch_config = value;
break;
case PlatinumReg::SWATCH_INT_MASK:
this->swatch_int_mask = value;
break;
case PlatinumReg::SWATCH_HAL:
LOG_F(INFO, "Swatch HAL set to 0x%X", value);
break;
case PlatinumReg::SWATCH_HFP:
LOG_F(INFO, "Swatch HFP set to 0x%X", value);
break;
case PlatinumReg::SWATCH_HPIX:
LOG_F(INFO, "Swatch HPIX set to 0x%X", value);
break;
case PlatinumReg::SWATCH_VAL:
LOG_F(INFO, "Swatch VAL set to 0x%X", value);
break;
case PlatinumReg::SWATCH_VFP:
LOG_F(INFO, "Swatch VFP set to 0x%X", value);
break;
default:
LOG_F(WARNING, "Platinum: unknown register write at offset 0x%X", offset);
}

77
devices/memctrl/platinum.h
View File

@ -33,8 +33,10 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
#include <devices/common/hwcomponent.h>
#include <devices/common/mmiodevice.h>
#include <devices/memctrl/memctrlbase.h>
#include <devices/video/displayid.h>
#include <cinttypes>
#include <memory>
namespace Platinum {
@ -101,25 +103,37 @@ enum CpuSpeed3 {
/** Configuration and status register offsets. */
enum PlatinumReg : uint32_t {
CPU_ID = 0x000,
ASIC_REVISION = 0x010,
ROM_TIMING = 0x020,
CACHE_CONFIG = 0x030,
DRAM_TIMING = 0x040,
DRAM_REFRESH = 0x050,
BANK_0_BASE = 0x060,
BANK_1_BASE = 0x070,
BANK_2_BASE = 0x080,
BANK_3_BASE = 0x090,
BANK_4_BASE = 0x0A0,
BANK_5_BASE = 0x0B0,
BANK_6_BASE = 0x0C0,
BANK_7_BASE = 0x0D0,
GP_SW_SCRATCH = 0x0E0,
PCI_ADDR_MASK = 0x0F0,
FB_CONFIG_1 = 0x140,
FB_CONFIG_2 = 0x150,
VRAM_REFRESH = 0x1B0,
CPU_ID = 0x000,
ASIC_REVISION = 0x010,
ROM_TIMING = 0x020,
CACHE_CONFIG = 0x030,
DRAM_TIMING = 0x040,
DRAM_REFRESH = 0x050,
BANK_0_BASE = 0x060,
BANK_1_BASE = 0x070,
BANK_2_BASE = 0x080,
BANK_3_BASE = 0x090,
BANK_4_BASE = 0x0A0,
BANK_5_BASE = 0x0B0,
BANK_6_BASE = 0x0C0,
BANK_7_BASE = 0x0D0,
GP_SW_SCRATCH = 0x0E0,
PCI_ADDR_MASK = 0x0F0,
FB_BASE_ADDR = 0x100,
FB_CONFIG_1 = 0x140,
FB_CONFIG_2 = 0x150,
VMEM_PAGE_MODE = 0x160,
MON_ID_SENSE = 0x170,
FB_RESET = 0x180,
VRAM_REFRESH = 0x1B0,
SWATCH_CONFIG = 0x200,
SWATCH_INT_MASK = 0x210,
SWATCH_HAL = 0x300,
SWATCH_HFP = 0x310,
SWATCH_HPIX = 0x320,
SWATCH_VAL = 0x370,
SWATCH_VFP = 0x380,
IRIDIUM_CONFIG = 0x4A0,
};
enum {
@ -132,6 +146,13 @@ enum {
DRAM_CAP_128MB = (1 << 27),
};
// FB_RESET register bits.
enum {
VRAM_SM_RESET = (1 << 0), // VRAM state machine reset
VREFRESH_SM_RESET = (1 << 1), // Video refresh state machine reset
SWATCH_RESET = (1 << 2), // Swatch reset
};
}; // namespace Platinum
class PlatinumCtrl : public MemCtrlBase, public MMIODevice {
@ -158,10 +179,24 @@ private:
uint32_t rom_timing = 0;
uint32_t dram_timing = 0xEFF;
uint32_t dram_refresh = 0x1F4;
uint32_t fb_config_2 = 0x1FFF;
uint32_t vram_refresh = 0x1F4;
uint32_t bank_base[8];
uint32_t bank_size[8] = { 0 };
// display controller state
uint32_t fb_addr = 0xF1000000;
uint32_t fb_config_1 = 0x1F00;
uint32_t fb_config_2 = 0x1FFF;
uint32_t fb_reset = 7;
uint32_t vram_refresh = 0x1F4;
uint32_t vram_size = 0;
uint8_t vmem_fp_mode = 0;
uint8_t cur_mon_id = 0;
// video timing generator (Swatch) state
uint32_t swatch_config = 0xFFD;
uint32_t swatch_int_mask = 0;
std::unique_ptr<DisplayID> display_id;
};
#endif // PLATINUM_MEMCTRL_H

2
machines/machinefactory.cpp
View File

@ -83,7 +83,7 @@ static const PropMap CatalystSettings = {
{"gfxmem_size",
new IntProperty( 1, vector<uint32_t>({1, 2, 4}))},
{"mon_id",
new StrProperty("")},
new StrProperty("HiRes12-14in")},
{"fdd_img",
new StrProperty("")},
{"serial_backend", new StrProperty("null", CharIoBackends)},