dbdma: support INT_SELECT & WAIT_SELECT registers.

This commit is contained in:
Maxim Poliakovski 2023-09-20 00:45:39 +02:00
parent 6eb6a5892d
commit 9db3076a48
2 changed files with 8 additions and 0 deletions

View File

@ -272,9 +272,15 @@ void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) {
LOG_F(9, "CommandPtrLo set to 0x%X", this->cmd_ptr); LOG_F(9, "CommandPtrLo set to 0x%X", this->cmd_ptr);
} }
break; break;
case DMAReg::INT_SELECT:
this->int_select = value & 0xFF00FFUL;
break;
case DMAReg::BRANCH_SELECT: case DMAReg::BRANCH_SELECT:
this->branch_select = value & 0xFF00FFUL; this->branch_select = value & 0xFF00FFUL;
break; break;
case DMAReg::WAIT_SELECT:
this->wait_select = value & 0xFF00FFUL;
break;
default: default:
LOG_F(WARNING, "Unsupported DMA channel register 0x%X", offset); LOG_F(WARNING, "Unsupported DMA channel register 0x%X", offset);
} }

View File

@ -43,6 +43,7 @@ enum DMAReg : uint32_t {
CMD_PTR_LO = 12, CMD_PTR_LO = 12,
INT_SELECT = 16, INT_SELECT = 16,
BRANCH_SELECT = 20, BRANCH_SELECT = 20,
WAIT_SELECT = 24,
}; };
/** Channel Status bits (DBDMA spec, 5.5.3) */ /** Channel Status bits (DBDMA spec, 5.5.3) */
@ -119,6 +120,7 @@ private:
uint8_t* queue_data = 0; uint8_t* queue_data = 0;
uint32_t int_select = 0; uint32_t int_select = 0;
uint32_t branch_select = 0; uint32_t branch_select = 0;
uint32_t wait_select = 0;
bool cmd_in_progress = false; bool cmd_in_progress = false;
uint8_t cur_cmd; uint8_t cur_cmd;