mirror of
https://github.com/dingusdev/dingusppc.git
synced 2025-01-11 05:29:43 +00:00
Rework DBDMA logic for bidirectional channels.
This commit is contained in:
parent
98ccef732f
commit
9f4c248e4c
@ -309,9 +309,11 @@ static PATResult page_address_translation(uint32_t la, bool is_instr_fetch,
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};
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}
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uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size)
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uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size, bool* is_writable)
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{
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if (addr >= last_dma_area.start && (addr + size) <= last_dma_area.end) {
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if (is_writable)
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*is_writable = last_dma_area.type & RT_RAM;
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return last_dma_area.mem_ptr + (addr - last_dma_area.start);
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} else {
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AddressMapEntry* entry = mem_ctrl_instance->find_range(addr);
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@ -319,6 +321,9 @@ uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size)
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last_dma_area.start = entry->start;
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last_dma_area.end = entry->end;
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last_dma_area.mem_ptr = entry->mem_ptr;
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last_dma_area.type = entry->type;
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if (is_writable)
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*is_writable = entry->type & RT_RAM;
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return last_dma_area.mem_ptr + (addr - last_dma_area.start);
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} else {
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ABORT_F("SOS: DMA access to unmapped memory %08X!\n", addr);
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@ -102,7 +102,7 @@ enum TLBFlags : uint16_t {
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extern std::function<void(uint32_t bat_reg)> ibat_update;
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extern std::function<void(uint32_t bat_reg)> dbat_update;
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extern uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size);
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extern uint8_t* mmu_get_dma_mem(uint32_t addr, uint32_t size, bool* is_writable);
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extern void mmu_change_mode(void);
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extern void mmu_pat_ctx_changed();
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -25,6 +25,7 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <devices/common/dbdma.h>
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#include <devices/common/dmacore.h>
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#include <endianswap.h>
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#include <memaccess.h>
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#include <cinttypes>
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#include <cstring>
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@ -36,21 +37,51 @@ void DMAChannel::set_callbacks(DbdmaCallback start_cb, DbdmaCallback stop_cb)
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this->stop_cb = stop_cb;
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}
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void DMAChannel::get_next_cmd(uint32_t cmd_addr, DMACmd* p_cmd) {
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void DMAChannel::fetch_cmd(uint32_t cmd_addr, DMACmd* p_cmd) {
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/* load DMACmd from physical memory */
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memcpy((uint8_t*)p_cmd, mmu_get_dma_mem(cmd_addr, 16), 16);
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memcpy((uint8_t*)p_cmd, mmu_get_dma_mem(cmd_addr, 16, nullptr), 16);
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}
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uint8_t DMAChannel::interpret_cmd() {
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DMACmd cmd_struct;
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bool is_writable;
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int cmd;
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get_next_cmd(this->cmd_ptr, &cmd_struct);
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if (this->cmd_in_progress) {
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// return current command if there is data to transfer
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if (this->queue_len)
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return cmd;
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// obtain real pointer to the descriptor of the completed command
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uint8_t *curr_cmd = mmu_get_dma_mem(this->cmd_ptr - 16, 16, &is_writable);
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// get command code
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cmd = curr_cmd[3] >> 4;
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// all commands except STOP update cmd.xferStatus
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if (cmd < 7 && is_writable) {
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WRITE_WORD_LE_A(&curr_cmd[14], this->ch_stat | CH_STAT_ACTIVE);
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}
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// all INPUT and OUTPUT commands update cmd.resCount
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if (cmd < 4 && is_writable) {
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WRITE_WORD_LE_A(&curr_cmd[12], this->queue_len & 0xFFFFUL);
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}
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this->cmd_in_progress = false;
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}
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fetch_cmd(this->cmd_ptr, &cmd_struct);
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cmd = cmd_struct.cmd_key >> 4;
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this->ch_stat &= ~CH_STAT_WAKE; /* clear wake bit (DMA spec, 5.5.3.4) */
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switch (cmd_struct.cmd_key >> 4) {
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case 0:
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LOG_F(9, "Executing DMA Command OUTPUT_MORE");
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case 0: // OUTPUT_MORE
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case 1: // OUTPUT_LAST
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case 2: // INPUT_MORE
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case 3: // INPUT_LAST
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if (cmd_struct.cmd_key & 7) {
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LOG_F(ERROR, "Key > 0 not implemented");
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break;
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@ -59,35 +90,10 @@ uint8_t DMAChannel::interpret_cmd() {
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LOG_F(ERROR, "non-zero i/b/w not implemented");
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break;
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}
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// this->dma_cb->dma_push(
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// mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count),
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// cmd_struct.req_count);
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this->queue_data = mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count);
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this->queue_data = mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count, &is_writable);
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this->queue_len = cmd_struct.req_count;
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this->cmd_ptr += 16;
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break;
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case 1:
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LOG_F(9, "Executing DMA Command OUTPUT_LAST");
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if (cmd_struct.cmd_key & 7) {
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LOG_F(ERROR, "Key > 0 not implemented");
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break;
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}
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if (cmd_struct.cmd_bits & 0x3F) {
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LOG_F(ERROR, "non-zero i/b/w not implemented");
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break;
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}
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// this->dma_cb->dma_push(
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// mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count),
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// cmd_struct.req_count);
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this->queue_data = mmu_get_dma_mem(cmd_struct.address, cmd_struct.req_count);
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this->queue_len = cmd_struct.req_count;
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this->cmd_ptr += 16;
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break;
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case 2:
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LOG_F(ERROR, "Unsupported DMA Command INPUT_MORE");
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break;
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case 3:
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LOG_F(ERROR, "Unsupported DMA Command INPUT_LAST");
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this->cmd_in_progress = true;
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break;
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case 4:
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LOG_F(ERROR, "Unsupported DMA Command STORE_QUAD");
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@ -96,11 +102,11 @@ uint8_t DMAChannel::interpret_cmd() {
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LOG_F(ERROR, "Unsupported DMA Command LOAD_QUAD");
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break;
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case 6:
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LOG_F(INFO, "Unsupported DMA Command NOP");
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LOG_F(ERROR, "Unsupported DMA Command NOP");
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break;
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case 7:
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LOG_F(INFO, "DMA Command: 7 (STOP)");
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this->ch_stat &= ~CH_STAT_ACTIVE;
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this->cmd_in_progress = false;
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break;
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default:
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LOG_F(ERROR, "Unsupported DMA command 0x%X", cmd_struct.cmd_key >> 4);
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@ -149,7 +155,7 @@ void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) {
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case DMAReg::CH_CTRL:
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mask = value >> 16;
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new_stat = (value & mask & 0xF0FFU) | (old_stat & ~mask);
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LOG_F(INFO, "New ChannelStatus value = 0x%X", new_stat);
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LOG_F(9, "New ChannelStatus value = 0x%X", new_stat);
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if ((new_stat & CH_STAT_RUN) != (old_stat & CH_STAT_RUN)) {
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if (new_stat & CH_STAT_RUN) {
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@ -184,7 +190,7 @@ void DMAChannel::reg_write(uint32_t offset, uint32_t value, int size) {
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case DMAReg::CMD_PTR_LO:
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if (!(this->ch_stat & CH_STAT_RUN) && !(this->ch_stat & CH_STAT_ACTIVE)) {
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this->cmd_ptr = value;
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LOG_F(INFO, "CommandPtrLo set to 0x%X", this->cmd_ptr);
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LOG_F(9, "CommandPtrLo set to 0x%X", this->cmd_ptr);
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}
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break;
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default:
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@ -227,6 +233,33 @@ DmaPullResult DMAChannel::pull_data(uint32_t req_len, uint32_t *avail_len, uint8
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return DmaPullResult::NoMoreData; /* tell the caller there is no more data */
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}
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int DMAChannel::push_data(const char* src_ptr, int len)
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{
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if (this->ch_stat & CH_STAT_DEAD || !(this->ch_stat & CH_STAT_ACTIVE)) {
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LOG_F(WARNING, "DBDMA: attempt to push data to dead/idle channel");
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return -1;
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}
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// interpret DBDMA program until we get buffer to fill in or become idle
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while ((this->ch_stat & CH_STAT_ACTIVE) && !this->queue_len) {
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this->interpret_cmd();
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}
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if (this->queue_len) {
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len = std::min((int)this->queue_len, len);
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std::memcpy(this->queue_data, src_ptr, len);
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this->queue_data += len;
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this->queue_len -= len;
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}
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// proceed with the DBDMA program if the buffer became exhausted
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if (!this->queue_len) {
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this->interpret_cmd();
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}
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return 0;
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}
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bool DMAChannel::is_active()
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{
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if (this->ch_stat & CH_STAT_DEAD || !(this->ch_stat & CH_STAT_ACTIVE)) {
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@ -248,7 +281,8 @@ void DMAChannel::start()
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this->queue_len = 0;
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this->start_cb();
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if (this->start_cb)
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this->start_cb();
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}
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void DMAChannel::resume() {
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@ -266,5 +300,6 @@ void DMAChannel::abort() {
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void DMAChannel::pause() {
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LOG_F(INFO, "Pausing DMA channel");
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this->stop_cb();
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if (this->stop_cb)
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this->stop_cb();
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}
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -42,7 +42,7 @@ enum DMAReg : uint32_t {
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};
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/** Channel Status bits (DBDMA spec, 5.5.3) */
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enum {
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enum : uint16_t {
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CH_STAT_ACTIVE = 0x400,
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CH_STAT_DEAD = 0x800,
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CH_STAT_WAKE = 0x1000,
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@ -53,18 +53,18 @@ enum {
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/** DBDMA command (DBDMA spec, 5.6.1) - all fields are little-endian! */
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typedef struct DMACmd {
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uint16_t req_count;
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uint8_t cmd_bits;
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uint8_t cmd_key;
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uint32_t address;
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uint32_t cmd_arg;
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uint16_t res_count;
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uint16_t xfer_stat;
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uint16_t req_count;
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uint8_t cmd_bits;
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uint8_t cmd_key;
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uint32_t address;
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uint32_t cmd_arg;
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uint16_t res_count;
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uint16_t xfer_stat;
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} DMACmd;
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typedef std::function<void(void)> DbdmaCallback;
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class DMAChannel : public DmaOutChannel {
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class DMAChannel : public DmaBidirChannel {
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public:
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DMAChannel() = default;
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~DMAChannel() = default;
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@ -75,9 +75,10 @@ public:
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bool is_active();
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DmaPullResult pull_data(uint32_t req_len, uint32_t *avail_len, uint8_t **p_data);
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int push_data(const char* src_ptr, int len);
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protected:
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void get_next_cmd(uint32_t cmd_addr, DMACmd* p_cmd);
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void fetch_cmd(uint32_t cmd_addr, DMACmd* p_cmd);
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uint8_t interpret_cmd(void);
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void start(void);
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@ -86,14 +87,15 @@ protected:
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void pause(void);
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private:
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std::function<void(void)> start_cb; // DMA channel start callback
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std::function<void(void)> stop_cb; // DMA channel stop callback
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std::function<void(void)> start_cb = nullptr; // DMA channel start callback
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std::function<void(void)> stop_cb = nullptr; // DMA channel stop callback
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uint16_t ch_stat = 0;
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uint32_t cmd_ptr = 0;
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uint32_t queue_len = 0;
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uint8_t* queue_data = 0;
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uint32_t queue_len;
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uint8_t* queue_data;
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bool cmd_in_progress = false;
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};
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#endif /* DB_DMA_H */
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-21 divingkatae and maximum
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Copyright (C) 2018-22 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -38,13 +38,13 @@ public:
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uint8_t **p_data) = 0;
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};
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// Base class for bidirectional DMA channels.
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class DmaBidirChannel {
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class DmaInChannel {
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public:
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virtual bool is_active() { return true; };
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virtual int push_data(const char* src_ptr, int len) = 0;
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virtual DmaPullResult pull_data(uint32_t req_len, uint32_t *avail_len,
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uint8_t **p_data) = 0;
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};
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// Base class for bidirectional DMA channels.
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class DmaBidirChannel : public DmaOutChannel, public DmaInChannel {
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};
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#endif // DMA_CORE_H
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@ -491,7 +491,7 @@ DmaPullResult AmicSndOutDma::pull_data(uint32_t req_len, uint32_t *avail_len,
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*p_data = mmu_get_dma_mem(
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(this->snd_buf_num ? this->out_buf1 : this->out_buf0) + this->cur_buf_pos,
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len);
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len, nullptr);
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this->cur_buf_pos += len;
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*avail_len = len;
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return DmaPullResult::MoreData;
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@ -524,9 +524,14 @@ void AmicFloppyDma::write_ctrl(uint8_t value)
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int AmicFloppyDma::push_data(const char* src_ptr, int len)
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{
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bool is_writable;
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len = std::min((int)this->byte_count, len);
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uint8_t *p_data = mmu_get_dma_mem(this->addr_ptr, len);
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uint8_t *p_data = mmu_get_dma_mem(this->addr_ptr, len, &is_writable);
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if (!is_writable) {
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ABORT_F("AMIC: attempting DMA write to read-only memory");
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}
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std::memcpy(p_data, src_ptr, len);
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this->addr_ptr += len;
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@ -204,7 +204,7 @@ void PdmOnboardVideo::enable_video_internal()
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LOG_F(INFO, "PDM-Video: framebuffer phys base addr = 0x%X", fb_base_phys);
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// set framebuffer address and pitch
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this->fb_ptr = mmu_get_dma_mem(fb_base_phys, PDM_FB_SIZE_MAX);
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this->fb_ptr = mmu_get_dma_mem(fb_base_phys, PDM_FB_SIZE_MAX, nullptr);
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this->active_width = new_width;
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this->active_height = new_height;
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