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Add BAR 0 to control
BAR 0 exists on a real Power Mac 8600 and the dingusppc 7500.
On a Power Mac 8600, the initial value is 0x84000003. In Open Firmware, you can write to all bits of the BAR and read the value back except the 2 least significant bits are always %11. Bit 0 indicates I/O space. Bit 1 is reserved and should be zero so maybe this is not a real I/O space BAR. 0x8400000 is written to the BAR by Open Firmware. It doesn't look like a normal I/O address which are usually 16 bits.
On the emulated 7500, 0x02000000 is written to the BAR by Open Firmware sometime during probe-all. The BAR did not behave as it does in the Power Mac 8600. This commit fixes that.
Two questions remain:
1) Which fcode writes to the BAR? Is it the probe fcode or is it the control fcode? There's no config-_! in the control fcode.
2) What is the purpose of the BAR? Writing to it can cause a hang. The testbits code below seems to succeed - it restores the original value after reading the result of testing each bit and before displaying the result. The values shown for the MSB (0x84 on the 8600 and 0x02 on the 7500) could be three flag bits.
```
dev vci0
: testbits { adr ; org }
cr
adr config-l@ dup -> org ." original : " 8 u.r cr
20 0 do
1 1f i - << dup 8 u.r ." : "
adr config-l!
adr config-l@
org adr config-l!
8 u.r cr
loop
;
15810 testbits \ 15810 is the address of the BAR on the emulated 7500.
```
This commit is contained in:
joevt
parent
a24840803c
commit
a08e70781a
@ -59,6 +59,7 @@ ControlVideo::ControlVideo()
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this->vendor_id = PCI_VENDOR_APPLE;
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this->device_id = 3;
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this->class_rev = 0;
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this->bars_cfg[0] = 0xFFFFFFFFUL; // I/O region (4 bytes but it's weird because bit 1 is set)
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this->bars_cfg[1] = 0xFFFFF000UL; // base address for the HW registers (4KB)
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this->bars_cfg[2] = 0xFC000000UL; // base address for the VRAM (64MB)
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@ -84,6 +85,10 @@ ControlVideo::ControlVideo()
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void ControlVideo::notify_bar_change(int bar_num)
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{
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switch (bar_num) {
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case 0:
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this->io_base = this->bars[bar_num] & ~3;
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LOG_F(INFO, "Control: I/O space address set to 0x%08X", this->io_base);
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break;
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case 1:
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if (this->regs_base != (this->bars[bar_num] & 0xFFFFFFF0UL)) {
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this->regs_base = this->bars[bar_num] & 0xFFFFFFF0UL;
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@ -116,18 +121,22 @@ uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size)
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}
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}
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switch (offset >> 4) {
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case ControlRegs::TEST:
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result = this->test;
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break;
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case ControlRegs::MON_SENSE:
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result = this->cur_mon_id << 6;
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break;
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default:
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LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset);
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if (rgn_start == this->regs_base) {
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switch (offset >> 4) {
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case ControlRegs::TEST:
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result = this->test;
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break;
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case ControlRegs::MON_SENSE:
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result = this->cur_mon_id << 6;
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break;
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default:
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LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset);
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}
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return BYTESWAP_32(result);
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}
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return BYTESWAP_32(result);
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return 0;
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}
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void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size)
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@ -141,75 +150,77 @@ void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in
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return;
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}
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value = BYTESWAP_32(value);
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if (rgn_start == this->regs_base) {
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value = BYTESWAP_32(value);
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switch (offset >> 4) {
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case ControlRegs::VFPEQ:
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case ControlRegs::VFP:
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case ControlRegs::VAL:
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case ControlRegs::VBP:
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case ControlRegs::VBPEQ:
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case ControlRegs::VSYNC:
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case ControlRegs::VHLINE:
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case ControlRegs::PIPED:
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case ControlRegs::HPIX:
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case ControlRegs::HFP:
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case ControlRegs::HAL:
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case ControlRegs::HBWAY:
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case ControlRegs::HSP:
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case ControlRegs::HEQ:
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case ControlRegs::HLFLN:
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case ControlRegs::HSERR:
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this->swatch_params[(offset >> 4) - 1] = value;
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break;
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case ControlRegs::TEST:
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if (this->test != value) {
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if ((this->test & ~TEST_STROBE) != (value & ~TEST_STROBE)) {
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this->test = value;
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this->test_shift = 0;
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LOG_F(9, "New TEST value: 0x%08X", this->test);
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} else {
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LOG_F(9, "TEST strobe bit flipped, new value: 0x%08X", value);
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this->test = value;
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if (++this->test_shift >= 3) {
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LOG_F(9, "Received TEST reg value: 0x%08X", this->test & ~TEST_STROBE);
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if ((this->test ^ this->prev_test) & 0x400) {
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if (this->test & 0x400) {
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this->disable_display();
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} else {
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this->enable_display();
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switch (offset >> 4) {
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case ControlRegs::VFPEQ:
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case ControlRegs::VFP:
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case ControlRegs::VAL:
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case ControlRegs::VBP:
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case ControlRegs::VBPEQ:
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case ControlRegs::VSYNC:
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case ControlRegs::VHLINE:
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case ControlRegs::PIPED:
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case ControlRegs::HPIX:
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case ControlRegs::HFP:
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case ControlRegs::HAL:
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case ControlRegs::HBWAY:
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case ControlRegs::HSP:
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case ControlRegs::HEQ:
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case ControlRegs::HLFLN:
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case ControlRegs::HSERR:
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this->swatch_params[(offset >> 4) - 1] = value;
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break;
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case ControlRegs::TEST:
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if (this->test != value) {
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if ((this->test & ~TEST_STROBE) != (value & ~TEST_STROBE)) {
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this->test = value;
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this->test_shift = 0;
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LOG_F(9, "New TEST value: 0x%08X", this->test);
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} else {
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LOG_F(9, "TEST strobe bit flipped, new value: 0x%08X", value);
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this->test = value;
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if (++this->test_shift >= 3) {
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LOG_F(9, "Received TEST reg value: 0x%08X", this->test & ~TEST_STROBE);
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if ((this->test ^ this->prev_test) & 0x400) {
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if (this->test & 0x400) {
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this->disable_display();
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} else {
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this->enable_display();
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}
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this->prev_test = this->test;
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}
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this->prev_test = this->test;
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}
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}
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}
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break;
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case ControlRegs::GBASE:
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this->fb_base = value;
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break;
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case ControlRegs::ROW_WORDS:
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this->row_words = value;
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break;
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case ControlRegs::MON_SENSE:
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LOG_F(9, "Control: monitor sense written with 0x%X", value);
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value = (value >> 3) & 7;
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this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
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break;
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case ControlRegs::ENABLE:
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this->flags = value;
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break;
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case ControlRegs::GSC_DIVIDE:
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this->clock_divider = value;
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break;
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case ControlRegs::REFRESH_COUNT:
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LOG_F(INFO, "Control: refresh count set to 0x%08X", value);
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break;
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case ControlRegs::INT_ENABLE:
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this->int_enable = value;
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break;
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default:
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LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset);
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}
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break;
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case ControlRegs::GBASE:
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this->fb_base = value;
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break;
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case ControlRegs::ROW_WORDS:
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this->row_words = value;
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break;
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case ControlRegs::MON_SENSE:
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LOG_F(9, "Control: monitor sense written with 0x%X", value);
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value = (value >> 3) & 7;
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this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7);
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break;
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case ControlRegs::ENABLE:
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this->flags = value;
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break;
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case ControlRegs::GSC_DIVIDE:
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this->clock_divider = value;
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break;
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case ControlRegs::REFRESH_COUNT:
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LOG_F(INFO, "Control: refresh count set to 0x%08X", value);
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break;
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case ControlRegs::INT_ENABLE:
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this->int_enable = value;
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break;
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default:
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LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset);
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}
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}
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@ -117,6 +117,7 @@ private:
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std::unique_ptr<uint8_t[]> vram_ptr;
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uint32_t vram_size;
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uint32_t io_base = 0;
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uint32_t vram_base = 0;
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uint32_t regs_base = 0;
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uint32_t prev_test = 0x433;
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