From a5ef814ec464b349c11f60ccf4cfa743963441b1 Mon Sep 17 00:00:00 2001
From: Maxim Poliakovski <maximumspatium@googlemail.com>
Date: Fri, 5 Feb 2021 01:10:56 +0100
Subject: [PATCH] atirage: add reading and writing of PLL registers.

---
 devices/atirage.cpp | 16 ++++++++++++++++
 devices/atirage.h   |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/devices/atirage.cpp b/devices/atirage.cpp
index 30c0ecc..f9464f3 100644
--- a/devices/atirage.cpp
+++ b/devices/atirage.cpp
@@ -124,6 +124,13 @@ uint32_t ATIRage::read_reg(uint32_t offset, uint32_t size) {
     switch (offset & ~3) {
     case ATI_GP_IO:
         break;
+    case ATI_CLOCK_CNTL:
+        if (offset == ATI_CLOCK_CNTL+2 && size == 1 &&
+            !(this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) {
+            int pll_addr = this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2;
+            return this->plls[pll_addr & 0xF];
+        }
+        break;
     case ATI_DAC_REGS:
         if (offset == ATI_DAC_DATA) {
             this->block_io_regs[ATI_DAC_DATA] =
@@ -168,6 +175,15 @@ void ATIRage::write_reg(uint32_t offset, uint32_t value, uint32_t size) {
                 this->disp_id->read_monitor_sense(gpio_val, gpio_dir));
         }
         break;
+    case ATI_CLOCK_CNTL:
+        if (offset == ATI_CLOCK_CNTL+2 && size == 1 &&
+            (this->block_io_regs[ATI_CLOCK_CNTL+1] & 0x2)) {
+            int pll_addr = this->block_io_regs[ATI_CLOCK_CNTL+1] >> 2;
+            uint8_t pll_data = this->block_io_regs[ATI_CLOCK_CNTL+2];
+            this->plls[pll_addr & 0xF] = pll_data;
+            LOG_F(INFO, "ATI Rage: PLL #%d set to 0x%02X", pll_addr, pll_data);
+        }
+        break;
     case ATI_DAC_REGS:
         switch (offset) {
         /* writing to read/write index registers resets color component index */
diff --git a/devices/atirage.h b/devices/atirage.h
index 7f201bc..6bb5618 100644
--- a/devices/atirage.h
+++ b/devices/atirage.h
@@ -217,6 +217,8 @@ private:
 
     uint8_t pci_cfg[256] = {0}; /* PCI configuration space */
 
+    uint8_t plls[16] = {0}; // internal PLL registers
+
     /* Video RAM variables */
     uint32_t    vram_size;
     uint8_t*    vram_ptr;