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https://github.com/dingusdev/dingusppc.git
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Refactor ATI Mach64 GX emulation.
This commit is contained in:
Maxim Poliakovski
parent
616d0728fd
commit
b07b700b36
@ -21,9 +21,10 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
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/** ATI Mach64 GX emulation.
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It emulates an ATI88800GX controller with an IBM RGB514 style RAMDAC.
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Emulation is limited to a basic framebuffer for now.
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Emulation is limited to a basic frame buffer for now.
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*/
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#include <core/bitops.h>
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#include <core/timermanager.h>
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#include <devices/deviceregistry.h>
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#include <devices/video/atimach64defs.h>
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@ -63,6 +64,9 @@ AtiMach64Gx::AtiMach64Gx()
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// allocate video RAM
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this->vram_size = 2 << 20;
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this->vram_ptr = std::unique_ptr<uint8_t[]> (new uint8_t[this->vram_size]);
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// set up RAMDAC identification
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this->regs[ATI_CONFIG_STAT0 >> 2] = 1 << 9;
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}
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void AtiMach64Gx::notify_bar_change(int bar_num)
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@ -104,7 +108,7 @@ static const uint32_t io_idx_to_reg_offset[32] = {
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ATI_DAC_CNTL, ATI_GEN_TEST_CNTL,
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ATI_CONFIG_CNTL, ATI_CONFIG_CHIP_ID,
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ATI_CONFIG_STAT0, ATI_GX_CONFIG_STAT1,
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ATI_INVALID, ATI_INVALID
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ATI_INVALID, ATI_CRTC_H_TOTAL_DISP
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};
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bool AtiMach64Gx::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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@ -123,7 +127,7 @@ bool AtiMach64Gx::pci_io_read(uint32_t offset, uint32_t size, uint32_t* res)
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if ((offset & ~3) == ATI_CONFIG_CNTL) {
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*res = read_mem(((uint8_t *)&this->config_cntl) + (offset & 3), size);
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} else {
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*res = this->read_reg(offset, size);
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*res = BYTESWAP_SIZED(this->read_reg(offset, size), size);
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}
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return true;
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@ -144,77 +148,102 @@ bool AtiMach64Gx::pci_io_write(uint32_t offset, uint32_t value, uint32_t size)
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write_mem(((uint8_t *)&this->config_cntl) + (offset & 3), value, size);
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switch (this->config_cntl & 3) {
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case 0:
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LOG_F(WARNING, "AtiMach64Gx: linear aperture disabled!");
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LOG_F(WARNING, "%s: linear aperture disabled!", this->name.c_str());
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break;
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case 1:
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LOG_F(INFO, "AtiMach64Gx: aperture size set to 4MB");
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LOG_F(INFO, "%s: aperture size set to 4MB", this->name.c_str());
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this->mm_regs_offset = MM_REGS_2_OFF;
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break;
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case 2:
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LOG_F(INFO, "AtiMach64Gx: aperture size set to 8MB");
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LOG_F(INFO, "%s: aperture size set to 8MB", this->name.c_str());
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this->mm_regs_offset = MM_REGS_0_OFF;
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break;
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default:
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LOG_F(ERROR, "AtiMach64Gx: invalid aperture size in CONFIG_CNTL");
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LOG_F(ERROR, "%s: invalid aperture size in CONFIG_CNTL", this->name.c_str());
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}
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} else {
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this->write_reg(offset, value, size);
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this->write_reg(offset, BYTESWAP_SIZED(value, size), size);
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}
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return true;
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}
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uint32_t AtiMach64Gx::read_reg(uint32_t offset, uint32_t size)
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uint32_t AtiMach64Gx::read_reg(uint32_t reg_offset, uint32_t size)
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{
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LOG_F(INFO, "AtiMach64Gx: read from I/O mapped reg at 0x%X", offset);
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uint32_t offset = reg_offset & 3;
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return read_mem(&this->mm_regs[offset], size);
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uint64_t result = this->regs[reg_offset >> 2];
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if (!offset && size == 4) { // fast path
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return result;
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} else { // slow path
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if ((offset + size) > 4) {
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result |= (uint64_t)(this->regs[(reg_offset >> 2) + 1]) << 32;
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}
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return extract_bits<uint64_t>(result, offset * 8, size * 8);
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}
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}
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void AtiMach64Gx::write_reg(uint32_t offset, uint32_t value, uint32_t size)
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void AtiMach64Gx::write_reg(uint32_t reg_offset, uint32_t value, uint32_t size)
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{
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uint8_t gpio_dirs, gpio_levels;
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int crtc_en;
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// write value to internal registers with endian conversion
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write_mem(&this->mm_regs[offset], value, size);
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uint32_t offset = reg_offset & 3;
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switch (offset & ~3) {
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if (offset || size != 4) { // slow path
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if ((offset + size) > 4) {
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ABORT_F("%s: unaligned DWORD writes not implemented", this->name.c_str());
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}
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uint64_t old_val = this->regs[reg_offset >> 2];
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insert_bits<uint64_t>(old_val, value, offset * 8, size * 8);
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value = old_val;
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}
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switch (reg_offset & ~3) {
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case ATI_CRTC_OFF_PITCH:
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this->regs[reg_offset >> 2] = value;
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this->fb_pitch = extract_bits<uint32_t>(value, 22, 10) * 8;
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this->fb_ptr = &this->vram_ptr[extract_bits<uint32_t>(value, 0, 20) * 8];
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break;
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case ATI_CRTC_GEN_CNTL:
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if (value & 0x40) {
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this->mm_regs[ATI_CRTC_GEN_CNTL] |= (1 << 6);
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this->blank_on = true;
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this->blank_display();
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} else {
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this->mm_regs[ATI_CRTC_GEN_CNTL] &= ~(1 << 6);
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this->blank_on = false;
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if (bit_changed(this->regs[reg_offset >> 2], value, 6)) {
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if (value & 0x40) {
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this->blank_on = true;
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this->blank_display();
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} else {
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this->blank_on = false;
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}
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}
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crtc_en = (this->mm_regs[ATI_CRTC_GEN_CNTL+3] >> 1) & 1;
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if (crtc_en != this->crtc_enable) {
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if (!crtc_en) {
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if (bit_changed(this->regs[reg_offset >> 2], value, 25)) {
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if (!bit_set(value, 25)) {
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this->disable_crtc_internal();
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} else {
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this->blank_on = false;
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}
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}
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break;
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case ATI_DAC_REGS:
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if (size == 1) { // only byte accesses are allowed for DAC registers
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int dac_reg_addr = ((this->mm_regs[ATI_DAC_CNTL] & 1) << 2) | (offset & 3);
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rgb514_write_reg(dac_reg_addr, value);
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int dac_reg_addr = ((this->regs[ATI_DAC_CNTL >> 2] & 1) << 2) | offset;
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rgb514_write_reg(dac_reg_addr, extract_bits<uint32_t>(value, offset * 8, 8));
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}
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break;
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case ATI_DAC_CNTL:
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// monitor ID is usually accessed using 8bit writes
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if ((offset & 3) == 3) {
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gpio_dirs = (value >> 3) & 7;
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gpio_levels = value & 7;
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if (offset == 3) {
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gpio_dirs = extract_bits<uint32_t>(value, 27, 3);
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gpio_levels = extract_bits<uint32_t>(value, 24, 3);
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gpio_levels = this->disp_id->read_monitor_sense(gpio_levels, gpio_dirs);
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this->mm_regs[ATI_DAC_CNTL+3] = (this->mm_regs[ATI_DAC_CNTL+3] & 0xF8U) | gpio_levels;
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insert_bits<uint32_t>(value, gpio_levels, 24, 3);
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}
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break;
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default:
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LOG_F(INFO, "AtiMach64Gx: write 0x%X to I/O mapped reg at 0x%X", value, offset);
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case ATI_CONFIG_STAT0:
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return; // prevent writes to this read-only register
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}
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this->regs[reg_offset >> 2] = value;
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}
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uint32_t AtiMach64Gx::read(uint32_t rgn_start, uint32_t offset, int size)
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@ -223,7 +252,7 @@ uint32_t AtiMach64Gx::read(uint32_t rgn_start, uint32_t offset, int size)
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if (offset < this->vram_size) {
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return read_mem(&this->vram_ptr[offset], size);
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} else if (offset >= this->mm_regs_offset) {
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return read_reg(offset - this->mm_regs_offset, size);
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return BYTESWAP_SIZED(read_reg(offset - this->mm_regs_offset, size), size);
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}
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}
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@ -241,33 +270,31 @@ void AtiMach64Gx::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int
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if (offset < this->vram_size) {
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write_mem(&this->vram_ptr[offset], value, size);
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} else if (offset >= this->mm_regs_offset) {
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write_reg(offset - this->mm_regs_offset, value, size);
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write_reg(offset - this->mm_regs_offset, BYTESWAP_SIZED(value, size), size);
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}
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}
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}
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void AtiMach64Gx::enable_crtc_internal()
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{
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int new_width = (this->mm_regs[ATI_CRTC_H_TOTAL_DISP+2] + 1) * 8;
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uint32_t new_width, new_height;
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int new_height = (READ_WORD_LE_A(&this->mm_regs[ATI_CRTC_V_TOTAL_DISP+2]) & 0x7FFUL) + 1;
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// check for unsupported modes and fail early
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if (!bit_set(this->regs[ATI_CRTC_GEN_CNTL >> 2], 24))
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ABORT_F("%s: VGA not supported", this->name.c_str());
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new_width = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP >> 2], 16, 8) + 1) * 8;
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new_height = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP >> 2], 16, 11) + 1;
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if (new_width != this->active_width || new_height != this->active_height) {
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LOG_F(WARNING, "AtiMach64Gx: display window resizing not implemented yet!");
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this->create_display_window(new_width, new_height);
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}
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// calculate display refresh rate
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int hori_total = (this->mm_regs[ATI_CRTC_H_TOTAL_DISP] + 1) * 8;
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this->hori_total = (extract_bits<uint32_t>(this->regs[ATI_CRTC_H_TOTAL_DISP >> 2], 0, 9) + 1) * 8;
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this->vert_total = extract_bits<uint32_t>(this->regs[ATI_CRTC_V_TOTAL_DISP >> 2], 0, 11) + 1;
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int vert_total = (READ_WORD_LE_A(&this->mm_regs[ATI_CRTC_V_TOTAL_DISP]) & 0x7FFUL) + 1;
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this->refresh_rate = this->pixel_clock / hori_total / vert_total;
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int32_t src_offset = (READ_DWORD_LE_A(&this->mm_regs[ATI_CRTC_OFF_PITCH]) & 0xFFFFFU) * 8;
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this->fb_pitch = ((READ_DWORD_LE_A(&this->mm_regs[ATI_CRTC_OFF_PITCH])) >> 19) & 0x1FF8U;
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this->fb_ptr = &this->vram_ptr[src_offset];
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this->refresh_rate = this->pixel_clock / this->hori_total / this->vert_total;
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// specify framebuffer converter
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switch (this->pixel_depth) {
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@ -277,7 +304,7 @@ void AtiMach64Gx::enable_crtc_internal()
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};
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break;
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default:
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ABORT_F("AtiMach64Gx: unsupported pixel depth %d", this->pixel_depth);
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ABORT_F("%s: unsupported pixel depth %d", this->name.c_str(), this->pixel_depth);
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}
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if (this->refresh_task_id) {
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@ -299,6 +326,8 @@ void AtiMach64Gx::enable_crtc_internal()
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void AtiMach64Gx::disable_crtc_internal()
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{
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this->blank_on = true;
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this->blank_display();
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this->crtc_enable = 0;
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}
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@ -333,14 +362,12 @@ void AtiMach64Gx::rgb514_write_reg(uint8_t reg_addr, uint8_t value)
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this->rgb514_write_ind_reg((this->dac_idx_hi << 8) + this->dac_idx_lo, value);
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break;
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default:
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LOG_F(WARNING, "RGB514: access to unimplemented register at 0x%X", reg_addr);
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ABORT_F("RGB514: access to unimplemented register at 0x%X", reg_addr);
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}
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}
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void AtiMach64Gx::rgb514_write_ind_reg(uint8_t reg_addr, uint8_t value)
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{
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LOG_F(INFO, "RGB514: write 0x%X to register 0x%X", value, reg_addr);
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this->dac_regs[reg_addr] = value;
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switch (reg_addr) {
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-22 divingkatae and maximum
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Copyright (C) 2018-23 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -41,23 +41,23 @@ public:
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return std::unique_ptr<AtiMach64Gx>(new AtiMach64Gx());
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}
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/* PCI device methods */
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// PCI device methods
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bool supports_io_space(void) {
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return true;
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};
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/* I/O space access methods */
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// I/O space access methods
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bool pci_io_read(uint32_t offset, uint32_t size, uint32_t* res);
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bool pci_io_write(uint32_t offset, uint32_t value, uint32_t size);
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/* MMIODevice methods */
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// MMIODevice methods
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uint32_t read(uint32_t rgn_start, uint32_t offset, int size);
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void write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size);
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protected:
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void notify_bar_change(int bar_num);
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uint32_t read_reg(uint32_t offset, uint32_t size);
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void write_reg(uint32_t offset, uint32_t value, uint32_t size);
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uint32_t read_reg(uint32_t reg_offset, uint32_t size);
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void write_reg(uint32_t reg_offset, uint32_t value, uint32_t size);
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void enable_crtc_internal();
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void disable_crtc_internal();
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@ -65,7 +65,7 @@ protected:
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void rgb514_write_ind_reg(uint8_t reg_addr, uint8_t value);
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private:
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uint8_t mm_regs[2048] = { 0 }; // internal registers
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uint32_t regs[256] = {}; // internal registers
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int vram_size;
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uint32_t aperture_base;
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@ -85,4 +85,4 @@ private:
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std::unique_ptr<uint8_t[]> vram_ptr;
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};
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#endif /* ATI_MACH64_GX_H */
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#endif // ATI_MACH64_GX_H
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