ppcopcodes: cosmetic improvements.
This commit is contained in:
Maxim Poliakovski
parent
2b6f41e0d0
commit
b5b14b2f9d
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@ -1,6 +1,6 @@
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/*
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DingusPPC - The Experimental PowerPC Macintosh emulator
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Copyright (C) 2018-23 divingkatae and maximum
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Copyright (C) 2018-24 divingkatae and maximum
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(theweirdo) spatium
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(Contact divingkatae#1017 or powermax#2286 on Discord for more info)
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@ -676,11 +676,12 @@ static inline uint32_t rot_mask(unsigned rot_mb, unsigned rot_me) {
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void dppc_interpreter::ppc_rlwimi() {
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ppc_grab_regssa(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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uint32_t mask = rot_mask(rot_mb, rot_me);
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uint32_t r = rot_sh ? ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh))) : ppc_result_d;
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uint32_t r = rot_sh ? ((ppc_result_d << rot_sh) |
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(ppc_result_d >> (32 - rot_sh))) : ppc_result_d;
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ppc_result_a = (ppc_result_a & ~mask) | (r & mask);
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if ((ppc_cur_instruction & 0x01) == 1) {
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ppc_changecrf0(ppc_result_a);
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@ -690,11 +691,12 @@ void dppc_interpreter::ppc_rlwimi() {
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void dppc_interpreter::ppc_rlwinm() {
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ppc_grab_regssa(ppc_cur_instruction);
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 31;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
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unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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uint32_t mask = rot_mask(rot_mb, rot_me);
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uint32_t r = rot_sh ? ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh))) : ppc_result_d;
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uint32_t r = rot_sh ? ((ppc_result_d << rot_sh) |
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(ppc_result_d >> (32 - rot_sh))) : ppc_result_d;
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ppc_result_a = r & mask;
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if ((ppc_cur_instruction & 0x01) == 1) {
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ppc_changecrf0(ppc_result_a);
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@ -704,12 +706,13 @@ void dppc_interpreter::ppc_rlwinm() {
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void dppc_interpreter::ppc_rlwnm() {
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ppc_grab_regssab(ppc_cur_instruction);
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ppc_result_b &= 31;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 31;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 31;
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ppc_result_b &= 0x1F;
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unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
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unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
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uint32_t mask = rot_mask(rot_mb, rot_me);
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uint32_t rot = ppc_result_b & 0x1F;
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uint32_t r = rot ? ((ppc_result_d << rot) | (ppc_result_d >> (32 - rot))) : ppc_result_d;
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uint32_t r = rot ? ((ppc_result_d << rot) |
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(ppc_result_d >> (32 - rot))) : ppc_result_d;
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ppc_result_a = r & mask;
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if ((ppc_cur_instruction & 0x01) == 1) {
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ppc_changecrf0(ppc_result_a);
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@ -718,7 +721,7 @@ void dppc_interpreter::ppc_rlwnm() {
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}
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void dppc_interpreter::ppc_mfcr() {
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int reg_d = (ppc_cur_instruction >> 21) & 31;
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int reg_d = (ppc_cur_instruction >> 21) & 0x1F;
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ppc_state.gpr[reg_d] = ppc_state.cr;
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}
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@ -729,8 +732,8 @@ void dppc_interpreter::ppc_mtsr() {
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if (ppc_state.msr & MSR::PR) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
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}
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int reg_s = (ppc_cur_instruction >> 21) & 31;
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uint32_t grab_sr = (ppc_cur_instruction >> 16) & 15;
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int reg_s = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t grab_sr = (ppc_cur_instruction >> 16) & 0x0F;
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ppc_state.sr[grab_sr] = ppc_state.gpr[reg_s];
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mmu_pat_ctx_changed();
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}
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@ -755,8 +758,8 @@ void dppc_interpreter::ppc_mfsr() {
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if (ppc_state.msr & MSR::PR) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
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}
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int reg_d = (ppc_cur_instruction >> 21) & 31;
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uint32_t grab_sr = (ppc_cur_instruction >> 16) & 15;
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int reg_d = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t grab_sr = (ppc_cur_instruction >> 16) & 0x0F;
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ppc_state.gpr[reg_d] = ppc_state.sr[grab_sr];
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}
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@ -779,7 +782,7 @@ void dppc_interpreter::ppc_mfmsr() {
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if (ppc_state.msr & MSR::PR) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
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}
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uint32_t reg_d = (ppc_cur_instruction >> 21) & 31;
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uint32_t reg_d = (ppc_cur_instruction >> 21) & 0x1F;
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ppc_state.gpr[reg_d] = ppc_state.msr;
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}
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@ -790,7 +793,7 @@ void dppc_interpreter::ppc_mtmsr() {
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if (ppc_state.msr & MSR::PR) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::NOT_ALLOWED);
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}
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uint32_t reg_s = (ppc_cur_instruction >> 21) & 31;
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uint32_t reg_s = (ppc_cur_instruction >> 21) & 0x1F;
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ppc_state.msr = ppc_state.gpr[reg_s];
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// generate External Interrupt Exception
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@ -888,7 +891,8 @@ static void update_decrementer(uint32_t val) {
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}
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void dppc_interpreter::ppc_mfspr() {
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 0x1F) << 5) |
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((ppc_cur_instruction >> 16) & 0x1F);
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#ifdef CPU_PROFILING
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if (ref_spr > 31) {
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@ -910,11 +914,12 @@ void dppc_interpreter::ppc_mfspr() {
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break;
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}
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ppc_state.gpr[(ppc_cur_instruction >> 21) & 31] = ppc_state.spr[ref_spr];
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ppc_state.gpr[(ppc_cur_instruction >> 21) & 0x1F] = ppc_state.spr[ref_spr];
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}
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void dppc_interpreter::ppc_mtspr() {
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 0x1F) << 5) |
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((ppc_cur_instruction >> 16) & 0x1F);
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#ifdef CPU_PROFILING
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if (ref_spr > 31) {
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@ -926,7 +931,7 @@ void dppc_interpreter::ppc_mtspr() {
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return;
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}
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uint32_t val = ppc_state.gpr[(ppc_cur_instruction >> 21) & 31];
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uint32_t val = ppc_state.gpr[(ppc_cur_instruction >> 21) & 0x1F];
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ppc_state.spr[ref_spr] = val;
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switch (ref_spr) {
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@ -976,8 +981,9 @@ void dppc_interpreter::ppc_mtspr() {
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}
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void dppc_interpreter::ppc_mftb() {
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 31) << 5) | ((ppc_cur_instruction >> 16) & 31);
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int reg_d = (ppc_cur_instruction >> 21) & 31;
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uint32_t ref_spr = (((ppc_cur_instruction >> 11) & 0x1F) << 5) |
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((ppc_cur_instruction >> 16) & 0x1F);
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int reg_d = (ppc_cur_instruction >> 21) & 0x1F;
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uint64_t tbr_value = calc_tbr_value();
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@ -1041,7 +1047,7 @@ template void dppc_interpreter::ppc_exts<int16_t, RC1>();
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template <field_lk l, field_aa a>
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void dppc_interpreter::ppc_b() {
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int32_t adr_li = int32_t((ppc_cur_instruction & ~3UL) << 6) >> 6;
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int32_t adr_li = int32_t((ppc_cur_instruction & ~3UL) << 6) >> 6;
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if (a)
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ppc_next_instruction_address = adr_li;
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@ -1063,8 +1069,8 @@ template <field_lk l, field_aa a>
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void dppc_interpreter::ppc_bc() {
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uint32_t ctr_ok;
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uint32_t cnd_ok;
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 31;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 31;
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 0x1F;
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int32_t br_bd = int32_t(int16_t(ppc_cur_instruction & ~3UL));
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if (!(br_bo & 0x04)) {
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@ -1094,8 +1100,8 @@ template<field_lk l, field_601 for601>
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void dppc_interpreter::ppc_bcctr() {
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uint32_t ctr_ok;
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uint32_t cnd_ok;
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 31;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 31;
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 0x1F;
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uint32_t ctr = ppc_state.spr[SPR::CTR];
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uint32_t new_ctr;
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@ -1127,8 +1133,8 @@ template void dppc_interpreter::ppc_bcctr<LK1, IS601>();
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template <field_lk l>
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void dppc_interpreter::ppc_bclr() {
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 31;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 31;
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uint32_t br_bo = (ppc_cur_instruction >> 21) & 0x1F;
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uint32_t br_bi = (ppc_cur_instruction >> 16) & 0x1F;
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uint32_t ctr_ok;
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uint32_t cnd_ok;
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@ -1309,9 +1315,9 @@ void dppc_interpreter::ppc_rfi() {
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#ifdef CPU_PROFILING
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num_supervisor_instrs++;
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#endif
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uint32_t new_srr1_val = (ppc_state.spr[SPR::SRR1] & 0x87C0FF73UL);
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uint32_t new_msr_val = (ppc_state.msr & ~(0x87C0FF73UL));
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ppc_state.msr = (new_msr_val | new_srr1_val) & 0xFFFBFFFFUL;
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uint32_t new_srr1_val = (ppc_state.spr[SPR::SRR1] & 0x87C0FF73UL);
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uint32_t new_msr_val = (ppc_state.msr & ~0x87C0FF73UL);
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ppc_state.msr = (new_msr_val | new_srr1_val) & 0xFFFBFFFFUL;
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// generate External Interrupt Exception
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// if CPU interrupt line is still asserted
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@ -1347,9 +1353,9 @@ void dppc_interpreter::ppc_sc() {
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}
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void dppc_interpreter::ppc_tw() {
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uint32_t reg_a = (ppc_cur_instruction >> 11) & 31;
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uint32_t reg_b = (ppc_cur_instruction >> 16) & 31;
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uint32_t ppc_to = (ppc_cur_instruction >> 21) & 31;
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uint32_t reg_a = (ppc_cur_instruction >> 11) & 0x1F;
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uint32_t reg_b = (ppc_cur_instruction >> 16) & 0x1F;
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uint32_t ppc_to = (ppc_cur_instruction >> 21) & 0x1F;
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if (((int32_t(ppc_state.gpr[reg_a]) < int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x10)) ||
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((int32_t(ppc_state.gpr[reg_a]) > int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x08)) ||
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((int32_t(ppc_state.gpr[reg_a]) == int32_t(ppc_state.gpr[reg_b])) && (ppc_to & 0x04)) ||
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@ -1785,7 +1791,7 @@ void dppc_interpreter::ppc_lswx() {
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for (;;) {
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if (is_601 && (reg_d == reg_b || (reg_a != 0 && reg_d == reg_a))) {
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// UNTESTED! MPC601 manual is inconsistant on whether reg_b is skipped or not
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reg_d = (reg_d + 1) & 31; // wrap around through GPR0
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reg_d = (reg_d + 1) & 0x1F; // wrap around through GPR0
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}
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switch (grab_inb) {
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case 0:
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@ -1802,7 +1808,7 @@ void dppc_interpreter::ppc_lswx() {
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return;
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}
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ppc_state.gpr[reg_d] = mmu_read_vmem<uint32_t>(ppc_effective_address);
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reg_d = (reg_d + 1) & 31; // wrap around through GPR0
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reg_d = (reg_d + 1) & 0x1F; // wrap around through GPR0
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ppc_effective_address += 4;
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grab_inb -= 4;
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}
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@ -1924,7 +1930,7 @@ void dppc_interpreter::ppc_tlbie() {
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num_supervisor_instrs++;
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#endif
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tlb_flush_entry(ppc_state.gpr[(ppc_cur_instruction >> 11) & 31]);
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tlb_flush_entry(ppc_state.gpr[(ppc_cur_instruction >> 11) & 0x1F]);
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}
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void dppc_interpreter::ppc_tlbia() {
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