ppcfpopcodes: fix mtfsf emulation.
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8595dd7d99
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c25b027de4
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@ -873,19 +873,29 @@ void dppc_interpreter::ppc_mffs() {
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}
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void dppc_interpreter::ppc_mtfsf() {
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int reg_b = (ppc_cur_instruction >> 11) & 0x1F;
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uint8_t fm = (ppc_cur_instruction >> 17) & 0xFF;
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uint32_t cr_mask = 0;
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reg_b = (ppc_cur_instruction >> 11) & 31;
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crm = (ppc_cur_instruction >> 17) & 255;
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cr_mask = ((crm & 1) == 1) ? 0xF0000000 : 0x00000000;
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cr_mask += (((crm >> 1) & 1) == 1) ? 0x0F000000 : 0x00000000;
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cr_mask += (((crm >> 2) & 1) == 1) ? 0x00F00000 : 0x00000000;
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cr_mask += (((crm >> 3) & 1) == 1) ? 0x000F0000 : 0x00000000;
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cr_mask += (((crm >> 4) & 1) == 1) ? 0x0000F000 : 0x00000000;
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cr_mask += (((crm >> 5) & 1) == 1) ? 0x00000F00 : 0x00000000;
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cr_mask += (((crm >> 6) & 1) == 1) ? 0x000000F0 : 0x00000000;
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cr_mask += (((crm >> 7) & 1) == 1) ? 0x0000000F : 0x00000000;
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uint32_t quickfprval = (uint32_t)(ppc_state.fpr[reg_b].int64_r & 0xFFFFFFFF);
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ppc_state.fpscr = (ppc_state.fpscr & ~cr_mask) | (quickfprval & cr_mask);
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if (fm == 0xFFU) // the fast case
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cr_mask = 0xFFFFFFFFUL;
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else { // the slow case
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if (fm & 0x80) cr_mask |= 0xF0000000UL;
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if (fm & 0x40) cr_mask |= 0x0F000000UL;
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if (fm & 0x20) cr_mask |= 0x00F00000UL;
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if (fm & 0x10) cr_mask |= 0x000F0000UL;
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if (fm & 0x08) cr_mask |= 0x0000F000UL;
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if (fm & 0x04) cr_mask |= 0x00000F00UL;
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if (fm & 0x02) cr_mask |= 0x000000F0UL;
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if (fm & 0x01) cr_mask |= 0x0000000FUL;
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}
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// ensure neither FEX nor VX will be changed
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cr_mask &= ~(FPSCR::FEX | FPSCR::VX);
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// copy FPR[reg_b] to FPSCR under control of cr_mask
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ppc_state.fpscr = (ppc_state.fpscr & ~cr_mask) | (ppc_state.fpr[reg_b].int64_r & cr_mask);
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if (rc_flag)
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ppc_update_cr1();
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