Macintosh-Tools
/
dingusppc
mirror of https://github.com/dingusdev/dingusppc.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cpu: Add ppc_grab_regssash macro. 

This macro is like ppc_grab_regssa but includes rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
This commit is contained in:
joevt 2024-04-08 21:26:14 -07:00 committed by dingusdev
parent 4f45d7de35
commit cb05bd05eb
3 changed files with 19 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
cpu/ppc/poweropcodes.cpp
View File

@ -372,8 +372,7 @@ template void dppc_interpreter::power_sleq<RC1>();
template <field_rc rec>
void dppc_interpreter::power_sliq() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
ppc_result_a = ppc_result_d << rot_sh;
ppc_state.spr[SPR::MQ] = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
@ -389,8 +388,7 @@ template void dppc_interpreter::power_sliq<RC1>();
template <field_rc rec>
void dppc_interpreter::power_slliq() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
uint32_t r = ((ppc_result_d << rot_sh) | (ppc_result_d >> (32 - rot_sh)));
uint32_t mask = power_rot_mask(0, 31 - rot_sh);
@ -451,8 +449,7 @@ template void dppc_interpreter::power_slq<RC1>();
template <field_rc rec>
void dppc_interpreter::power_sraiq() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
uint32_t mask = (1 << rot_sh) - 1;
ppc_result_a = (int32_t)ppc_result_d >> rot_sh;
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
@ -557,8 +554,7 @@ template void dppc_interpreter::power_sreq<RC1>();
template <field_rc rec>
void dppc_interpreter::power_sriq() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
ppc_result_a = ppc_result_d >> rot_sh;
ppc_state.spr[SPR::MQ] = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
@ -573,8 +569,7 @@ template void dppc_interpreter::power_sriq<RC1>();
template <field_rc rec>
void dppc_interpreter::power_srliq() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
uint32_t r = (ppc_result_d >> rot_sh) | (ppc_result_d << (32 - rot_sh));
unsigned mask = power_rot_mask(rot_sh, 31);

8
cpu/ppc/ppcmacros.h
View File

@ -74,6 +74,12 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
uint32_t ppc_result_d = ppc_state.gpr[reg_s]; \
uint32_t ppc_result_a = ppc_state.gpr[reg_a];
#define ppc_grab_regssash(opcode) \
uint32_t reg_s = (opcode >> 21) & 31; \
uint32_t reg_a = (opcode >> 16) & 31; \
uint32_t rot_sh = (opcode >> 11) & 31; \
uint32_t ppc_result_d = ppc_state.gpr[reg_s]; \
uint32_t ppc_result_a = ppc_state.gpr[reg_a];
#define ppc_grab_regssb(opcode) \
uint32_t reg_s = (opcode >> 21) & 31; \
@ -169,4 +175,4 @@ along with this program. If not, see <https://www.gnu.org/licenses/>.
double val_reg_b = GET_FPR(reg_b); \
double val_reg_c = GET_FPR(reg_c);
#endif // PPC_MACROS_H
#endif // PPC_MACROS_H

18
cpu/ppc/ppcopcodes.cpp
View File

@ -647,16 +647,15 @@ template void dppc_interpreter::ppc_sraw<RC1>();
template <field_rc rec>
void dppc_interpreter::ppc_srawi() {
ppc_grab_regssa(ppc_cur_instruction);
uint32_t shift = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
// clear XER[CA] by default
ppc_state.spr[SPR::XER] &= ~XER::CA;
if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & ((1U << shift) - 1)))
if ((ppc_result_d & 0x80000000UL) && (ppc_result_d & ((1U << rot_sh) - 1)))
ppc_state.spr[SPR::XER] |= XER::CA;
ppc_result_a = int32_t(ppc_result_d) >> shift;
ppc_result_a = int32_t(ppc_result_d) >> rot_sh;
if (rec)
ppc_changecrf0(ppc_result_a);
@ -675,8 +674,7 @@ static inline uint32_t rot_mask(unsigned rot_mb, unsigned rot_me) {
}
void dppc_interpreter::ppc_rlwimi() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
uint32_t mask = rot_mask(rot_mb, rot_me);
@ -690,8 +688,7 @@ void dppc_interpreter::ppc_rlwimi() {
}
void dppc_interpreter::ppc_rlwinm() {
ppc_grab_regssa(ppc_cur_instruction);
unsigned rot_sh = (ppc_cur_instruction >> 11) & 0x1F;
ppc_grab_regssash(ppc_cur_instruction);
unsigned rot_mb = (ppc_cur_instruction >> 6) & 0x1F;
unsigned rot_me = (ppc_cur_instruction >> 1) & 0x1F;
uint32_t mask = rot_mask(rot_mb, rot_me);
@ -1820,10 +1817,9 @@ void dppc_interpreter::ppc_stswi() {
#ifdef CPU_PROFILING
num_int_stores++;
#endif
ppc_grab_regssa(ppc_cur_instruction);
ppc_grab_regssash(ppc_cur_instruction);
ppc_effective_address = reg_a ? ppc_result_a : 0;
uint32_t grab_inb = (ppc_cur_instruction >> 11) & 0x1F;
grab_inb = grab_inb ? grab_inb : 32;
uint32_t grab_inb = rot_sh ? rot_sh : 32;
while (grab_inb >= 4) {
mmu_write_vmem<uint32_t>(ppc_effective_address, ppc_state.gpr[reg_s]);