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https://github.com/dingusdev/dingusppc.git
synced 2025-04-02 23:29:52 +00:00
ppcopcodes: Fixes for SPRs.
- Rename DEC to DEC_S and add DEC_U. - MQ, RTCL_U, RTCU_U, and DEC_U should cause an illegal instruction program exception for non-MPC601 CPUs. The exception handler of classic Mac OS uses this to emulate the instruction. - For mtspr, the SPRs RTCL_U, RTCU_U, and DEC_U are treated as no-op on MPC601. - For debugging, use the supervisor instead of the user SPR number as the index for storing the values for RTC, TB, and DEC. - For debugging, RTC, TB, and DEC should be updated after each access. Previously, mfspr and mtspr would only update the half of RTC and TB that was being accessed instead of both halves.
This commit is contained in:
joevt
dingusdev
parent
67a5c39b1c
commit
cb88bab67d
@ -85,17 +85,18 @@ extern SetPRS ppc_state;
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/** symbolic names for frequently used SPRs */
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enum SPR : int {
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MQ = 0,
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MQ = 0, // MQ (601)
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XER = 1,
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RTCU_U = 4, // user RTCU
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RTCL_U = 5, // user RTCL
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RTCU_U = 4, // user mode RTCU (601)
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RTCL_U = 5, // user mode RTCL (601)
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DEC_U = 6, // user mode decrementer (601)
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LR = 8,
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CTR = 9,
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DSISR = 18,
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DAR = 19,
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RTCU_S = 20, // supervisor RTCU
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RTCL_S = 21, // supervisor RTCL
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DEC = 22, // decrementer
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RTCU_S = 20, // supervisor RTCU (601)
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RTCL_S = 21, // supervisor RTCL (601)
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DEC_S = 22, // supervisor decrementer
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SDR1 = 25,
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SRR0 = 26,
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SRR1 = 27,
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@ -864,8 +864,8 @@ void ppc_cpu_init(MemCtrlBase* mem_ctrl, uint32_t cpu_version, bool include_601,
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/* MPC601 sets MSR[ME] bit during hard reset / Power-On */
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ppc_state.msr = (MSR::ME + MSR::IP);
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} else {
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ppc_state.msr = MSR::IP;
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ppc_state.spr[SPR::DEC] = 0xFFFFFFFFUL;
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ppc_state.msr = MSR::IP;
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ppc_state.spr[SPR::DEC_S] = 0xFFFFFFFFUL;
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}
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ppc_mmu_init();
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@ -885,10 +885,10 @@ void print_fprs() {
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}
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static map<string, int> SPRName2Num = {
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{"XER", SPR::XER}, {"LR", SPR::LR}, {"CTR", SPR::CTR},
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{"DEC", SPR::DEC}, {"PVR", SPR::PVR}, {"SPRG0", SPR::SPRG0},
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{"SPRG1", SPR::SPRG1}, {"SPRG2", SPR::SPRG2}, {"SPRG3", SPR::SPRG3},
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{"SRR0", SPR::SRR0}, {"SRR1", SPR::SRR1}, {"IBAT0U", 528},
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{"XER", SPR::XER}, {"LR", SPR::LR}, {"CTR", SPR::CTR},
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{"DEC", SPR::DEC_S}, {"PVR", SPR::PVR}, {"SPRG0", SPR::SPRG0},
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{"SPRG1", SPR::SPRG1}, {"SPRG2", SPR::SPRG2}, {"SPRG3", SPR::SPRG3},
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{"SRR0", SPR::SRR0}, {"SRR1", SPR::SRR1}, {"IBAT0U", 528},
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{"IBAT0L", 529}, {"IBAT1U", 530}, {"IBAT1L", 531},
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{"IBAT2U", 532}, {"IBAT2L", 533}, {"IBAT3U", 534},
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{"IBAT3L", 535}, {"DBAT0U", 536}, {"DBAT0L", 537},
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@ -897,9 +897,9 @@ static map<string, int> SPRName2Num = {
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{"HID0", SPR::HID0}, {"HID1", SPR::HID1}, {"IABR", 1010},
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{"DABR", 1013}, {"L2CR", 1017}, {"ICTC", 1019},
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{"THRM1", 1020}, {"THRM2", 1021}, {"THRM3", 1022},
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{"PIR", 1023}, {"TBL", SPR::TBL_U}, {"TBU", SPR::TBU_U},
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{"SDR1", SPR::SDR1}, {"MQ", SPR::MQ}, {"RTCU", SPR::RTCU_U},
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{"RTCL", SPR::RTCL_U}, {"DSISR", SPR::DSISR}, {"DAR", SPR::DAR},
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{"PIR", 1023}, {"TBL", SPR::TBL_S}, {"TBU", SPR::TBU_S},
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{"SDR1", SPR::SDR1}, {"MQ", SPR::MQ}, {"RTCU", SPR::RTCU_S},
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{"RTCL", SPR::RTCL_S}, {"DSISR", SPR::DSISR}, {"DAR", SPR::DAR},
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{"MMCR0", SPR::MMCR0}, {"PMC1", SPR::PMC1}, {"PMC2", SPR::PMC2},
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{"SDA", SPR::SDA}, {"SIA", SPR::SIA}, {"MMCR1", SPR::MMCR1}
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};
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@ -974,6 +974,13 @@ uint64_t reg_op(string& reg_name, uint64_t val, bool is_write) {
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reg_num_str = reg_name_u.substr(3);
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reg_num = (unsigned)stoul(reg_num_str, NULL, 0);
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if (reg_num < 1024) {
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switch (reg_num) {
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case SPR::DEC_U : reg_num = SPR::DEC_S ; break;
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case SPR::RTCL_U : reg_num = SPR::RTCL_S ; break;
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case SPR::RTCU_U : reg_num = SPR::RTCU_S ; break;
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case SPR::TBL_U : reg_num = SPR::TBL_S ; break;
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case SPR::TBU_U : reg_num = SPR::TBU_S ; break;
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}
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if (is_write)
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ppc_state.spr[reg_num] = (uint32_t)val;
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return ppc_state.spr[reg_num];
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@ -898,20 +898,42 @@ void dppc_interpreter::ppc_mfspr() {
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}
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switch (ref_spr) {
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case SPR::MQ:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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ppc_state.gpr[reg_d] = ppc_state.spr[ref_spr];
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break;
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case SPR::RTCL_U:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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calc_rtcl_value();
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ppc_state.spr[SPR::RTCL_U] = rtc_lo & 0x3FFFFF80UL;
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ppc_state.gpr[reg_d] =
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ppc_state.spr[SPR::RTCL_S] = rtc_lo & 0x3FFFFF80UL;
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ppc_state.spr[SPR::RTCU_S] = rtc_hi;
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break;
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case SPR::RTCU_U:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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calc_rtcl_value();
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ppc_state.spr[SPR::RTCU_U] = rtc_hi;
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ppc_state.gpr[reg_d] =
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ppc_state.spr[SPR::RTCU_S] = rtc_hi;
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ppc_state.spr[SPR::RTCL_S] = rtc_lo;
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break;
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case SPR::DEC:
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ppc_state.spr[SPR::DEC] = calc_dec_value();
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case SPR::DEC_U:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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// fallthrough
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case SPR::DEC_S:
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ppc_state.gpr[reg_d] = ppc_state.spr[SPR::DEC_S] = calc_dec_value();
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break;
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default:
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// FIXME: Unknown SPR should be noop or illegal instruction.
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ppc_state.gpr[reg_d] = ppc_state.spr[ref_spr];
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}
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ppc_state.gpr[reg_d] = ppc_state.spr[ref_spr];
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}
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void dppc_interpreter::ppc_mtspr() {
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@ -927,38 +949,54 @@ void dppc_interpreter::ppc_mtspr() {
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}
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}
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if (ref_spr == SPR::PVR || (
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ref_spr == SPR::MQ && !is_601
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)) { // prevent writes to the read-only registers
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return;
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}
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uint32_t val = ppc_state.gpr[reg_d];
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ppc_state.spr[ref_spr] = val;
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switch (ref_spr) {
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case SPR::MQ:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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ppc_state.spr[ref_spr] = val;
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break;
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case SPR::RTCL_U:
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case SPR::RTCU_U:
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case SPR::DEC_U:
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if (!is_601) {
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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}
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break;
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case SPR::XER:
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ppc_state.spr[ref_spr] = val & 0xe000ff7f;
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break;
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case SPR::SDR1:
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ppc_state.spr[ref_spr] = val;
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mmu_pat_ctx_changed(); // adapt to SDR1 changes
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break;
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case SPR::RTCL_S:
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calc_rtcl_value();
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rtc_lo = val & 0x3FFFFF80UL;
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ppc_state.spr[RTCL_S] = rtc_lo = val & 0x3FFFFF80UL;
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ppc_state.spr[RTCU_S] = rtc_hi;
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break;
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case SPR::RTCU_S:
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calc_rtcl_value();
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rtc_hi = val;
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ppc_state.spr[RTCL_S] = rtc_lo;
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ppc_state.spr[RTCU_S] = rtc_hi = val;
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break;
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case SPR::DEC:
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case SPR::DEC_S:
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ppc_state.spr[DEC_S] = val;
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update_decrementer(val);
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break;
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case SPR::TBL_S:
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update_timebase(0xFFFFFFFF00000000ULL, val);
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ppc_state.spr[TBL_S] = val;
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ppc_state.spr[TBU_S] = tbr_wr_value >> 32;
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break;
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case SPR::TBU_S:
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update_timebase(0x00000000FFFFFFFFULL, uint64_t(val) << 32);
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ppc_state.spr[TBL_S] = (uint32_t)tbr_wr_value;
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ppc_state.spr[TBU_S] = val;
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break;
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case SPR::PVR:
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break;
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case 528:
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case 529:
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@ -968,6 +1006,7 @@ void dppc_interpreter::ppc_mtspr() {
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case 533:
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case 534:
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case 535:
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ppc_state.spr[ref_spr] = val;
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ibat_update(ref_spr);
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break;
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case 536:
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@ -978,7 +1017,11 @@ void dppc_interpreter::ppc_mtspr() {
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case 541:
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case 542:
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case 543:
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ppc_state.spr[ref_spr] = val;
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dbat_update(ref_spr);
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default:
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// FIXME: Unknown SPR should be noop or illegal instruction.
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ppc_state.spr[ref_spr] = val;
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}
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}
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@ -990,10 +1033,14 @@ void dppc_interpreter::ppc_mftb() {
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switch (ref_spr) {
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case SPR::TBL_U:
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ppc_state.gpr[reg_d] = uint32_t(tbr_value);
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ppc_state.gpr[reg_d] =
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ppc_state.spr[TBL_S] = uint32_t(tbr_value);
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ppc_state.spr[TBU_S] = uint32_t(tbr_value >> 32);
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break;
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case SPR::TBU_U:
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ppc_state.gpr[reg_d] = uint32_t(tbr_value >> 32);
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ppc_state.gpr[reg_d] =
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ppc_state.spr[TBU_S] = uint32_t(tbr_value >> 32);
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ppc_state.spr[TBL_S] = uint32_t(tbr_value);
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break;
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default:
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ppc_exception_handler(Except_Type::EXC_PROGRAM, Exc_Cause::ILLEGAL_OP);
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