From cf9237f7d62142c628aa64472d9d8ba86f1ef43d Mon Sep 17 00:00:00 2001 From: joevt Date: Mon, 30 Oct 2023 16:58:20 -0700 Subject: [PATCH] control: Fixes. - Fix video vram endianness. It should behave like RAM. - Add read for registers ENABLE, INT_STATUS, INT_ENABLE. - Add write for registers CNTTST, INT_ENABLE. - Add support for 16bpp and 32bpp. - Add vbl interrupt. --- devices/video/control.cpp | 495 ++++++++++++++++++++++++++++++-------- devices/video/control.h | 78 +++--- 2 files changed, 445 insertions(+), 128 deletions(-) diff --git a/devices/video/control.cpp b/devices/video/control.cpp index 4c2612c..b047cf3 100644 --- a/devices/video/control.cpp +++ b/devices/video/control.cpp @@ -31,6 +31,7 @@ along with this program. If not, see . Kudos to joevt#3510 for his precious technical help and HW hacking. */ +#include #include #include #include @@ -43,6 +44,13 @@ along with this program. If not, see . #include +namespace loguru { + enum : Verbosity { + Verbosity_RADACAL = loguru::Verbosity_INFO, + Verbosity_CONTROL = loguru::Verbosity_INFO + }; +} + ControlVideo::ControlVideo() : PCIDevice("Control-Video"), VideoCtrlBase(640, 480) { @@ -76,7 +84,7 @@ ControlVideo::ControlVideo() I2CBus* i2c_bus = dynamic_cast(gMachineObj->get_comp_by_type(HWCompType::I2C_HOST)); i2c_bus->register_device(0x28, this->clk_gen.get()); - // register RaDACal with the I/O controller + // attach IOBus Device #2 0xF301B000 ; register RaDACal with the I/O controller GrandCentral* gc_obj = dynamic_cast(gMachineObj->get_comp_by_name("GrandCentral")); gc_obj->attach_iodevice(1, this); @@ -110,52 +118,58 @@ void ControlVideo::notify_bar_change(int bar_num) } } -uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size) -{ - uint32_t result = 0; - - if (rgn_start == this->vram_base) { - if (offset >= 0x800000) { - return read_mem_rev(&this->vram_ptr[offset - 0x800000], size); - } else { - LOG_F(INFO, "Control: little-endian access to VRAM not supported yet"); - return 0; - } +static const char * get_name_controlreg(int offset) { + switch (offset >> 4) { + case ControlRegs::CUR_LINE : return "CUR_LINE"; + case ControlRegs::VFPEQ : return "VFPEQ"; + case ControlRegs::VFP : return "VFP"; + case ControlRegs::VAL : return "VAL"; + case ControlRegs::VBP : return "VBP"; + case ControlRegs::VBPEQ : return "VBPEQ"; + case ControlRegs::VSYNC : return "VSYNC"; + case ControlRegs::VHLINE : return "VHLINE"; + case ControlRegs::PIPED : return "PIPED"; + case ControlRegs::HPIX : return "HPIX"; + case ControlRegs::HFP : return "HFP"; + case ControlRegs::HAL : return "HAL"; + case ControlRegs::HBWAY : return "HBWAY"; + case ControlRegs::HSP : return "HSP"; + case ControlRegs::HEQ : return "HEQ"; + case ControlRegs::HLFLN : return "HLFLN"; + case ControlRegs::HSERR : return "HSERR"; + case ControlRegs::CNTTST : return "CNTTST"; + case ControlRegs::TEST : return "TEST"; + case ControlRegs::GBASE : return "GBASE"; + case ControlRegs::ROW_WORDS : return "ROW_WORDS"; + case ControlRegs::MON_SENSE : return "MON_SENSE"; + case ControlRegs::ENABLE : return "ENABLE"; + case ControlRegs::GSC_DIVIDE : return "GSC_DIVIDE"; + case ControlRegs::REFRESH_COUNT : return "REFRESH_COUNT"; + case ControlRegs::INT_ENABLE : return "INT_ENABLE"; + case ControlRegs::INT_STATUS : return "INT_STATUS"; + default : return "unknown"; } - - if (rgn_start == this->regs_base) { - switch (offset >> 4) { - case ControlRegs::TEST: - result = this->test; - break; - case ControlRegs::MON_SENSE: - result = this->cur_mon_id << 6; - break; - default: - LOG_F(INFO, "read from 0x%08X:0x%08X", rgn_start, offset); - } - - return BYTESWAP_32(result); - } - - return 0; } -void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) +uint32_t ControlVideo::read(uint32_t rgn_start, uint32_t offset, int size) { if (rgn_start == this->vram_base) { if (offset >= 0x800000) { - write_mem_rev(&this->vram_ptr[offset - 0x800000], value, size); - } else { - LOG_F(INFO, "Control: little-endian access to VRAM not supported yet"); + return read_mem(&this->vram_ptr[offset - 0x800000], size); } - return; + + LOG_F(INFO, "Control: little-endian access to VRAM not supported yet"); + return 0; } - if (rgn_start == this->regs_base) { - value = BYTESWAP_32(value); + uint32_t value; + if (rgn_start == this->regs_base) { switch (offset >> 4) { + case ControlRegs::CUR_LINE: + value = 0; // current active video line should relate this to refresh rate + LOG_F(ERROR, "Control: read CUR_LINE %03x.%c", offset, SIZE_ARG(size)); + break; case ControlRegs::VFPEQ: case ControlRegs::VFP: case ControlRegs::VAL: @@ -172,24 +186,162 @@ void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in case ControlRegs::HEQ: case ControlRegs::HLFLN: case ControlRegs::HSERR: - this->swatch_params[(offset >> 4) - 1] = value; + value = this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ]; + LOG_F(CONTROL, "Control: read %s %03x.%c = %0*x", get_name_controlreg(offset), offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::CNTTST: + value = 0; + LOG_F(ERROR, "Control: read CNTTST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); break; case ControlRegs::TEST: + value = this->test; + LOG_F(CONTROL, "Control: read TEST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::GBASE: + value = this->fb_base; + LOG_F(CONTROL, "Control: read GBASE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::ROW_WORDS: + value = this->row_words; + LOG_F(CONTROL, "Control: read ROW_WORDS %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::MON_SENSE: + value = this->cur_mon_id << 6; + LOG_F(CONTROL, "Control: read MON_SENSE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::ENABLE: + value = this->flags; + LOG_F(CONTROL, "Control: read ENABLE %03x.%c", offset, SIZE_ARG(size)); + break; + case ControlRegs::GSC_DIVIDE: + value = this->clock_divider; + LOG_F(CONTROL, "Control: read GSC_DIVIDE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::REFRESH_COUNT: + value = 0; + LOG_F(ERROR, "Control: read CNTTST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::INT_STATUS: + value = this->int_status; + if (value != this->last_int_status) { + LOG_F(CONTROL, "Control: read (previous %d times) INT_STATUS %03x.%c = %0*x", last_int_status_read_count, offset, SIZE_ARG(size), size * 2, value); + this->last_int_status = value; + this->last_int_status_read_count = 0; + } + else { + this->last_int_status_read_count++; + + } + break; + case ControlRegs::INT_ENABLE: + value = this->int_enable; + LOG_F(CONTROL, "Control: read INT_ENABLE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + default: + LOG_F(ERROR, "Control: read %03x.%c", offset, SIZE_ARG(size)); + value = 0; + } + + AccessDetails details; + details.size = size; + details.offset = offset & 3; + uint32_t result = pci_conv_rd_data(value, value, details); + if ((offset & 3) || (size != 4)) { + LOG_F(WARNING, "Control: read %03x.%c = %08x -> %0*x", offset, SIZE_ARG(size), value, size * 2, result); + //dump_backtrace(); + } + + return result; + } + + return 0; +} + +void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, int size) +{ + if (rgn_start == this->vram_base) { + if (offset >= 0x800000) { + write_mem(&this->vram_ptr[offset - 0x800000], value, size); + } else { + LOG_F(INFO, "Control: little-endian access to VRAM not supported yet"); + } + return; + } + + if (rgn_start == this->regs_base) { + value = BYTESWAP_32(value); + + switch (offset >> 4) { + case ControlRegs::PIPED: + this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0x3ff; + if (value & ~0x3ff) + LOG_F(ERROR, "Control: write PIPED %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write PIPED %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + if (this->display_enabled) { + this->enable_display(); + } + break; + case ControlRegs::HEQ: + this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0xff; + if (value & ~0xff) + LOG_F(ERROR, "Control: write HEQ %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write HEQ %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + if (this->display_enabled) { + this->enable_display(); + } + break; + case ControlRegs::VFPEQ: + case ControlRegs::VFP: + case ControlRegs::VAL: + case ControlRegs::VBP: + case ControlRegs::VBPEQ: + case ControlRegs::VSYNC: + case ControlRegs::VHLINE: + case ControlRegs::HPIX: + case ControlRegs::HFP: + case ControlRegs::HAL: + case ControlRegs::HBWAY: + case ControlRegs::HSP: + case ControlRegs::HLFLN: + case ControlRegs::HSERR: + this->swatch_params[(offset >> 4) - ControlRegs::VFPEQ] = value & 0xfff; + if (value & ~0xfff) + LOG_F(ERROR, "Control: write %s %03x.%c = %0*x", get_name_controlreg(offset), offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write %s %03x.%c = %0*x", get_name_controlreg(offset), offset, SIZE_ARG(size), size * 2, value); + if (this->display_enabled) { + this->enable_display(); + } + break; + case ControlRegs::CNTTST: + if (value != 0) + LOG_F(ERROR, "Control: write CNTTST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write CNTTST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + break; + case ControlRegs::TEST: + if (value & ~0x7ff) + LOG_F(ERROR, "Control: write TEST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write TEST %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + value &= 0x7ff; if (this->test != value) { - if ((this->test & ~TEST_STROBE) != (value & ~TEST_STROBE)) { + if ((this->test & ~TEST_STROBE & 0x400) != (value & ~TEST_STROBE & 0x400)) { this->test = value; this->test_shift = 0; - LOG_F(9, "New TEST value: 0x%08X", this->test); + LOG_F(CONTROL, "New TEST value: 0x%08X", this->test); } else { - LOG_F(9, "TEST strobe bit flipped, new value: 0x%08X", value); + LOG_F(CONTROL, "TEST strobe bit flipped, new value: 0x%08X", value); this->test = value; if (++this->test_shift >= 3) { - LOG_F(9, "Received TEST reg value: 0x%08X", this->test & ~TEST_STROBE); + LOG_F(CONTROL, "Received TEST reg value: 0x%08X", this->test & ~TEST_STROBE); if ((this->test ^ this->prev_test) & 0x400) { - if (this->test & 0x400) { - this->disable_display(); - } else { + if ((this->display_enabled = !(this->test & 0x400))) { this->enable_display(); + } else { + this->disable_display(); } this->prev_test = this->test; } @@ -198,37 +350,73 @@ void ControlVideo::write(uint32_t rgn_start, uint32_t offset, uint32_t value, in } break; case ControlRegs::GBASE: - this->fb_base = value; + if (value & ~0x3fffe0) + LOG_F(ERROR, "Control: write GBASE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write GBASE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + this->fb_base = value & 0x3fffe0; + if (this->display_enabled) { + this->enable_display(); + } break; case ControlRegs::ROW_WORDS: - this->row_words = value; + if (value & ~0x7fe0) + LOG_F(ERROR, "Control: write ROW_WORDS %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write ROW_WORDS %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + this->row_words = value & 0x7fe0; + if (this->display_enabled) { + this->enable_display(); + } break; case ControlRegs::MON_SENSE: - LOG_F(9, "Control: monitor sense written with 0x%X", value); + if (value & ~0x1FF) + LOG_F(ERROR, "Control: write MON_SENSE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write MON_SENSE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); value = (value >> 3) & 7; this->cur_mon_id = this->display_id->read_monitor_sense(value & 7, value ^ 7); break; case ControlRegs::ENABLE: - this->flags = value; + if (value & ~0xfff) + LOG_F(ERROR, "Control: write ENABLE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write ENABLE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + this->flags = value & -0xfff; break; case ControlRegs::GSC_DIVIDE: - this->clock_divider = value; + if (value & ~0x3) + LOG_F(ERROR, "Control: write GSC_DIVIDE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write GSC_DIVIDE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + this->clock_divider = value & 3; + if (this->display_enabled) { + this->enable_display(); + } break; case ControlRegs::REFRESH_COUNT: - LOG_F(INFO, "Control: refresh count set to 0x%08X", value); + if (value & ~0x3ff) + LOG_F(ERROR, "Control: write REFRESH_COUNT %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else + LOG_F(CONTROL, "Control: write REFRESH_COUNT %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); break; case ControlRegs::INT_ENABLE: - this->int_enable = value; + if (value & ~0xc) + LOG_F(ERROR, "Control: write INT_ENABLE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + else { + //LOG_F(CONTROL, "Control: write INT_ENABLE %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); + } + this->int_enable = value & 0xf; // alternates between 0x04 and 0x0c break; default: - LOG_F(INFO, "write 0x%08X to 0x%08X:0x%08X", value, rgn_start, offset); + LOG_F(ERROR, "Control: write %03x.%c = %0*x", offset, SIZE_ARG(size), size * 2, value); } } } void ControlVideo::enable_display() { - int new_width, new_height, hori_blank, vert_blank, clk_divisor; + int new_width, new_height, clk_divisor; // get pixel frequency from Athens this->pixel_clock = this->clk_gen->get_dot_freq(); @@ -243,64 +431,71 @@ void ControlVideo::enable_display() new_width *= clk_divisor; new_height >>= 1; // FIXME: assume non-interlaced mode for now - if (new_width != this->active_width || new_height != this->active_height) { - LOG_F(WARNING, "Display window resizing not implemented yet!"); - } - this->active_width = new_width; this->active_height = new_height; - // get pixel depth from RaDACal - switch ((this->rad_cr >> 2) & 3) { - case 0: - this->pixel_depth = 8; - break; - case 1: - this->pixel_depth = 16; - break; - case 2: - this->pixel_depth = 32; - break; - default: - ABORT_F("Invalid RaDACal pixel depth code!"); - } - - if (pixel_depth == 8) { - this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { - this->convert_frame_8bpp_indexed(dst_buf, dst_pitch); - }; - } else { - ABORT_F("Control: 16bpp and 32bpp formats not supported yet!"); - } - // set framebuffer parameters this->fb_ptr = &this->vram_ptr[this->fb_base]; this->fb_pitch = this->row_words; + // get pixel depth from RaDACal + switch ((this->rad_cr >> 2) & 3) { + case 0: + this->pixel_depth = 8; + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_8bpp_indexed(dst_buf, dst_pitch); + }; + break; + case 1: + this->pixel_depth = 16; + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_15bpp(dst_buf, dst_pitch); + }; + break; + case 2: + this->pixel_depth = 32; + this->fb_ptr += 16; + this->convert_fb_cb = [this](uint8_t *dst_buf, int dst_pitch) { + this->convert_frame_32bpp_BE(dst_buf, dst_pitch); + }; + break; + default: + LOG_F(ERROR, "RaDACal: Invalid pixel depth code!"); + } + // calculate display refresh rate - hori_blank = swatch_params[ControlRegs::HAL-1] + + this->hori_blank = swatch_params[ControlRegs::HAL-1] + (swatch_params[ControlRegs::HSP-1] - swatch_params[ControlRegs::HFP-1]); - hori_blank *= clk_divisor; + this->hori_blank *= clk_divisor; - vert_blank = swatch_params[ControlRegs::VAL-1] + + this->vert_blank = swatch_params[ControlRegs::VAL-1] + (swatch_params[ControlRegs::VSYNC-1] - swatch_params[ControlRegs::VFP-1]); - vert_blank >>= 1; + this->vert_blank >>= 1; - this->refresh_rate = (double)(this->pixel_clock) / (new_width + hori_blank) - / (new_height + vert_blank); - LOG_F(INFO, "Control: refresh rate set to %f Hz", this->refresh_rate); + this->hori_total = this->hori_blank + new_width; + this->vert_total = this->vert_blank + new_height; this->stop_refresh_task(); // set up periodic timer for display updates - this->start_refresh_task(); + if (this->active_width > 0 && this->active_height > 0 && this->pixel_clock > 0) { + this->refresh_rate = (double)(this->pixel_clock) / (this->hori_total * this->vert_total); + LOG_F(INFO, "Control: refresh rate set to %f Hz", this->refresh_rate); - this->blank_on = false; + this->start_refresh_task(); - LOG_F(INFO, "Control: display enabled"); - this->crtc_on = true; + this->blank_on = false; + + LOG_F(CONTROL, "Control: display enabled"); + this->crtc_on = true; + } + else { + LOG_F(CONTROL, "Control: display not enabled"); + this->blank_on = true; + this->crtc_on = false; + } } void ControlVideo::disable_display() @@ -309,42 +504,125 @@ void ControlVideo::disable_display() LOG_F(INFO, "Control: display disabled"); } +void ControlVideo::draw_hw_cursor(uint8_t *dst_buf, int dst_pitch) { + uint8_t *src_row = &this->vram_ptr[this->fb_base]; + uint8_t *dst_row = dst_buf; + int cur_height = this->active_height; + dst_pitch -= 32 * 4; + int src_pitch = this->fb_pitch - 16; + + uint32_t color[16]; + for (int c = 0; c < 16; c++) { + color[c] = (this->cursor_data[c*3] << 16) | (this->cursor_data[c*3 + 1] << 8) | (this->cursor_data[c*3 + 2]); + } + + for (int h = 0; h < cur_height; h++) { + for (int x = 0; x < 2; x++) { + uint64_t px16 = READ_QWORD_BE_A(src_row); + for (int p = 0; p < 16; p++) { + int c = px16 >> 60; + switch (c) { + case 0: + // transparent + break; + case 1: + // 1's complement + WRITE_DWORD_LE_A(dst_row, READ_DWORD_LE_A(dst_row) ^ 0xffffff); + break; + case 8: + WRITE_DWORD_LE_A(dst_row, color[0]); + break; + case 9: + WRITE_DWORD_LE_A(dst_row, color[1]); + break; + default: + WRITE_DWORD_LE_A(dst_row, (c << 16) | (c << 8) | c); + break; + } + px16 <<= 4; + dst_row += 4; + } + src_row += 8; + } + dst_row += dst_pitch; + src_row += src_pitch; + } +} + // ========================== RaDACal related stuff ========================== uint16_t ControlVideo::iodev_read(uint32_t address) { - LOG_F(INFO, "RaDACal: read from 0x%08X", address); - return 0; -} + uint16_t result; + switch (address) { + case RadacalRegs::MULTI: + switch (this->rad_addr) { + case RadacalRegs::MISC_CTRL: + result = this->rad_cr; + LOG_F(RADACAL, "RaDACal: read MISC_CTRL = 0x%02x", result); + break; +/* + case RadacalRegs::CLOCK_SELECT: + result = this->dac_clock_select; + LOG_F(RADACAL, "RaDACal: read CLOCK_SELECT = 0x%02x", result); + break; + case RadacalRegs::DAC_TYPE: + result = this->dac_type; + LOG_F(RADACAL, "RaDACal: read DAC_TYPE = 0x%02x", result); + break; +*/ + default: + LOG_F(ERROR, "RaDACal: read MULTI 0x%02x", this->rad_addr); + result = 0; + } + break; + case RadacalRegs::CLUT_DATA: + LOG_F(ERROR, "RaDACal: read CLUT_DATA 0x%02x", rad_addr); + result = 0; + break; + default: + LOG_F(ERROR, "RaDACal: read 0x%02x", address); + result = 0; + } + return result; +} void ControlVideo::iodev_write(uint32_t address, uint16_t value) { switch (address) { case RadacalRegs::ADDRESS: + LOG_F(RADACAL, "RaDACal: write ADDRESS = 0x%02x", value); this->rad_addr = value; this->comp_index = 0; break; case RadacalRegs::CURSOR_DATA: + LOG_F(RADACAL, "RaDACal: write CURSOR_DATA 0x%02x = 0x%02x", this->rad_addr, value); + this->cursor_data[(this->rad_addr++) % 24] = value; break; case RadacalRegs::MULTI: switch (this->rad_addr) { case RadacalRegs::CURSOR_POS_HI: - this->rad_cur_pos_hi = value; + LOG_F(RADACAL, "RaDACal: write CURSOR_POS_HI = 0x%02x", value); + this->rad_cur_pos = (value << 8) | (this->rad_cur_pos & 0x00ff); break; case RadacalRegs::CURSOR_POS_LO: - this->rad_cur_pos_lo = value; + LOG_F(RADACAL, "RaDACal: write CURSOR_POS_LO = 0x%02x", value); + this->rad_cur_pos = (this->rad_cur_pos & 0xff00) | (value & 0x00ff); break; case RadacalRegs::MISC_CTRL: + LOG_F(RADACAL, "RaDACal: write MISC_CTRL = 0x%02x", value); this->rad_cr = value; break; case RadacalRegs::DBL_BUF_CTRL: + LOG_F(RADACAL, "RaDACal: write DBL_BUF_CTRL = 0x%02x", value); this->rad_dbl_buf_cr = value; break; default: - LOG_F(ERROR, "Unsupported RaDACal register %d", this->rad_addr); + LOG_F(ERROR, "RaDACal: write MULTI 0x%02x = 0x%02x", this->rad_addr, value); } break; case RadacalRegs::CLUT_DATA: + LOG_F(RADACAL, "RaDACal: write CLUT_DATA 0x%02x = 0x%02x", this->rad_addr, value); this->clut_color[this->comp_index++] = value; if (this->comp_index >= 3) { this->set_palette_color(this->rad_addr, clut_color[0], @@ -354,10 +632,31 @@ void ControlVideo::iodev_write(uint32_t address, uint16_t value) } break; default: - LOG_F(INFO, "RaDACal: write to non-existent register at 0x%08X", address); + LOG_F(ERROR, "RaDACal: write 0x%02x = 0x%02x", address, value); } } +int ControlVideo::device_postinit() +{ + this->int_ctrl = dynamic_cast( + gMachineObj->get_comp_by_type(HWCompType::INT_CTRL)); + this->irq_id = this->int_ctrl->register_dev_int(IntSrc::CONTROL); + + this->vbl_cb = [this](uint8_t irq_line_state) { + if (irq_line_state) + this->int_status |= 0xc; + else + this->int_status &= ~0xc; + + if (this->crtc_on && (4 & this->int_enable)) { + //this->pci_interrupt(irq_line_state); + this->int_ctrl->ack_int(this->irq_id, irq_line_state); + } + }; + + return 0; +} + // ========================== Device registry stuff ========================== static const PropMap Control_Properties = { diff --git a/devices/video/control.h b/devices/video/control.h index 89aa376..a29fa94 100644 --- a/devices/video/control.h +++ b/devices/video/control.h @@ -33,39 +33,46 @@ along with this program. If not, see . #include #include -#define TEST_STROBE (1 << 3) // strobe bit +#define FB_BLANK_VSYNC (3 << 0) // FB_BLANK_VSYNC_SUSPEND = &= ~0x03 +#define FB_BLANK_HSYNC (3 << 4) // FB_BLANK_HSYNC_SUSPEND = &= ~0x30 + // FB_BLANK_POWERDOWN = &= ~0x33 +#define FB_BLANK_NORMAL (1 << 10) // = |= 0x400 +#define TEST_STROBE (1 << 3) // strobe bit +#define FB_DISABLE (1 << 10) // disable bit = &= ~0x400 // Memory-mapped registers. namespace ControlRegs { enum ControlRegs : int { - CUR_LINE = 0x00, // current active video line - VFPEQ = 0x01, - VFP = 0x02, - VAL = 0x03, // vertical active line - VBP = 0x04, - VBPEQ = 0x05, // begin of th vertical back porch with equalization - VSYNC = 0x06, - VHLINE = 0x07, - PIPED = 0x08, - HPIX = 0x09, - HFP = 0x0A, - HAL = 0x0B, // horizontal active line - HBWAY = 0x0C, - HSP = 0x0D, - HEQ = 0x0E, - HLFLN = 0x0F, - HSERR = 0x10, - CNTTST = 0x11, // Swatch counter test - TEST = 0x12, - GBASE = 0x13, // Graphics base address - ROW_WORDS = 0x14, - MON_SENSE = 0x15, // Monitor sense control & status - ENABLE = 0x16, - GSC_DIVIDE = 0x17, // graphics clock divide count - REFRESH_COUNT = 0x18, - INT_ENABLE = 0x19, - INT_STATUS = 0x1A + // 512 bytes, repeats 8 times for 4K total. + // A register every 16 bytes, little endian, 32 bits, repeats 4 times. + CUR_LINE = 0x00, // (ro) ; current active video line + VFPEQ = 0x01, // (rw) 12 bits ; + VFP = 0x02, // (rw) 12 bits ; + VAL = 0x03, // (rw) 12 bits ; vertical active line + VBP = 0x04, // (rw) 12 bits ; + VBPEQ = 0x05, // (rw) 12 bits ; vertical back porch with equalization + VSYNC = 0x06, // (rw) 12 bits ; + VHLINE = 0x07, // (rw) 12 bits ; + PIPED = 0x08, // (rw) 10 bits ; + HPIX = 0x09, // (rw) 12 bits ; + HFP = 0x0A, // (rw) 12 bits ; + HAL = 0x0B, // (rw) 12 bits ; horizontal active line + HBWAY = 0x0C, // (rw) 12 bits ; + HSP = 0x0D, // (rw) 12 bits ; + HEQ = 0x0E, // (rw) 8 bits ; + HLFLN = 0x0F, // (rw) 12 bits ; + HSERR = 0x10, // (rw) 12 bits ; + CNTTST = 0x11, // (rw) 12 bits ; Swatch counter test + TEST = 0x12, // (rw) 11 bits ; ctrl + GBASE = 0x13, // (rw) 22 bits, 32 byte aligned ; Graphics base address + ROW_WORDS = 0x14, // (rw) 15 bits, 32 byte aligned ; + MON_SENSE = 0x15, // (rw) 9 bits ; Monitor sense control & status + ENABLE = 0x16, // (rw) 12 bits ; bit 7 does something + GSC_DIVIDE = 0x17, // (rw) 2 bits ; graphics clock divide count + REFRESH_COUNT = 0x18, // (rw) 10 bits ; + INT_ENABLE = 0x19, // (rw) 4 bits ; + INT_STATUS = 0x1A, // (ro) ? bits ; }; }; // namespace ControlRegs @@ -83,6 +90,7 @@ enum RadacalRegs : uint8_t { CURSOR_POS_LO = 0x11, // cursor position, low-order byte MISC_CTRL = 0x20, // miscellaneus control bits DBL_BUF_CTRL = 0x21, // double buffer control bits + // = 0x22, // ? = 0 }; }; // namespace RadacalRegs @@ -106,10 +114,16 @@ protected: void enable_display(); void disable_display(); + // HWComponent methods + int device_postinit(); + // IobusDevice methods for RaDACal uint16_t iodev_read(uint32_t address); void iodev_write(uint32_t address, uint16_t value); + // HW cursor support + void draw_hw_cursor(uint8_t *dst_buf, int dst_pitch); + private: std::unique_ptr display_id; std::unique_ptr clk_gen; @@ -122,6 +136,7 @@ private: uint32_t regs_base = 0; uint32_t prev_test = 0x433; uint32_t test = 0; + bool display_enabled = false; uint32_t clock_divider = 0; uint32_t row_words = 0; uint32_t fb_base = 0; @@ -130,15 +145,18 @@ private: uint8_t cur_mon_id = 0; uint8_t flags = 0; uint8_t int_enable = 0; + uint8_t int_status = 0; + uint8_t last_int_status = -1; + int last_int_status_read_count = 0; // RaDACal internal state uint8_t rad_addr = 0; uint8_t rad_cr = 0; uint8_t rad_dbl_buf_cr = 0; - uint8_t rad_cur_pos_hi = 0; - uint8_t rad_cur_pos_lo = 0; + uint16_t rad_cur_pos = 0; uint8_t comp_index; uint8_t clut_color[3]; + uint8_t cursor_data[24] = { 0 }; }; #endif // CONTROL_VIDEO_H